Group : dv_base_reg_pkg::mubi_cov#(4,32'b00000000000000000000000000000101,32'b00000000000000000000000000001010)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(4,32'b00000000000000000000000000000101,32'b00000000000000000000000000001010)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

5 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi4_cov_of_tb.dut.u_lc_check_byp_en_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_tb.dut.u_lc_dft_en_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if 100.00 1 100 1 64 64




Group Instance : mubi4_cov_of_tb.dut.u_lc_check_byp_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_check_byp_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_check_byp_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_dft_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_dft_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_dft_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 606 1 T5 7 T8 1 T17 2
others[1] 640 1 T5 5 T11 1 T39 1
others[2] 639 1 T5 3 T8 1 T39 1
others[3] 1057 1 T2 1 T5 14 T10 1
false 5769 1 T1 3 T2 1 T3 1
true 8098 1 T1 3 T2 2 T3 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 278 1 T5 1 T39 1 T106 1
others[1] 258 1 T2 1 T5 1 T10 1
others[2] 296 1 T4 1 T5 1 T8 1
others[3] 498 1 T1 1 T5 9 T8 1
false 2242 1 T1 2 T4 1 T5 17
true 16539 1 T1 7 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 1632 1 T1 1 T5 6 T29 2
others[1] 1751 1 T5 14 T39 4 T157 2
others[2] 1644 1 T3 2 T5 3 T39 2
others[3] 2649 1 T4 3 T5 30 T8 2
false 13227 1 T1 5 T2 4 T3 3
true 5233 1 T4 3 T5 10 T16 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 23 1 T203 1 T368 1 T251 1
others[1] 28 1 T11 1 T157 1 T202 1
others[2] 18 1 T158 1 T208 1 T18 1
others[3] 39 1 T9 1 T13 1 T271 1
false 14815 1 T1 5 T2 5 T3 4
true 210 1 T2 1 T5 4 T8 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 937 1 T4 2 T5 9 T42 2
others[1] 953 1 T5 9 T39 3 T106 3
others[2] 928 1 T5 3 T17 3 T68 3
others[3] 1675 1 T5 9 T10 3 T39 3
false 7869 1 T2 4 T3 4 T5 83
true 7672 1 T1 5 T4 3 T5 62

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