Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.80	97.40	96.15	96.81		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	481243923	8536731	0	0
check_regwen_rd_A	481243923	3128	0	0
check_timeout_rd_A	481243923	2366	0	0
check_trigger_regwen_rd_A	481243923	3325	0	0
consistency_check_period_rd_A	481243923	3468	0	0
creator_sw_cfg_read_lock_rd_A	481243923	2699	0	0
direct_access_address_rd_A	481243923	2189	0	0
direct_access_wdata_0_rd_A	481243923	1266	0	0
direct_access_wdata_1_rd_A	481243923	1618	0	0
integrity_check_period_rd_A	481243923	3074	0	0
intr_enable_rd_A	481243923	3970	0	0
owner_sw_cfg_read_lock_rd_A	481243923	2465	0	0
rot_creator_auth_codesign_read_lock_rd_A	481243923	2789	0	0
rot_creator_auth_state_read_lock_rd_A	481243923	2474	0	0
vendor_test_read_lock_rd_A	481243923	2310	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	8536731	0	0
T13	112167	305928	0	0
T14	0	14239	0	0
T15	0	142951	0	0
T18	0	148373	0	0
T19	0	79349	0	0
T37	0	64048	0	0
T45	13874	0	0	0
T47	10412	0	0	0
T109	45178	0	0	0
T110	13998	0	0	0
T115	12744	0	0	0
T129	0	103737	0	0
T172	11772	0	0	0
T202	11638	0	0	0
T203	30115	0	0	0
T228	24422	0	0	0
T269	0	104403	0	0
T270	0	119396	0	0
T271	0	130195	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	3128	0	0
T19	545843	92	0	0
T21	0	122	0	0
T46	11502	0	0	0
T116	10299	0	0	0
T120	13157	0	0	0
T141	0	108	0	0
T204	70572	0	0	0
T231	5482	0	0	0
T257	51126	0	0	0
T269	441375	0	0	0
T276	0	106	0	0
T306	53514	0	0	0
T307	10985	0	0	0
T318	0	98	0	0
T322	0	214	0	0
T323	0	47	0	0
T324	0	10	0	0
T325	0	94	0	0
T326	0	55	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	2366	0	0
T19	545843	89	0	0
T21	0	113	0	0
T46	11502	0	0	0
T116	10299	0	0	0
T120	13157	0	0	0
T141	0	147	0	0
T204	70572	0	0	0
T231	5482	0	0	0
T257	51126	0	0	0
T269	441375	0	0	0
T276	0	141	0	0
T306	53514	0	0	0
T307	10985	0	0	0
T318	0	58	0	0
T322	0	223	0	0
T323	0	60	0	0
T324	0	39	0	0
T325	0	101	0	0
T326	0	90	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	3325	0	0
T19	545843	89	0	0
T21	0	173	0	0
T46	11502	0	0	0
T116	10299	0	0	0
T120	13157	0	0	0
T141	0	147	0	0
T204	70572	0	0	0
T231	5482	0	0	0
T257	51126	0	0	0
T269	441375	0	0	0
T276	0	96	0	0
T306	53514	0	0	0
T307	10985	0	0	0
T318	0	99	0	0
T322	0	127	0	0
T323	0	46	0	0
T324	0	34	0	0
T325	0	140	0	0
T326	0	95	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	3468	0	0
T19	545843	106	0	0
T21	0	176	0	0
T46	11502	0	0	0
T116	10299	0	0	0
T120	13157	0	0	0
T141	0	185	0	0
T204	70572	0	0	0
T231	5482	0	0	0
T257	51126	0	0	0
T269	441375	0	0	0
T276	0	116	0	0
T306	53514	0	0	0
T307	10985	0	0	0
T318	0	50	0	0
T322	0	164	0	0
T323	0	65	0	0
T324	0	45	0	0
T325	0	137	0	0
T326	0	51	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	2699	0	0
T19	545843	122	0	0
T21	0	190	0	0
T46	11502	0	0	0
T116	10299	0	0	0
T120	13157	0	0	0
T141	0	106	0	0
T204	70572	0	0	0
T231	5482	0	0	0
T257	51126	0	0	0
T269	441375	0	0	0
T276	0	89	0	0
T306	53514	0	0	0
T307	10985	0	0	0
T318	0	61	0	0
T322	0	190	0	0
T323	0	71	0	0
T324	0	36	0	0
T325	0	132	0	0
T326	0	82	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	2189	0	0
T19	545843	115	0	0
T21	0	143	0	0
T46	11502	0	0	0
T116	10299	0	0	0
T120	13157	0	0	0
T141	0	123	0	0
T204	70572	0	0	0
T231	5482	0	0	0
T257	51126	0	0	0
T269	441375	0	0	0
T276	0	129	0	0
T306	53514	0	0	0
T307	10985	0	0	0
T318	0	58	0	0
T322	0	171	0	0
T323	0	62	0	0
T324	0	54	0	0
T325	0	142	0	0
T326	0	119	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	1266	0	0
T19	545843	43	0	0
T21	0	76	0	0
T46	11502	0	0	0
T116	10299	0	0	0
T120	13157	0	0	0
T141	0	80	0	0
T204	70572	0	0	0
T231	5482	0	0	0
T257	51126	0	0	0
T269	441375	0	0	0
T276	0	37	0	0
T306	53514	0	0	0
T307	10985	0	0	0
T318	0	24	0	0
T322	0	160	0	0
T323	0	32	0	0
T324	0	28	0	0
T325	0	61	0	0
T326	0	53	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	1618	0	0
T19	545843	68	0	0
T21	0	133	0	0
T46	11502	0	0	0
T116	10299	0	0	0
T120	13157	0	0	0
T141	0	78	0	0
T204	70572	0	0	0
T231	5482	0	0	0
T257	51126	0	0	0
T269	441375	0	0	0
T276	0	107	0	0
T306	53514	0	0	0
T307	10985	0	0	0
T318	0	21	0	0
T322	0	180	0	0
T323	0	31	0	0
T324	0	39	0	0
T325	0	62	0	0
T326	0	64	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	3074	0	0
T19	545843	118	0	0
T21	0	108	0	0
T46	11502	0	0	0
T116	10299	0	0	0
T120	13157	0	0	0
T141	0	73	0	0
T204	70572	0	0	0
T231	5482	0	0	0
T257	51126	0	0	0
T269	441375	0	0	0
T276	0	118	0	0
T306	53514	0	0	0
T307	10985	0	0	0
T318	0	91	0	0
T322	0	147	0	0
T323	0	68	0	0
T324	0	43	0	0
T325	0	99	0	0
T326	0	96	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	3970	0	0
T15	669827	0	0	0
T19	0	92	0	0
T72	0	29	0	0
T103	822170	16	0	0
T107	49548	0	0	0
T145	0	12	0	0
T158	28331	0	0	0
T163	20956	0	0	0
T164	11889	0	0	0
T169	14230	0	0	0
T177	0	17	0	0
T189	14576	0	0	0
T224	8531	0	0	0
T230	4790	0	0	0
T276	0	154	0	0
T318	0	59	0	0
T322	0	209	0	0
T323	0	57	0	0
T324	0	53	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	2465	0	0
T19	545843	145	0	0
T21	0	102	0	0
T46	11502	0	0	0
T116	10299	0	0	0
T120	13157	0	0	0
T141	0	126	0	0
T204	70572	0	0	0
T231	5482	0	0	0
T257	51126	0	0	0
T269	441375	0	0	0
T276	0	109	0	0
T306	53514	0	0	0
T307	10985	0	0	0
T318	0	97	0	0
T322	0	183	0	0
T323	0	57	0	0
T324	0	53	0	0
T325	0	107	0	0
T326	0	60	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	2789	0	0
T19	545843	90	0	0
T21	0	172	0	0
T46	11502	0	0	0
T116	10299	0	0	0
T120	13157	0	0	0
T141	0	120	0	0
T204	70572	0	0	0
T231	5482	0	0	0
T257	51126	0	0	0
T269	441375	0	0	0
T276	0	132	0	0
T306	53514	0	0	0
T307	10985	0	0	0
T318	0	101	0	0
T322	0	181	0	0
T323	0	53	0	0
T324	0	23	0	0
T325	0	131	0	0
T326	0	76	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	2474	0	0
T19	545843	90	0	0
T21	0	165	0	0
T46	11502	0	0	0
T116	10299	0	0	0
T120	13157	0	0	0
T141	0	132	0	0
T204	70572	0	0	0
T231	5482	0	0	0
T257	51126	0	0	0
T269	441375	0	0	0
T276	0	73	0	0
T306	53514	0	0	0
T307	10985	0	0	0
T318	0	88	0	0
T322	0	197	0	0
T323	0	36	0	0
T324	0	34	0	0
T325	0	119	0	0
T326	0	76	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481243923	2310	0	0
T19	545843	98	0	0
T21	0	151	0	0
T46	11502	0	0	0
T116	10299	0	0	0
T120	13157	0	0	0
T141	0	116	0	0
T204	70572	0	0	0
T231	5482	0	0	0
T257	51126	0	0	0
T269	441375	0	0	0
T276	0	97	0	0
T306	53514	0	0	0
T307	10985	0	0	0
T318	0	87	0	0
T322	0	186	0	0
T323	0	58	0	0
T324	0	32	0	0
T325	0	77	0	0
T326	0	82	0	0