Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.80	97.40	96.15	96.81		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.80	97.40	96.15	96.81		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.80	97.40	96.15	96.81		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T3,T4,T5
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T153
1	Covered	T153

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T3,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T3,T4,T5
ReadWaitSt	252	Covered	T3,T4,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T5
IdleSt->ReadSt	236	Covered	T3,T4,T5
InitSt->ErrorSt	315	Covered	T206,T207
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T103,T208,T173
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T39,T17
ReadSt->ReadWaitSt	252	Covered	T3,T4,T5
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T3,T4,T5
ResetSt->ErrorSt	315	Covered	T17,T79,T80
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T5,T39,T17
CheckFailError	317	Covered	T153
FsmStateError	289	Covered	T2,T3,T5
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T6,T7,T14
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T5,T39,T17
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T153
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T2,T3,T5
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T5,T39,T17
NoError->CheckFailError	317	Covered	T153
NoError->FsmStateError	289	Covered	T2,T3,T5
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T3,T4,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T13,T14
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T39,T17
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T3,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T5,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T5,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T153
1	0	Covered	T153
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T5,T12,T106
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	478379515	477502715	0	0
DigestKnown_A	478379515	477502715	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	478379515	3510	0	0
ErrorKnown_A	478379515	477502715	0	0
FsmStateKnown_A	478379515	477502715	0	0
InitDoneKnown_A	478379515	477502715	0	0
InitReadLocksPartition_A	478379515	85232629	0	0
InitWriteLocksPartition_A	478379515	85232629	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	478379515	477502715	0	0
OtpCmdKnown_A	478379515	477502715	0	0
OtpErrorState_A	478379515	0	0	0
OtpReqKnown_A	478379515	477502715	0	0
OtpSizeKnown_A	478379515	477502715	0	0
OtpWdataKnown_A	478379515	477502715	0	0
ReadLockPropagation_A	478379515	207506206	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	478379515	477502715	0	0
TlulRdataKnown_A	478379515	477502715	0	0
TlulReadOnReadLock_A	478379515	8524	0	0
TlulRerrorKnown_A	478379515	477502715	0	0
TlulRvalidKnown_A	478379515	477502715	0	0
WriteLockPropagation_A	478379515	2347077	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	478379515	25878625	0	0
u_state_regs_A	478379515	477502715	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	3510	0	0
T153	13366	3510	0	0
T179	125077	0	0	0
T180	13700	0	0	0
T181	22459	0	0	0
T182	18978	0	0	0
T183	14484	0	0	0
T184	70648	0	0	0
T185	24297	0	0	0
T186	27597	0	0	0
T187	13900	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	85232629	0	0
T1	20153	536	0	0
T2	29996	18551	0	0
T3	13219	3541	0	0
T4	15302	189	0	0
T5	509718	51572	0	0
T8	8057	2182	0	0
T9	27395	21853	0	0
T10	28552	12080	0	0
T11	59216	53891	0	0
T12	11269	3560	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	85232629	0	0
T1	20153	536	0	0
T2	29996	18551	0	0
T3	13219	3541	0	0
T4	15302	189	0	0
T5	509718	51572	0	0
T8	8057	2182	0	0
T9	27395	21853	0	0
T10	28552	12080	0	0
T11	59216	53891	0	0
T12	11269	3560	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	207506206	0	0
T1	20153	2542	0	0
T2	29996	0	0	0
T3	13219	0	0	0
T4	15302	2451	0	0
T5	509718	44083	0	0
T8	8057	0	0	0
T9	27395	0	0	0
T10	28552	0	0	0
T11	59216	0	0	0
T12	11269	0	0	0
T17	0	29667	0	0
T29	0	505	0	0
T38	0	15673	0	0
T39	0	8280	0	0
T42	0	2454	0	0
T68	0	14045	0	0
T106	0	543	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	8524	0	0
T2	29996	4	0	0
T3	13219	0	0	0
T4	15302	0	0	0
T5	509718	71	0	0
T8	8057	8	0	0
T9	27395	19	0	0
T10	28552	3	0	0
T11	59216	12	0	0
T12	11269	0	0	0
T16	3773	0	0	0
T39	0	9	0	0
T106	0	7	0	0
T139	0	4	0	0
T201	0	10	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	2347077	0	0
T5	509718	23150	0	0
T8	8057	0	0	0
T9	27395	0	0	0
T10	28552	0	0	0
T11	59216	0	0	0
T12	11269	0	0	0
T16	3773	0	0	0
T29	31038	0	0	0
T38	0	25327	0	0
T39	83882	2781	0	0
T68	0	5712	0	0
T72	0	26379	0	0
T102	0	6124	0	0
T103	0	94582	0	0
T104	0	19580	0	0
T106	91492	0	0	0
T107	0	4267	0	0
T109	0	249	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	25878625	0	0
T1	20153	14175	0	0
T2	29996	2490	0	0
T3	13219	0	0	0
T4	15302	0	0	0
T5	509718	282700	0	0
T8	8057	0	0	0
T9	27395	0	0	0
T10	28552	3926	0	0
T11	59216	0	0	0
T12	11269	0	0	0
T17	0	127076	0	0
T38	0	160885	0	0
T39	0	58591	0	0
T68	0	137636	0	0
T70	0	2216	0	0
T119	0	3746	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T70,T168,T164

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T106,T38,T43

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T79
1	Covered	T79

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T8
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T39

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T39

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T5
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T103,T208,T173
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T69,T119,T172
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T39,T42
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T139,T165,T197
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T17,T79,T80
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T39,T42
CheckFailError	317	Covered	T79
FsmStateError	289	Covered	T2,T3,T5
MacroEccCorrError	221	Covered	T106,T38,T70
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T6,T13
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T5,T39,T42
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T79
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T106,T70,T168
MacroEccCorrError->NoError	235	Covered	T38,T43,T63
NoError->AccessError	256	Covered	T5,T39,T42
NoError->CheckFailError	317	Covered	T79
NoError->FsmStateError	289	Covered	T2,T3,T5
NoError->MacroEccCorrError	221	Covered	T106,T38,T70

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T39
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T70,T168,T164
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T69,T119,T172
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T39,T15
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T39,T42
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T106,T38,T43
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T139,T165,T197
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T5,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T5,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T79
1	0	Covered	T79
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	478379515	477502715	0	0
DigestKnown_A	478379515	477502715	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	478379515	2169	0	0
ErrorKnown_A	478379515	477502715	0	0
FsmStateKnown_A	478379515	477502715	0	0
InitDoneKnown_A	478379515	477502715	0	0
InitReadLocksPartition_A	478379515	85419955	0	0
InitWriteLocksPartition_A	478379515	85419955	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	478379515	477502715	0	0
OtpCmdKnown_A	478379515	477502715	0	0
OtpErrorState_A	478379515	63	0	0
OtpReqKnown_A	478379515	477502715	0	0
OtpSizeKnown_A	478379515	477502715	0	0
OtpWdataKnown_A	478379515	477502715	0	0
ReadLockPropagation_A	478379515	199393905	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	478379515	477502715	0	0
TlulRdataKnown_A	478379515	477502715	0	0
TlulReadOnReadLock_A	478379515	8962	0	0
TlulRerrorKnown_A	478379515	477502715	0	0
TlulRvalidKnown_A	478379515	477502715	0	0
WriteLockPropagation_A	478379515	2355981	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	478379515	24771980	0	0
u_state_regs_A	478379515	477502715	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	2169	0	0
T79	11508	2169	0	0
T143	420791	0	0	0
T145	749373	0	0	0
T171	92015	0	0	0
T173	44319	0	0	0
T174	18331	0	0	0
T175	10508	0	0	0
T176	183154	0	0	0
T177	776308	0	0	0
T178	49322	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	85419955	0	0
T1	20153	621	0	0
T2	29996	18602	0	0
T3	13219	3575	0	0
T4	15302	257	0	0
T5	509718	53408	0	0
T8	8057	2233	0	0
T9	27395	21887	0	0
T10	28552	12148	0	0
T11	59216	53925	0	0
T12	11269	3611	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	85419955	0	0
T1	20153	621	0	0
T2	29996	18602	0	0
T3	13219	3575	0	0
T4	15302	257	0	0
T5	509718	53408	0	0
T8	8057	2233	0	0
T9	27395	21887	0	0
T10	28552	12148	0	0
T11	59216	53925	0	0
T12	11269	3611	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	63	0	0
T6	140153	0	0	0
T7	154777	0	0	0
T17	249278	0	0	0
T38	186996	0	0	0
T68	165403	0	0	0
T69	13298	1	0	0
T70	13349	0	0	0
T71	15198	0	0	0
T119	8970	1	0	0
T139	67565	1	0	0
T165	0	1	0	0
T172	0	1	0	0
T188	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	199393905	0	0
T1	20153	505	0	0
T2	29996	0	0	0
T3	13219	0	0	0
T4	15302	1401	0	0
T5	509718	39676	0	0
T8	8057	2110	0	0
T9	27395	0	0	0
T10	28552	16844	0	0
T11	59216	0	0	0
T12	11269	0	0	0
T17	0	31609	0	0
T29	0	503	0	0
T39	0	9111	0	0
T42	0	2911	0	0
T68	0	15459	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	8962	0	0
T2	29996	4	0	0
T3	13219	0	0	0
T4	15302	0	0	0
T5	509718	61	0	0
T8	8057	8	0	0
T9	27395	25	0	0
T10	28552	2	0	0
T11	59216	19	0	0
T12	11269	0	0	0
T16	3773	0	0	0
T39	0	14	0	0
T42	0	1	0	0
T106	0	5	0	0
T201	0	16	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	2355981	0	0
T5	509718	16150	0	0
T8	8057	0	0	0
T9	27395	0	0	0
T10	28552	0	0	0
T11	59216	0	0	0
T12	11269	0	0	0
T16	3773	0	0	0
T17	0	8196	0	0
T29	31038	0	0	0
T38	0	22906	0	0
T39	83882	10002	0	0
T68	0	12248	0	0
T72	0	133696	0	0
T102	0	20184	0	0
T103	0	66670	0	0
T106	91492	0	0	0
T107	0	6501	0	0
T109	0	249	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	24771980	0	0
T1	20153	5198	0	0
T2	29996	0	0	0
T3	13219	0	0	0
T4	15302	0	0	0
T5	509718	238188	0	0
T8	8057	0	0	0
T9	27395	0	0	0
T10	28552	0	0	0
T11	59216	0	0	0
T12	11269	0	0	0
T17	0	109060	0	0
T38	0	160664	0	0
T39	0	58353	0	0
T68	0	137364	0	0
T69	0	2478	0	0
T102	0	193419	0	0
T106	0	5155	0	0
T109	0	13287	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T115,T169,T26

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T42,T38,T165

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T153,T170,T166
1	Covered	T153,T170,T166

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T3,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T12

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T12

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T5
ReadWaitSt	252	Covered	T1,T3,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T5
IdleSt->ReadSt	236	Covered	T1,T3,T5
InitSt->ErrorSt	315	Covered	T103,T208,T173
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T12,T69,T119
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T5,T10
ReadSt->ReadWaitSt	252	Covered	T1,T3,T5
ReadWaitSt->ErrorSt	276	Covered	T106,T165,T197
ReadWaitSt->IdleSt	270	Covered	T1,T3,T5
ResetSt->ErrorSt	315	Covered	T17,T79,T80
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T5,T10
CheckFailError	317	Covered	T153,T170,T166
FsmStateError	289	Covered	T2,T3,T5
MacroEccCorrError	221	Covered	T42,T38,T115
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T10,T13
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T5,T10
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T153,T170,T166
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T115,T169,T26
MacroEccCorrError->NoError	235	Covered	T42,T38,T165
NoError->AccessError	256	Covered	T1,T5,T10
NoError->CheckFailError	317	Covered	T153,T170,T166
NoError->FsmStateError	289	Covered	T2,T3,T5
NoError->MacroEccCorrError	221	Covered	T42,T38,T115

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T115,T169,T26
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T12,T194,T195
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T13,T109
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T5,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T42,T38,T165
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T106,T165,T197
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T5,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T5,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T153,T170,T166
1	0	Covered	T153,T170,T166
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	478379515	477502715	0	0
DigestKnown_A	478379515	477502715	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	478379515	8889	0	0
ErrorKnown_A	478379515	477502715	0	0
FsmStateKnown_A	478379515	477502715	0	0
InitDoneKnown_A	478379515	477502715	0	0
InitReadLocksPartition_A	478379515	85606254	0	0
InitWriteLocksPartition_A	478379515	85606254	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	478379515	477502715	0	0
OtpCmdKnown_A	478379515	477502715	0	0
OtpErrorState_A	478379515	50	0	0
OtpReqKnown_A	478379515	477502715	0	0
OtpSizeKnown_A	478379515	477502715	0	0
OtpWdataKnown_A	478379515	477502715	0	0
ReadLockPropagation_A	478379515	214620852	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	478379515	477502715	0	0
TlulRdataKnown_A	478379515	477502715	0	0
TlulReadOnReadLock_A	478379515	9049	0	0
TlulRerrorKnown_A	478379515	477502715	0	0
TlulRvalidKnown_A	478379515	477502715	0	0
WriteLockPropagation_A	478379515	1251403	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	478379515	15690035	0	0
u_state_regs_A	478379515	477502715	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	8889	0	0
T153	13366	3510	0	0
T166	0	2594	0	0
T170	0	2785	0	0
T179	125077	0	0	0
T180	13700	0	0	0
T181	22459	0	0	0
T182	18978	0	0	0
T183	14484	0	0	0
T184	70648	0	0	0
T185	24297	0	0	0
T186	27597	0	0	0
T187	13900	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	85606254	0	0
T1	20153	706	0	0
T2	29996	18653	0	0
T3	13219	3609	0	0
T4	15302	325	0	0
T5	509718	55230	0	0
T8	8057	2284	0	0
T9	27395	21921	0	0
T10	28552	12216	0	0
T11	59216	53959	0	0
T12	11269	3652	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	85606254	0	0
T1	20153	706	0	0
T2	29996	18653	0	0
T3	13219	3609	0	0
T4	15302	325	0	0
T5	509718	55230	0	0
T8	8057	2284	0	0
T9	27395	21921	0	0
T10	28552	12216	0	0
T11	59216	53959	0	0
T12	11269	3652	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	50	0	0
T12	11269	1	0	0
T16	3773	0	0	0
T17	249278	0	0	0
T29	31038	0	0	0
T39	83882	0	0	0
T42	24030	0	0	0
T106	91492	1	0	0
T139	67565	0	0	0
T157	10471	0	0	0
T165	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	59755	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	214620852	0	0
T1	20153	503	0	0
T2	29996	0	0	0
T3	13219	0	0	0
T4	15302	4081	0	0
T5	509718	48297	0	0
T7	0	145623	0	0
T8	8057	0	0	0
T9	27395	0	0	0
T10	28552	16835	0	0
T11	59216	0	0	0
T12	11269	0	0	0
T17	0	31709	0	0
T38	0	14467	0	0
T39	0	9977	0	0
T42	0	2440	0	0
T68	0	13652	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	9049	0	0
T1	20153	2	0	0
T2	29996	3	0	0
T3	13219	0	0	0
T4	15302	0	0	0
T5	509718	78	0	0
T8	8057	3	0	0
T9	27395	26	0	0
T10	28552	5	0	0
T11	59216	17	0	0
T12	11269	0	0	0
T39	0	6	0	0
T106	0	3	0	0
T201	0	9	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	1251403	0	0
T5	509718	13469	0	0
T8	8057	0	0	0
T9	27395	0	0	0
T10	28552	0	0	0
T11	59216	0	0	0
T12	11269	0	0	0
T16	3773	0	0	0
T17	0	4290	0	0
T29	31038	0	0	0
T39	83882	4169	0	0
T68	0	24907	0	0
T72	0	85816	0	0
T78	0	3154	0	0
T102	0	6672	0	0
T103	0	11937	0	0
T106	91492	0	0	0
T107	0	4267	0	0
T109	0	4211	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	15690035	0	0
T2	29996	2456	0	0
T3	13219	0	0	0
T4	15302	0	0	0
T5	509718	272104	0	0
T8	8057	0	0	0
T9	27395	0	0	0
T10	28552	0	0	0
T11	59216	0	0	0
T12	11269	2792	0	0
T16	3773	0	0	0
T17	0	32418	0	0
T29	0	24047	0	0
T39	0	58115	0	0
T68	0	137092	0	0
T102	0	192892	0	0
T106	0	5138	0	0
T109	0	37988	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478379515	477502715	0	0
T1	20153	19811	0	0
T2	29996	29740	0	0
T3	13219	12962	0	0
T4	15302	15048	0	0
T5	509718	500911	0	0
T8	8057	7820	0	0
T9	27395	27207	0	0
T10	28552	28297	0	0
T11	59216	59028	0	0
T12	11269	11014	0	0