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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.87 93.83 96.38 95.62 91.65 97.00 96.33 93.28


Total test records in report: 1325
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T1264 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.849825750 Apr 18 02:27:12 PM PDT 24 Apr 18 02:27:14 PM PDT 24 134499113 ps
T1265 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.781378992 Apr 18 02:27:17 PM PDT 24 Apr 18 02:27:20 PM PDT 24 43440662 ps
T308 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3468364635 Apr 18 02:26:55 PM PDT 24 Apr 18 02:27:01 PM PDT 24 159656176 ps
T1266 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1512061764 Apr 18 02:27:02 PM PDT 24 Apr 18 02:27:05 PM PDT 24 104233825 ps
T1267 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.115829194 Apr 18 02:26:49 PM PDT 24 Apr 18 02:26:53 PM PDT 24 161959922 ps
T1268 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1619057469 Apr 18 02:26:55 PM PDT 24 Apr 18 02:27:00 PM PDT 24 864930710 ps
T1269 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.746018392 Apr 18 02:27:01 PM PDT 24 Apr 18 02:27:05 PM PDT 24 104553012 ps
T1270 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.868502420 Apr 18 02:27:09 PM PDT 24 Apr 18 02:27:11 PM PDT 24 40786303 ps
T1271 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3165360645 Apr 18 02:27:16 PM PDT 24 Apr 18 02:27:18 PM PDT 24 150408764 ps
T1272 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3138484281 Apr 18 02:27:16 PM PDT 24 Apr 18 02:27:21 PM PDT 24 145912209 ps
T1273 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.2742038755 Apr 18 02:27:19 PM PDT 24 Apr 18 02:27:21 PM PDT 24 41275933 ps
T1274 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3864003573 Apr 18 02:27:12 PM PDT 24 Apr 18 02:27:17 PM PDT 24 408761632 ps
T1275 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.633984039 Apr 18 02:26:50 PM PDT 24 Apr 18 02:26:54 PM PDT 24 535285013 ps
T1276 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.145529578 Apr 18 02:27:17 PM PDT 24 Apr 18 02:27:20 PM PDT 24 553362533 ps
T1277 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.702132251 Apr 18 02:27:10 PM PDT 24 Apr 18 02:27:13 PM PDT 24 139268394 ps
T1278 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.1392212984 Apr 18 02:26:54 PM PDT 24 Apr 18 02:26:56 PM PDT 24 78222862 ps
T300 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2806482033 Apr 18 02:26:55 PM PDT 24 Apr 18 02:26:58 PM PDT 24 65601607 ps
T1279 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.513144215 Apr 18 02:26:55 PM PDT 24 Apr 18 02:26:58 PM PDT 24 532529488 ps
T1280 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.2183620897 Apr 18 02:27:12 PM PDT 24 Apr 18 02:27:15 PM PDT 24 91789616 ps
T1281 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.3857202995 Apr 18 02:26:53 PM PDT 24 Apr 18 02:26:56 PM PDT 24 57122228 ps
T1282 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1358580611 Apr 18 02:26:50 PM PDT 24 Apr 18 02:26:53 PM PDT 24 37449071 ps
T1283 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.173858550 Apr 18 02:27:10 PM PDT 24 Apr 18 02:27:16 PM PDT 24 1575009811 ps
T1284 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.4012792464 Apr 18 02:26:49 PM PDT 24 Apr 18 02:26:53 PM PDT 24 92795870 ps
T1285 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.738109197 Apr 18 02:27:04 PM PDT 24 Apr 18 02:27:08 PM PDT 24 360769042 ps
T1286 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.363456336 Apr 18 02:26:56 PM PDT 24 Apr 18 02:27:01 PM PDT 24 246277544 ps
T1287 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.2373227689 Apr 18 02:27:00 PM PDT 24 Apr 18 02:27:03 PM PDT 24 85395300 ps
T1288 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3178514769 Apr 18 02:26:54 PM PDT 24 Apr 18 02:26:57 PM PDT 24 108568167 ps
T1289 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1820545949 Apr 18 02:26:56 PM PDT 24 Apr 18 02:26:59 PM PDT 24 220422920 ps
T1290 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1785350585 Apr 18 02:27:04 PM PDT 24 Apr 18 02:27:09 PM PDT 24 125372365 ps
T1291 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.766227596 Apr 18 02:27:03 PM PDT 24 Apr 18 02:27:05 PM PDT 24 534267531 ps
T1292 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.71137251 Apr 18 02:26:53 PM PDT 24 Apr 18 02:26:58 PM PDT 24 98559277 ps
T347 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.3049071108 Apr 18 02:26:55 PM PDT 24 Apr 18 02:27:18 PM PDT 24 4770305069 ps
T1293 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2526142609 Apr 18 02:27:09 PM PDT 24 Apr 18 02:27:15 PM PDT 24 1765408397 ps
T1294 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3416928332 Apr 18 02:27:07 PM PDT 24 Apr 18 02:27:09 PM PDT 24 587530674 ps
T1295 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2445773141 Apr 18 02:26:50 PM PDT 24 Apr 18 02:26:52 PM PDT 24 45354392 ps
T1296 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3673585316 Apr 18 02:27:22 PM PDT 24 Apr 18 02:27:25 PM PDT 24 41835543 ps
T1297 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.250535310 Apr 18 02:27:07 PM PDT 24 Apr 18 02:27:09 PM PDT 24 43707191 ps
T301 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3400342324 Apr 18 02:27:00 PM PDT 24 Apr 18 02:27:03 PM PDT 24 158809016 ps
T1298 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.1709389139 Apr 18 02:27:17 PM PDT 24 Apr 18 02:27:20 PM PDT 24 47387347 ps
T1299 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3381451472 Apr 18 02:27:04 PM PDT 24 Apr 18 02:27:06 PM PDT 24 168752694 ps
T1300 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.1659310416 Apr 18 02:27:14 PM PDT 24 Apr 18 02:27:16 PM PDT 24 39768436 ps
T1301 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2754908631 Apr 18 02:27:19 PM PDT 24 Apr 18 02:27:21 PM PDT 24 40265559 ps
T1302 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.918627480 Apr 18 02:26:55 PM PDT 24 Apr 18 02:27:03 PM PDT 24 651762773 ps
T1303 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2844006451 Apr 18 02:27:18 PM PDT 24 Apr 18 02:27:20 PM PDT 24 55896266 ps
T1304 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.228964535 Apr 18 02:26:52 PM PDT 24 Apr 18 02:26:55 PM PDT 24 38588980 ps
T1305 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.4092295863 Apr 18 02:26:55 PM PDT 24 Apr 18 02:26:57 PM PDT 24 70274472 ps
T1306 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1355163002 Apr 18 02:27:14 PM PDT 24 Apr 18 02:27:16 PM PDT 24 38629285 ps
T302 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.123001728 Apr 18 02:27:19 PM PDT 24 Apr 18 02:27:21 PM PDT 24 158281601 ps
T1307 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.2335330975 Apr 18 02:26:55 PM PDT 24 Apr 18 02:26:57 PM PDT 24 531421296 ps
T303 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.280312135 Apr 18 02:27:05 PM PDT 24 Apr 18 02:27:07 PM PDT 24 47465307 ps
T1308 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3589759660 Apr 18 02:26:53 PM PDT 24 Apr 18 02:26:57 PM PDT 24 132458386 ps
T304 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1380091520 Apr 18 02:27:00 PM PDT 24 Apr 18 02:27:07 PM PDT 24 173997180 ps
T290 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2187861033 Apr 18 02:27:12 PM PDT 24 Apr 18 02:27:14 PM PDT 24 50157225 ps
T1309 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.819840233 Apr 18 02:27:03 PM PDT 24 Apr 18 02:27:06 PM PDT 24 74209219 ps
T1310 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1416653335 Apr 18 02:27:01 PM PDT 24 Apr 18 02:27:03 PM PDT 24 77268926 ps
T343 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.395695691 Apr 18 02:27:10 PM PDT 24 Apr 18 02:27:33 PM PDT 24 2515706137 ps
T1311 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3436401923 Apr 18 02:27:19 PM PDT 24 Apr 18 02:27:21 PM PDT 24 53826728 ps
T1312 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3496677827 Apr 18 02:26:53 PM PDT 24 Apr 18 02:26:57 PM PDT 24 235954113 ps
T1313 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.2380346364 Apr 18 02:26:55 PM PDT 24 Apr 18 02:26:59 PM PDT 24 104686976 ps
T1314 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1507725767 Apr 18 02:26:50 PM PDT 24 Apr 18 02:26:54 PM PDT 24 362086243 ps
T305 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2524600550 Apr 18 02:26:53 PM PDT 24 Apr 18 02:27:01 PM PDT 24 128730945 ps
T1315 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.552889742 Apr 18 02:27:08 PM PDT 24 Apr 18 02:27:12 PM PDT 24 111393409 ps
T1316 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.394512953 Apr 18 02:27:07 PM PDT 24 Apr 18 02:27:09 PM PDT 24 151176991 ps
T1317 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3932791821 Apr 18 02:27:07 PM PDT 24 Apr 18 02:27:12 PM PDT 24 211214358 ps
T349 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.4098567701 Apr 18 02:27:01 PM PDT 24 Apr 18 02:27:18 PM PDT 24 3531167318 ps
T1318 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.4067382798 Apr 18 02:27:12 PM PDT 24 Apr 18 02:27:15 PM PDT 24 131767417 ps
T1319 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1260737132 Apr 18 02:27:17 PM PDT 24 Apr 18 02:27:20 PM PDT 24 571818117 ps
T1320 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1430909450 Apr 18 02:26:48 PM PDT 24 Apr 18 02:26:55 PM PDT 24 388022281 ps
T1321 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.2328890277 Apr 18 02:26:51 PM PDT 24 Apr 18 02:26:54 PM PDT 24 126888938 ps
T344 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.735823856 Apr 18 02:26:49 PM PDT 24 Apr 18 02:27:09 PM PDT 24 2418676996 ps
T1322 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.2777847895 Apr 18 02:27:16 PM PDT 24 Apr 18 02:27:18 PM PDT 24 73013923 ps
T267 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2922706758 Apr 18 02:27:08 PM PDT 24 Apr 18 02:27:36 PM PDT 24 18929135227 ps
T1323 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2617049884 Apr 18 02:26:57 PM PDT 24 Apr 18 02:27:00 PM PDT 24 72953166 ps
T1324 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.523555535 Apr 18 02:27:19 PM PDT 24 Apr 18 02:27:21 PM PDT 24 42889966 ps
T1325 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.3505721120 Apr 18 02:27:14 PM PDT 24 Apr 18 02:27:16 PM PDT 24 553297170 ps

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.3675104727
Short name T5
Test name
Test status
Simulation time 35072444001 ps
CPU time 187.33 seconds
Started Apr 18 03:43:04 PM PDT 24
Finished Apr 18 03:46:11 PM PDT 24
Peak memory 257024 kb
Host smart-152704e3-cac9-4eab-8636-260cd6e7c77c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675104727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.3675104727
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.3108472205
Short name T13
Test name
Test status
Simulation time 178680139458 ps
CPU time 3372.79 seconds
Started Apr 18 03:44:31 PM PDT 24
Finished Apr 18 04:40:45 PM PDT 24
Peak memory 375412 kb
Host smart-d2e7a52d-d364-486c-b10f-dbce372ec54d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108472205 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.3108472205
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.303423454
Short name T72
Test name
Test status
Simulation time 17721261906 ps
CPU time 210.42 seconds
Started Apr 18 03:42:06 PM PDT 24
Finished Apr 18 03:45:37 PM PDT 24
Peak memory 247708 kb
Host smart-8f5915a9-557f-4370-a04e-3054a71ba970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303423454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.
303423454
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.3058924879
Short name T106
Test name
Test status
Simulation time 1867198761 ps
CPU time 26.47 seconds
Started Apr 18 03:42:30 PM PDT 24
Finished Apr 18 03:42:57 PM PDT 24
Peak memory 242664 kb
Host smart-408b5a91-de1f-4250-b74d-bbe4c1341e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058924879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.3058924879
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.540313571
Short name T17
Test name
Test status
Simulation time 5491113185 ps
CPU time 107.83 seconds
Started Apr 18 03:41:37 PM PDT 24
Finished Apr 18 03:43:26 PM PDT 24
Peak memory 249484 kb
Host smart-5ec5df03-4b72-4c11-a923-7cff0250fb56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540313571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.
540313571
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.1257566311
Short name T236
Test name
Test status
Simulation time 41441118789 ps
CPU time 214.93 seconds
Started Apr 18 03:37:11 PM PDT 24
Finished Apr 18 03:40:46 PM PDT 24
Peak memory 269384 kb
Host smart-2a728b1f-647d-42fa-9392-a41660ba64ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257566311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1257566311
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.2050920056
Short name T103
Test name
Test status
Simulation time 34342015702 ps
CPU time 227.59 seconds
Started Apr 18 03:41:22 PM PDT 24
Finished Apr 18 03:45:10 PM PDT 24
Peak memory 281204 kb
Host smart-13b1c037-8b5f-4f0f-ae65-a13b01b7c9e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050920056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.2050920056
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.1689467395
Short name T43
Test name
Test status
Simulation time 2428864076 ps
CPU time 19 seconds
Started Apr 18 03:41:10 PM PDT 24
Finished Apr 18 03:41:30 PM PDT 24
Peak memory 244456 kb
Host smart-ea52eb88-a7a7-4528-951a-2e8f064b5589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689467395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.1689467395
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.582733128
Short name T19
Test name
Test status
Simulation time 909741623570 ps
CPU time 1647.34 seconds
Started Apr 18 03:44:42 PM PDT 24
Finished Apr 18 04:12:10 PM PDT 24
Peak memory 312756 kb
Host smart-86713e21-2667-4c9f-85c7-f9bff59a2433
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582733128 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.582733128
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.4094031749
Short name T143
Test name
Test status
Simulation time 11912087929 ps
CPU time 149.48 seconds
Started Apr 18 03:42:14 PM PDT 24
Finished Apr 18 03:44:44 PM PDT 24
Peak memory 251048 kb
Host smart-cd5931be-4c31-4277-8bb4-5027d684e08c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094031749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.4094031749
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.563251505
Short name T266
Test name
Test status
Simulation time 3509315087 ps
CPU time 19.76 seconds
Started Apr 18 02:27:10 PM PDT 24
Finished Apr 18 02:27:30 PM PDT 24
Peak memory 246860 kb
Host smart-8c6071e8-bbe8-490c-80cd-f489bdeba345
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563251505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_in
tg_err.563251505
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.3114200282
Short name T166
Test name
Test status
Simulation time 1480091529 ps
CPU time 5.29 seconds
Started Apr 18 03:45:01 PM PDT 24
Finished Apr 18 03:45:07 PM PDT 24
Peak memory 241684 kb
Host smart-157f217c-dc83-469f-85da-b5ae28a76015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114200282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.3114200282
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.1698707617
Short name T47
Test name
Test status
Simulation time 108492744 ps
CPU time 3.66 seconds
Started Apr 18 03:36:47 PM PDT 24
Finished Apr 18 03:36:51 PM PDT 24
Peak memory 242276 kb
Host smart-80d2f06f-fd71-4a04-9455-709bb656d0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698707617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.1698707617
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.3327892327
Short name T38
Test name
Test status
Simulation time 1869985850 ps
CPU time 34.06 seconds
Started Apr 18 03:42:58 PM PDT 24
Finished Apr 18 03:43:32 PM PDT 24
Peak memory 242620 kb
Host smart-691cbb88-c39b-4455-96d6-ecd82ea31006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327892327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.3327892327
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.3062070467
Short name T139
Test name
Test status
Simulation time 1647919157 ps
CPU time 19.65 seconds
Started Apr 18 03:42:35 PM PDT 24
Finished Apr 18 03:42:55 PM PDT 24
Peak memory 242532 kb
Host smart-0653541e-9b1c-412a-9b2b-0b8c2b8021fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062070467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.3062070467
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.4269019540
Short name T62
Test name
Test status
Simulation time 201703603 ps
CPU time 4.6 seconds
Started Apr 18 03:44:47 PM PDT 24
Finished Apr 18 03:44:52 PM PDT 24
Peak memory 242248 kb
Host smart-b64f4223-6610-43d7-9595-90c9eb2f85d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269019540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.4269019540
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.2866728765
Short name T380
Test name
Test status
Simulation time 21024428609 ps
CPU time 135.54 seconds
Started Apr 18 03:39:37 PM PDT 24
Finished Apr 18 03:41:53 PM PDT 24
Peak memory 248728 kb
Host smart-09ad6cc0-f92f-4f00-8cef-2947c0d0b3c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866728765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.2866728765
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.1280420923
Short name T26
Test name
Test status
Simulation time 188669878 ps
CPU time 3.59 seconds
Started Apr 18 03:46:27 PM PDT 24
Finished Apr 18 03:46:31 PM PDT 24
Peak memory 242076 kb
Host smart-7498b09c-61f1-4c43-8bcd-0467cbaf8fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280420923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.1280420923
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.868169060
Short name T22
Test name
Test status
Simulation time 280774364154 ps
CPU time 2296.52 seconds
Started Apr 18 03:44:29 PM PDT 24
Finished Apr 18 04:22:47 PM PDT 24
Peak memory 445592 kb
Host smart-490a9602-9729-45c8-b379-b06d5bc8e986
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868169060 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.868169060
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.669385565
Short name T73
Test name
Test status
Simulation time 2247892434 ps
CPU time 4.69 seconds
Started Apr 18 03:46:40 PM PDT 24
Finished Apr 18 03:46:46 PM PDT 24
Peak memory 241920 kb
Host smart-27409bc3-d1ff-4a20-a37c-a56f5ef1afeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669385565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.669385565
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.1939649371
Short name T15
Test name
Test status
Simulation time 1116382119773 ps
CPU time 2814.67 seconds
Started Apr 18 03:44:10 PM PDT 24
Finished Apr 18 04:31:06 PM PDT 24
Peak memory 587472 kb
Host smart-013bbd20-6638-4af6-a4f7-75bd53fc7f9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939649371 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.1939649371
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.3517321824
Short name T16
Test name
Test status
Simulation time 83861449 ps
CPU time 1.59 seconds
Started Apr 18 03:42:48 PM PDT 24
Finished Apr 18 03:42:50 PM PDT 24
Peak memory 240044 kb
Host smart-e4e50a53-e1fb-4553-a05f-bcc1dae091e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517321824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.3517321824
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.733079206
Short name T252
Test name
Test status
Simulation time 17821073613 ps
CPU time 222.86 seconds
Started Apr 18 03:39:21 PM PDT 24
Finished Apr 18 03:43:05 PM PDT 24
Peak memory 257056 kb
Host smart-61d906be-f8e8-4a4f-96cc-907ccfc4f06b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733079206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.
733079206
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.710646729
Short name T3
Test name
Test status
Simulation time 2203481286 ps
CPU time 4.16 seconds
Started Apr 18 03:45:28 PM PDT 24
Finished Apr 18 03:45:32 PM PDT 24
Peak memory 242004 kb
Host smart-3190f461-cce4-440d-b446-4a89e27ac62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710646729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.710646729
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.3269329002
Short name T65
Test name
Test status
Simulation time 3046409389 ps
CPU time 6.04 seconds
Started Apr 18 03:46:40 PM PDT 24
Finished Apr 18 03:46:46 PM PDT 24
Peak memory 241972 kb
Host smart-d24fcc63-a56e-427c-9382-492aa5cafa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269329002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.3269329002
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.3629375620
Short name T79
Test name
Test status
Simulation time 205523013 ps
CPU time 4.39 seconds
Started Apr 18 03:36:18 PM PDT 24
Finished Apr 18 03:36:23 PM PDT 24
Peak memory 241708 kb
Host smart-853a6220-e7db-44bf-ae15-ede819648f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629375620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.3629375620
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.856865872
Short name T153
Test name
Test status
Simulation time 139267612 ps
CPU time 3.27 seconds
Started Apr 18 03:45:55 PM PDT 24
Finished Apr 18 03:45:59 PM PDT 24
Peak memory 241808 kb
Host smart-134b22d9-41f3-4d8c-bfce-669fac9c0497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856865872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.856865872
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.2971073844
Short name T83
Test name
Test status
Simulation time 1517130826 ps
CPU time 15.32 seconds
Started Apr 18 03:43:22 PM PDT 24
Finished Apr 18 03:43:38 PM PDT 24
Peak memory 242096 kb
Host smart-cddbc351-8cfc-418c-bfcd-62fd2881f85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971073844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.2971073844
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.617064032
Short name T32
Test name
Test status
Simulation time 246916889 ps
CPU time 3.85 seconds
Started Apr 18 03:46:20 PM PDT 24
Finished Apr 18 03:46:24 PM PDT 24
Peak memory 241888 kb
Host smart-e119606a-ad4b-4ba9-bdf5-72f5a71cd257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617064032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.617064032
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.1892242073
Short name T171
Test name
Test status
Simulation time 3834063074 ps
CPU time 34.95 seconds
Started Apr 18 03:42:38 PM PDT 24
Finished Apr 18 03:43:14 PM PDT 24
Peak memory 245252 kb
Host smart-e20b0533-e2fe-4539-bd65-f17f55b1a5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892242073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.1892242073
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.543606239
Short name T219
Test name
Test status
Simulation time 2058900284 ps
CPU time 5.62 seconds
Started Apr 18 03:46:54 PM PDT 24
Finished Apr 18 03:47:01 PM PDT 24
Peak memory 241836 kb
Host smart-ea228ebd-69d3-4317-b30b-fe61817ac1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543606239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.543606239
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.224461534
Short name T48
Test name
Test status
Simulation time 284664707 ps
CPU time 3.53 seconds
Started Apr 18 03:45:17 PM PDT 24
Finished Apr 18 03:45:22 PM PDT 24
Peak memory 241804 kb
Host smart-42d987cc-314d-4330-8fba-18caf1b932b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224461534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.224461534
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.1483654416
Short name T35
Test name
Test status
Simulation time 161290647 ps
CPU time 4.84 seconds
Started Apr 18 03:45:10 PM PDT 24
Finished Apr 18 03:45:16 PM PDT 24
Peak memory 241960 kb
Host smart-25c75e9d-7bed-441a-be17-ace84ec0675a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483654416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.1483654416
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.3474358737
Short name T119
Test name
Test status
Simulation time 1495411901 ps
CPU time 3.43 seconds
Started Apr 18 03:45:44 PM PDT 24
Finished Apr 18 03:45:48 PM PDT 24
Peak memory 241708 kb
Host smart-cfd59fea-27cb-42c6-995e-3a35f25e8052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474358737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.3474358737
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.652239928
Short name T158
Test name
Test status
Simulation time 4722256510 ps
CPU time 11.3 seconds
Started Apr 18 03:42:42 PM PDT 24
Finished Apr 18 03:42:54 PM PDT 24
Peak memory 241920 kb
Host smart-104580bc-0363-4a32-8b31-85bee9712098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652239928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.652239928
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.3141102436
Short name T749
Test name
Test status
Simulation time 30539149083 ps
CPU time 237.97 seconds
Started Apr 18 03:40:00 PM PDT 24
Finished Apr 18 03:43:59 PM PDT 24
Peak memory 247504 kb
Host smart-4e210614-beaf-49ed-af27-8a1b39db0e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141102436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.3141102436
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.3452077861
Short name T140
Test name
Test status
Simulation time 49099170798 ps
CPU time 1294.33 seconds
Started Apr 18 03:44:10 PM PDT 24
Finished Apr 18 04:05:45 PM PDT 24
Peak memory 413448 kb
Host smart-afb3c302-f133-4b99-9118-20a1c092772a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452077861 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.3452077861
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.4123531465
Short name T434
Test name
Test status
Simulation time 1770265207 ps
CPU time 5.22 seconds
Started Apr 18 03:46:16 PM PDT 24
Finished Apr 18 03:46:22 PM PDT 24
Peak memory 241816 kb
Host smart-e2841670-bcf0-4910-9b8e-5e24542bcb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123531465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.4123531465
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.4272826380
Short name T54
Test name
Test status
Simulation time 427733618 ps
CPU time 4.32 seconds
Started Apr 18 03:46:52 PM PDT 24
Finished Apr 18 03:46:57 PM PDT 24
Peak memory 242196 kb
Host smart-c6a10dde-5d5d-446d-aeda-99697424fa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272826380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.4272826380
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.49883173
Short name T356
Test name
Test status
Simulation time 5008996429 ps
CPU time 9.28 seconds
Started Apr 18 03:38:35 PM PDT 24
Finished Apr 18 03:38:45 PM PDT 24
Peak memory 242636 kb
Host smart-4db7771b-3293-443a-ba30-34d08e3b7106
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49883173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.49883173
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.276020731
Short name T179
Test name
Test status
Simulation time 13029384414 ps
CPU time 282.13 seconds
Started Apr 18 03:43:42 PM PDT 24
Finished Apr 18 03:48:25 PM PDT 24
Peak memory 274020 kb
Host smart-2a84b2ea-aa3f-4b84-a6be-981a84fddf1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276020731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.
276020731
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.969099250
Short name T177
Test name
Test status
Simulation time 124121919453 ps
CPU time 189.06 seconds
Started Apr 18 03:39:34 PM PDT 24
Finished Apr 18 03:42:44 PM PDT 24
Peak memory 277500 kb
Host smart-39e1c700-37d3-475a-863d-89a5d7ad0660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969099250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.
969099250
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.1518621172
Short name T30
Test name
Test status
Simulation time 449875980 ps
CPU time 13.88 seconds
Started Apr 18 03:42:08 PM PDT 24
Finished Apr 18 03:42:23 PM PDT 24
Peak memory 241816 kb
Host smart-27fef01d-1a97-46e4-84c5-f24ca0596f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518621172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.1518621172
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.270794064
Short name T339
Test name
Test status
Simulation time 2378056765 ps
CPU time 18.03 seconds
Started Apr 18 02:27:10 PM PDT 24
Finished Apr 18 02:27:28 PM PDT 24
Peak memory 245356 kb
Host smart-bf0c422f-a28d-4a40-ae3c-a5623188e5ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270794064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_in
tg_err.270794064
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.2007651272
Short name T77
Test name
Test status
Simulation time 621050045 ps
CPU time 19.57 seconds
Started Apr 18 03:38:45 PM PDT 24
Finished Apr 18 03:39:05 PM PDT 24
Peak memory 242420 kb
Host smart-c0574c5a-fe0e-4ad9-aef9-a537aaa44730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007651272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.2007651272
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.1755857315
Short name T1064
Test name
Test status
Simulation time 434699283 ps
CPU time 9.87 seconds
Started Apr 18 03:45:05 PM PDT 24
Finished Apr 18 03:45:16 PM PDT 24
Peak memory 242032 kb
Host smart-3e4368dc-555e-4996-9bce-813b245f542e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755857315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1755857315
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.2722074903
Short name T156
Test name
Test status
Simulation time 4733655116 ps
CPU time 26.35 seconds
Started Apr 18 03:45:11 PM PDT 24
Finished Apr 18 03:45:38 PM PDT 24
Peak memory 241760 kb
Host smart-96f1f6ce-96c8-4d86-a1b0-2ddd54c8fbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722074903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.2722074903
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.1467339272
Short name T76
Test name
Test status
Simulation time 487680612 ps
CPU time 5.65 seconds
Started Apr 18 03:38:51 PM PDT 24
Finished Apr 18 03:38:57 PM PDT 24
Peak memory 241988 kb
Host smart-7cf3035a-bb51-458f-a430-0c305a572a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467339272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.1467339272
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.2800560245
Short name T133
Test name
Test status
Simulation time 309215372 ps
CPU time 8.27 seconds
Started Apr 18 03:45:27 PM PDT 24
Finished Apr 18 03:45:36 PM PDT 24
Peak memory 241784 kb
Host smart-d9457c35-15bc-4291-bd9d-974b73989c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800560245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.2800560245
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.3081321361
Short name T144
Test name
Test status
Simulation time 201446701 ps
CPU time 5.54 seconds
Started Apr 18 03:39:39 PM PDT 24
Finished Apr 18 03:39:45 PM PDT 24
Peak memory 241684 kb
Host smart-e7e8e4c6-a7b6-4d55-a5ee-99db33796f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081321361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.3081321361
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.3192555992
Short name T877
Test name
Test status
Simulation time 644506801 ps
CPU time 14.91 seconds
Started Apr 18 03:46:14 PM PDT 24
Finished Apr 18 03:46:29 PM PDT 24
Peak memory 242048 kb
Host smart-19954444-5cdc-47e1-9854-f8ca0a821ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192555992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.3192555992
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.1057881295
Short name T207
Test name
Test status
Simulation time 5113800391 ps
CPU time 12.2 seconds
Started Apr 18 03:40:05 PM PDT 24
Finished Apr 18 03:40:18 PM PDT 24
Peak memory 242116 kb
Host smart-83a7bdfb-7a87-423f-9fe5-caa2244278a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057881295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.1057881295
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.2822086600
Short name T152
Test name
Test status
Simulation time 340039916 ps
CPU time 14.55 seconds
Started Apr 18 03:46:28 PM PDT 24
Finished Apr 18 03:46:43 PM PDT 24
Peak memory 241848 kb
Host smart-f4ae0f0f-037a-4540-bed3-1b18f3807665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822086600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2822086600
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.1176252951
Short name T123
Test name
Test status
Simulation time 200952400 ps
CPU time 4.21 seconds
Started Apr 18 03:46:24 PM PDT 24
Finished Apr 18 03:46:29 PM PDT 24
Peak memory 241944 kb
Host smart-d2329567-5e1b-4824-86ef-0060654545c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176252951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.1176252951
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.97705708
Short name T90
Test name
Test status
Simulation time 153192846 ps
CPU time 4.34 seconds
Started Apr 18 03:44:31 PM PDT 24
Finished Apr 18 03:44:36 PM PDT 24
Peak memory 241940 kb
Host smart-e310ce05-7b1a-4c68-b572-e0c65bedc979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97705708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.97705708
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.3976046019
Short name T370
Test name
Test status
Simulation time 1729418688 ps
CPU time 34.91 seconds
Started Apr 18 03:42:58 PM PDT 24
Finished Apr 18 03:43:33 PM PDT 24
Peak memory 241772 kb
Host smart-692034f5-05d6-44e8-bd57-6cd61a4ad694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976046019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.3976046019
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.691422911
Short name T340
Test name
Test status
Simulation time 1237579147 ps
CPU time 9.85 seconds
Started Apr 18 02:27:11 PM PDT 24
Finished Apr 18 02:27:21 PM PDT 24
Peak memory 244800 kb
Host smart-99d9e3d4-0ad6-43ed-9981-019210c69ec4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691422911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_in
tg_err.691422911
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.741831036
Short name T383
Test name
Test status
Simulation time 4698193350 ps
CPU time 16.5 seconds
Started Apr 18 03:39:29 PM PDT 24
Finished Apr 18 03:39:46 PM PDT 24
Peak memory 242364 kb
Host smart-0be1cc62-e29e-4330-bb1e-a476aedcab51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=741831036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.741831036
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.78271485
Short name T724
Test name
Test status
Simulation time 348969494 ps
CPU time 9.1 seconds
Started Apr 18 03:39:40 PM PDT 24
Finished Apr 18 03:39:49 PM PDT 24
Peak memory 241880 kb
Host smart-50322cc4-257c-4880-ae1a-ea0cb19ea3ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78271485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.78271485
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.4138211167
Short name T84
Test name
Test status
Simulation time 2232648015 ps
CPU time 22.72 seconds
Started Apr 18 03:36:54 PM PDT 24
Finished Apr 18 03:37:17 PM PDT 24
Peak memory 242448 kb
Host smart-3db93a57-53b6-476d-9238-12b52ffa67c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138211167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.4138211167
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.3049071108
Short name T347
Test name
Test status
Simulation time 4770305069 ps
CPU time 22.01 seconds
Started Apr 18 02:26:55 PM PDT 24
Finished Apr 18 02:27:18 PM PDT 24
Peak memory 246784 kb
Host smart-2cc48cb6-744c-4759-a370-4b43213758f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049071108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.3049071108
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1017755959
Short name T288
Test name
Test status
Simulation time 318853043 ps
CPU time 6.16 seconds
Started Apr 18 02:26:52 PM PDT 24
Finished Apr 18 02:26:59 PM PDT 24
Peak memory 239396 kb
Host smart-ab5b14ec-d3a5-4d37-afeb-3a65eaf017b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017755959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.1017755959
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3710953831
Short name T312
Test name
Test status
Simulation time 91761215 ps
CPU time 1.97 seconds
Started Apr 18 02:27:04 PM PDT 24
Finished Apr 18 02:27:06 PM PDT 24
Peak memory 239336 kb
Host smart-3bffb58b-c9d0-4df2-bea2-767e5e1b42a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710953831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.3710953831
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.2041841521
Short name T244
Test name
Test status
Simulation time 26749727866 ps
CPU time 684.4 seconds
Started Apr 18 03:41:57 PM PDT 24
Finished Apr 18 03:53:22 PM PDT 24
Peak memory 248848 kb
Host smart-cd2ea9e0-a22a-4464-920d-3d1ba1e865b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041841521 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.2041841521
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.3204278565
Short name T115
Test name
Test status
Simulation time 260101959 ps
CPU time 3.93 seconds
Started Apr 18 03:43:36 PM PDT 24
Finished Apr 18 03:43:41 PM PDT 24
Peak memory 241888 kb
Host smart-576ef4fe-695b-4799-950d-050691750f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204278565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.3204278565
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.4155911391
Short name T57
Test name
Test status
Simulation time 891803281 ps
CPU time 10.54 seconds
Started Apr 18 03:36:07 PM PDT 24
Finished Apr 18 03:36:18 PM PDT 24
Peak memory 242212 kb
Host smart-4f28a170-e125-43c6-b33e-1eed0b2fa8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155911391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.4155911391
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.667430441
Short name T91
Test name
Test status
Simulation time 544381285 ps
CPU time 5.04 seconds
Started Apr 18 03:46:36 PM PDT 24
Finished Apr 18 03:46:42 PM PDT 24
Peak memory 241796 kb
Host smart-e542ada0-4562-45a2-9ce5-0a343833eeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667430441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.667430441
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.1855926984
Short name T495
Test name
Test status
Simulation time 269282698 ps
CPU time 4.3 seconds
Started Apr 18 03:45:09 PM PDT 24
Finished Apr 18 03:45:14 PM PDT 24
Peak memory 241824 kb
Host smart-4aca6f69-6103-4582-8cd5-f077214bafd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855926984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.1855926984
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.2945702872
Short name T60
Test name
Test status
Simulation time 353065821 ps
CPU time 3.63 seconds
Started Apr 18 03:46:00 PM PDT 24
Finished Apr 18 03:46:04 PM PDT 24
Peak memory 241928 kb
Host smart-2e1cf8f2-86b5-4000-a66d-9c05a35670b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945702872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.2945702872
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.447917946
Short name T74
Test name
Test status
Simulation time 32263020050 ps
CPU time 244.17 seconds
Started Apr 18 03:39:51 PM PDT 24
Finished Apr 18 03:43:56 PM PDT 24
Peak memory 259924 kb
Host smart-1c70232b-2ec3-48d9-bc8e-504469bb2f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447917946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.
447917946
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.3906026335
Short name T361
Test name
Test status
Simulation time 568398035 ps
CPU time 10.52 seconds
Started Apr 18 03:38:45 PM PDT 24
Finished Apr 18 03:38:56 PM PDT 24
Peak memory 241876 kb
Host smart-5e5a7d8a-9640-450a-9119-81c86d400ba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906026335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.3906026335
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.4031779781
Short name T452
Test name
Test status
Simulation time 757385206 ps
CPU time 13.74 seconds
Started Apr 18 03:39:14 PM PDT 24
Finished Apr 18 03:39:28 PM PDT 24
Peak memory 241664 kb
Host smart-cd3d47c7-7bcf-44e8-95f0-14296e8c1b4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031779781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.4031779781
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.3504898981
Short name T325
Test name
Test status
Simulation time 43646267474 ps
CPU time 1225.68 seconds
Started Apr 18 03:41:48 PM PDT 24
Finished Apr 18 04:02:14 PM PDT 24
Peak memory 311676 kb
Host smart-ecfc1754-569e-4d9b-aa69-48243e6524d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504898981 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.3504898981
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.283425729
Short name T85
Test name
Test status
Simulation time 461716450 ps
CPU time 4.34 seconds
Started Apr 18 03:47:01 PM PDT 24
Finished Apr 18 03:47:05 PM PDT 24
Peak memory 242124 kb
Host smart-30ad4e16-6b06-4815-ba52-dd510fb59288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283425729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.283425729
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2922706758
Short name T267
Test name
Test status
Simulation time 18929135227 ps
CPU time 27.46 seconds
Started Apr 18 02:27:08 PM PDT 24
Finished Apr 18 02:27:36 PM PDT 24
Peak memory 245720 kb
Host smart-c43e80d2-8c28-4ca2-aa38-68ed4c17d4de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922706758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.2922706758
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.2728936382
Short name T246
Test name
Test status
Simulation time 404848705 ps
CPU time 3.88 seconds
Started Apr 18 03:46:31 PM PDT 24
Finished Apr 18 03:46:35 PM PDT 24
Peak memory 241872 kb
Host smart-0f33b7f2-7d5a-4e6b-b48a-c8e63c041106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728936382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2728936382
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.430590440
Short name T89
Test name
Test status
Simulation time 117282794 ps
CPU time 4.42 seconds
Started Apr 18 03:45:51 PM PDT 24
Finished Apr 18 03:45:56 PM PDT 24
Peak memory 242116 kb
Host smart-cf607fa3-0011-43c1-8507-5e5d527aaf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430590440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.430590440
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.3117973921
Short name T78
Test name
Test status
Simulation time 70956350333 ps
CPU time 191.53 seconds
Started Apr 18 03:40:34 PM PDT 24
Finished Apr 18 03:43:46 PM PDT 24
Peak memory 248724 kb
Host smart-84d26f7b-ee0b-4a30-8d7b-1333ba3caddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117973921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.3117973921
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.2315302048
Short name T235
Test name
Test status
Simulation time 13605724509 ps
CPU time 197.75 seconds
Started Apr 18 03:36:42 PM PDT 24
Finished Apr 18 03:40:00 PM PDT 24
Peak memory 270120 kb
Host smart-702f165d-60ab-4b61-84cc-86a7d81f6eec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315302048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.2315302048
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.3053722548
Short name T401
Test name
Test status
Simulation time 3135528066 ps
CPU time 8.67 seconds
Started Apr 18 03:43:03 PM PDT 24
Finished Apr 18 03:43:13 PM PDT 24
Peak memory 241788 kb
Host smart-6a761cf8-e261-4794-917c-b5b5f0a0c2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053722548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.3053722548
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.971655737
Short name T88
Test name
Test status
Simulation time 1552808972 ps
CPU time 5.64 seconds
Started Apr 18 03:46:16 PM PDT 24
Finished Apr 18 03:46:22 PM PDT 24
Peak memory 241824 kb
Host smart-ad86a4a0-f40d-4c31-8cdc-6196109a0dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971655737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.971655737
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.158644953
Short name T92
Test name
Test status
Simulation time 338752160 ps
CPU time 4.35 seconds
Started Apr 18 03:44:58 PM PDT 24
Finished Apr 18 03:45:03 PM PDT 24
Peak memory 241864 kb
Host smart-b7499345-b2b0-4211-9d53-f1c1ce1a2b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158644953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.158644953
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.1589509876
Short name T127
Test name
Test status
Simulation time 13513971854 ps
CPU time 25.89 seconds
Started Apr 18 03:36:45 PM PDT 24
Finished Apr 18 03:37:11 PM PDT 24
Peak memory 243488 kb
Host smart-e5e81c29-7692-4560-b527-0a01b2c7640b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589509876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.1589509876
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2027353474
Short name T1214
Test name
Test status
Simulation time 134834401 ps
CPU time 6.07 seconds
Started Apr 18 02:26:53 PM PDT 24
Finished Apr 18 02:26:59 PM PDT 24
Peak memory 238052 kb
Host smart-ce0fd46c-d8f1-42b1-a2b0-fe95a2a04ad6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027353474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.2027353474
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.182993901
Short name T296
Test name
Test status
Simulation time 137818767 ps
CPU time 2.58 seconds
Started Apr 18 02:26:51 PM PDT 24
Finished Apr 18 02:26:55 PM PDT 24
Peak memory 239404 kb
Host smart-57718125-0c54-4840-947a-a3444474ffca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182993901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_re
set.182993901
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1820545949
Short name T1289
Test name
Test status
Simulation time 220422920 ps
CPU time 2.16 seconds
Started Apr 18 02:26:56 PM PDT 24
Finished Apr 18 02:26:59 PM PDT 24
Peak memory 239472 kb
Host smart-c4c43b48-25e6-42ef-b482-b3fab8fe92a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820545949 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.1820545949
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.394512953
Short name T1316
Test name
Test status
Simulation time 151176991 ps
CPU time 1.68 seconds
Started Apr 18 02:27:07 PM PDT 24
Finished Apr 18 02:27:09 PM PDT 24
Peak memory 239400 kb
Host smart-a645fbef-d207-4105-842c-8560b1162996
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394512953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.394512953
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3496310743
Short name T1208
Test name
Test status
Simulation time 529778285 ps
CPU time 1.36 seconds
Started Apr 18 02:26:53 PM PDT 24
Finished Apr 18 02:26:55 PM PDT 24
Peak memory 230984 kb
Host smart-12b61cf0-826d-4c74-8b71-adcfb0e9e26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496310743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.3496310743
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.228964535
Short name T1304
Test name
Test status
Simulation time 38588980 ps
CPU time 1.43 seconds
Started Apr 18 02:26:52 PM PDT 24
Finished Apr 18 02:26:55 PM PDT 24
Peak memory 230832 kb
Host smart-31aad2e4-52f1-4aa3-9db5-a804f3e63bdf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228964535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl
_mem_partial_access.228964535
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.2328890277
Short name T1321
Test name
Test status
Simulation time 126888938 ps
CPU time 1.4 seconds
Started Apr 18 02:26:51 PM PDT 24
Finished Apr 18 02:26:54 PM PDT 24
Peak memory 230900 kb
Host smart-f1f9fb60-f612-4590-801d-51a49f14cb1b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328890277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.2328890277
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.2380346364
Short name T1313
Test name
Test status
Simulation time 104686976 ps
CPU time 3.22 seconds
Started Apr 18 02:26:55 PM PDT 24
Finished Apr 18 02:26:59 PM PDT 24
Peak memory 239340 kb
Host smart-08d769f5-fa8e-4e9f-98f9-f77e2efaa389
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380346364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.2380346364
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1430909450
Short name T1320
Test name
Test status
Simulation time 388022281 ps
CPU time 6.6 seconds
Started Apr 18 02:26:48 PM PDT 24
Finished Apr 18 02:26:55 PM PDT 24
Peak memory 247296 kb
Host smart-02eff862-6bbf-4a01-8deb-0546bd6c1694
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430909450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.1430909450
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3111781871
Short name T346
Test name
Test status
Simulation time 863704335 ps
CPU time 11.32 seconds
Started Apr 18 02:26:50 PM PDT 24
Finished Apr 18 02:27:03 PM PDT 24
Peak memory 239696 kb
Host smart-43d18dcf-86a9-448b-b44f-b63810b1f4b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111781871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.3111781871
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1619057469
Short name T1268
Test name
Test status
Simulation time 864930710 ps
CPU time 3.77 seconds
Started Apr 18 02:26:55 PM PDT 24
Finished Apr 18 02:27:00 PM PDT 24
Peak memory 239248 kb
Host smart-7140d834-e6bb-4320-9e4a-98e993bca85d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619057469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.1619057469
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.4146690434
Short name T293
Test name
Test status
Simulation time 2009534112 ps
CPU time 7.94 seconds
Started Apr 18 02:26:53 PM PDT 24
Finished Apr 18 02:27:02 PM PDT 24
Peak memory 240840 kb
Host smart-e081e10f-691a-4149-a7be-3a10f48ed932
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146690434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.4146690434
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1507725767
Short name T1314
Test name
Test status
Simulation time 362086243 ps
CPU time 2.25 seconds
Started Apr 18 02:26:50 PM PDT 24
Finished Apr 18 02:26:54 PM PDT 24
Peak memory 238212 kb
Host smart-7ab36169-457a-4ea5-914f-712a0def49f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507725767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.1507725767
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3589759660
Short name T1308
Test name
Test status
Simulation time 132458386 ps
CPU time 2.88 seconds
Started Apr 18 02:26:53 PM PDT 24
Finished Apr 18 02:26:57 PM PDT 24
Peak memory 247564 kb
Host smart-e4d70440-1c27-491e-8407-1b6830576bd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589759660 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.3589759660
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.115829194
Short name T1267
Test name
Test status
Simulation time 161959922 ps
CPU time 1.99 seconds
Started Apr 18 02:26:49 PM PDT 24
Finished Apr 18 02:26:53 PM PDT 24
Peak memory 240584 kb
Host smart-6e1d5226-7f58-4da9-bd64-47457a658470
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115829194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.115829194
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2720681526
Short name T1242
Test name
Test status
Simulation time 74924126 ps
CPU time 1.41 seconds
Started Apr 18 02:26:53 PM PDT 24
Finished Apr 18 02:26:56 PM PDT 24
Peak memory 231152 kb
Host smart-9cad502e-5628-4fd3-bd55-6fd6b7e8fd6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720681526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.2720681526
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2445773141
Short name T1295
Test name
Test status
Simulation time 45354392 ps
CPU time 1.37 seconds
Started Apr 18 02:26:50 PM PDT 24
Finished Apr 18 02:26:52 PM PDT 24
Peak memory 230496 kb
Host smart-d729d774-3ded-4f5a-8cf3-fe6d790f7196
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445773141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.2445773141
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1358580611
Short name T1282
Test name
Test status
Simulation time 37449071 ps
CPU time 1.32 seconds
Started Apr 18 02:26:50 PM PDT 24
Finished Apr 18 02:26:53 PM PDT 24
Peak memory 230996 kb
Host smart-ceb01581-c557-48a9-95b9-0aa22cc500d6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358580611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.1358580611
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.4012792464
Short name T1284
Test name
Test status
Simulation time 92795870 ps
CPU time 1.97 seconds
Started Apr 18 02:26:49 PM PDT 24
Finished Apr 18 02:26:53 PM PDT 24
Peak memory 239488 kb
Host smart-5727d50f-bd91-45c7-85e1-0e79e461cb57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012792464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.4012792464
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2107609745
Short name T1235
Test name
Test status
Simulation time 278155178 ps
CPU time 6.49 seconds
Started Apr 18 02:26:50 PM PDT 24
Finished Apr 18 02:26:58 PM PDT 24
Peak memory 247096 kb
Host smart-d0db3439-2b21-4952-add4-39f1372542f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107609745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.2107609745
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3697250924
Short name T268
Test name
Test status
Simulation time 20145869716 ps
CPU time 19.51 seconds
Started Apr 18 02:26:50 PM PDT 24
Finished Apr 18 02:27:11 PM PDT 24
Peak memory 245844 kb
Host smart-27634a7f-8e94-4a56-86e0-49c58be04269
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697250924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.3697250924
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.738109197
Short name T1285
Test name
Test status
Simulation time 360769042 ps
CPU time 2.92 seconds
Started Apr 18 02:27:04 PM PDT 24
Finished Apr 18 02:27:08 PM PDT 24
Peak memory 247604 kb
Host smart-18b860f7-2b28-499a-aeea-8946960b36f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738109197 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.738109197
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.280312135
Short name T303
Test name
Test status
Simulation time 47465307 ps
CPU time 1.64 seconds
Started Apr 18 02:27:05 PM PDT 24
Finished Apr 18 02:27:07 PM PDT 24
Peak memory 241844 kb
Host smart-7164c562-9412-4c60-8bed-3f1b8271ef0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280312135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.280312135
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3381451472
Short name T1299
Test name
Test status
Simulation time 168752694 ps
CPU time 1.41 seconds
Started Apr 18 02:27:04 PM PDT 24
Finished Apr 18 02:27:06 PM PDT 24
Peak memory 231000 kb
Host smart-608aa09f-392c-4699-9613-6eb036b85085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381451472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.3381451472
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2215252968
Short name T1223
Test name
Test status
Simulation time 140830180 ps
CPU time 3.67 seconds
Started Apr 18 02:27:06 PM PDT 24
Finished Apr 18 02:27:11 PM PDT 24
Peak memory 238160 kb
Host smart-7a3469b8-72e5-4093-a242-23a27f79be05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215252968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.2215252968
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.2281662137
Short name T1228
Test name
Test status
Simulation time 151245425 ps
CPU time 3.13 seconds
Started Apr 18 02:27:05 PM PDT 24
Finished Apr 18 02:27:09 PM PDT 24
Peak memory 246248 kb
Host smart-00d36a0f-ffe6-4696-9bad-c014ffb1810a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281662137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.2281662137
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.583529330
Short name T342
Test name
Test status
Simulation time 2523332903 ps
CPU time 19.72 seconds
Started Apr 18 02:27:17 PM PDT 24
Finished Apr 18 02:27:38 PM PDT 24
Peak memory 245376 kb
Host smart-88cf5730-f719-4d50-887c-d76d375f551a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583529330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_in
tg_err.583529330
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3932791821
Short name T1317
Test name
Test status
Simulation time 211214358 ps
CPU time 4.33 seconds
Started Apr 18 02:27:07 PM PDT 24
Finished Apr 18 02:27:12 PM PDT 24
Peak memory 247688 kb
Host smart-1be37070-4722-4ef0-800c-a019939b1389
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932791821 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.3932791821
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3416928332
Short name T1294
Test name
Test status
Simulation time 587530674 ps
CPU time 1.76 seconds
Started Apr 18 02:27:07 PM PDT 24
Finished Apr 18 02:27:09 PM PDT 24
Peak memory 241428 kb
Host smart-0b04f505-dbee-4f81-9a48-2874bb3e5896
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416928332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.3416928332
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1344962046
Short name T1203
Test name
Test status
Simulation time 45164556 ps
CPU time 1.37 seconds
Started Apr 18 02:27:02 PM PDT 24
Finished Apr 18 02:27:04 PM PDT 24
Peak memory 231196 kb
Host smart-bd1c9d8a-1b25-4153-9e98-73d1da874078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344962046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.1344962046
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2805501571
Short name T1248
Test name
Test status
Simulation time 183143322 ps
CPU time 7.29 seconds
Started Apr 18 02:27:06 PM PDT 24
Finished Apr 18 02:27:14 PM PDT 24
Peak memory 246444 kb
Host smart-53b2157a-3113-4db6-a9a8-2a32a4258d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805501571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.2805501571
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3253383040
Short name T263
Test name
Test status
Simulation time 1263274786 ps
CPU time 11.56 seconds
Started Apr 18 02:27:17 PM PDT 24
Finished Apr 18 02:27:29 PM PDT 24
Peak memory 244452 kb
Host smart-176e795c-c2f2-484f-a7f1-815c022c1135
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253383040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.3253383040
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.124137647
Short name T1259
Test name
Test status
Simulation time 286483382 ps
CPU time 3.39 seconds
Started Apr 18 02:27:06 PM PDT 24
Finished Apr 18 02:27:10 PM PDT 24
Peak memory 247636 kb
Host smart-754980d7-8582-4953-962f-f223e87a87b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124137647 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.124137647
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.3283635448
Short name T299
Test name
Test status
Simulation time 617202280 ps
CPU time 1.87 seconds
Started Apr 18 02:27:12 PM PDT 24
Finished Apr 18 02:27:15 PM PDT 24
Peak memory 241556 kb
Host smart-f301dc49-97ec-42ad-8774-098cb65c4c3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283635448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.3283635448
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.766227596
Short name T1291
Test name
Test status
Simulation time 534267531 ps
CPU time 1.56 seconds
Started Apr 18 02:27:03 PM PDT 24
Finished Apr 18 02:27:05 PM PDT 24
Peak memory 231204 kb
Host smart-6a18fe5b-6343-49b1-a7c3-833ce66968ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766227596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.766227596
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3018965662
Short name T316
Test name
Test status
Simulation time 83624535 ps
CPU time 2.39 seconds
Started Apr 18 02:27:09 PM PDT 24
Finished Apr 18 02:27:12 PM PDT 24
Peak memory 238232 kb
Host smart-1992440f-d956-4fe7-839d-c30b6f719077
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018965662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.3018965662
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1429084456
Short name T1250
Test name
Test status
Simulation time 282667434 ps
CPU time 4.9 seconds
Started Apr 18 02:27:06 PM PDT 24
Finished Apr 18 02:27:11 PM PDT 24
Peak memory 247008 kb
Host smart-755ad8ca-15ff-4627-b3d8-0fe73d1698d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429084456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.1429084456
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.71562919
Short name T262
Test name
Test status
Simulation time 10356707780 ps
CPU time 27.49 seconds
Started Apr 18 02:27:06 PM PDT 24
Finished Apr 18 02:27:34 PM PDT 24
Peak memory 244576 kb
Host smart-713daef2-6faa-4f1d-91bb-bde15e9ea235
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71562919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_int
g_err.71562919
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.552889742
Short name T1315
Test name
Test status
Simulation time 111393409 ps
CPU time 2.86 seconds
Started Apr 18 02:27:08 PM PDT 24
Finished Apr 18 02:27:12 PM PDT 24
Peak memory 247564 kb
Host smart-3d1afc52-5faf-4522-a026-5317d4e84056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552889742 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.552889742
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.284409514
Short name T298
Test name
Test status
Simulation time 48483317 ps
CPU time 1.72 seconds
Started Apr 18 02:27:06 PM PDT 24
Finished Apr 18 02:27:09 PM PDT 24
Peak memory 241936 kb
Host smart-db36f6cb-5176-4f46-af15-9eebbc3568ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284409514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.284409514
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.250535310
Short name T1297
Test name
Test status
Simulation time 43707191 ps
CPU time 1.4 seconds
Started Apr 18 02:27:07 PM PDT 24
Finished Apr 18 02:27:09 PM PDT 24
Peak memory 231164 kb
Host smart-340f4a20-6606-4a09-a6a7-4ce395810834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250535310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.250535310
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3033404256
Short name T264
Test name
Test status
Simulation time 369805534 ps
CPU time 3.61 seconds
Started Apr 18 02:27:12 PM PDT 24
Finished Apr 18 02:27:16 PM PDT 24
Peak memory 239384 kb
Host smart-4c9eafbb-b1f0-4679-9e02-de555ecf75b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033404256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.3033404256
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1785350585
Short name T1290
Test name
Test status
Simulation time 125372365 ps
CPU time 4.63 seconds
Started Apr 18 02:27:04 PM PDT 24
Finished Apr 18 02:27:09 PM PDT 24
Peak memory 247584 kb
Host smart-63a32040-ec2e-49b3-bd3f-65afaca542fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785350585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.1785350585
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3895197437
Short name T345
Test name
Test status
Simulation time 5413366708 ps
CPU time 23.61 seconds
Started Apr 18 02:27:03 PM PDT 24
Finished Apr 18 02:27:27 PM PDT 24
Peak memory 244592 kb
Host smart-feb2f188-539c-4794-8203-a07d640d7490
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895197437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.3895197437
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.3567479932
Short name T1227
Test name
Test status
Simulation time 211148008 ps
CPU time 3.22 seconds
Started Apr 18 02:27:11 PM PDT 24
Finished Apr 18 02:27:15 PM PDT 24
Peak memory 246808 kb
Host smart-dbcb3f59-99da-4c63-a167-65baf0de0738
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567479932 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.3567479932
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2187861033
Short name T290
Test name
Test status
Simulation time 50157225 ps
CPU time 1.6 seconds
Started Apr 18 02:27:12 PM PDT 24
Finished Apr 18 02:27:14 PM PDT 24
Peak memory 240928 kb
Host smart-a18da259-27de-4269-9ed2-7d119f0f178d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187861033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.2187861033
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2844006451
Short name T1303
Test name
Test status
Simulation time 55896266 ps
CPU time 1.45 seconds
Started Apr 18 02:27:18 PM PDT 24
Finished Apr 18 02:27:20 PM PDT 24
Peak memory 231192 kb
Host smart-4e02f3bd-40f4-4407-a4e3-c9563be6fad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844006451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.2844006451
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2243973913
Short name T1241
Test name
Test status
Simulation time 510786492 ps
CPU time 3.91 seconds
Started Apr 18 02:27:10 PM PDT 24
Finished Apr 18 02:27:14 PM PDT 24
Peak memory 239384 kb
Host smart-788685cf-5d31-4fe7-97e2-645a3df989bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243973913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.2243973913
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.570014463
Short name T1233
Test name
Test status
Simulation time 78297742 ps
CPU time 5.14 seconds
Started Apr 18 02:27:10 PM PDT 24
Finished Apr 18 02:27:16 PM PDT 24
Peak memory 246904 kb
Host smart-cf640ac0-092a-435d-8088-fa28ce9c37ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570014463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.570014463
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.855252078
Short name T1244
Test name
Test status
Simulation time 736120329 ps
CPU time 9.99 seconds
Started Apr 18 02:27:15 PM PDT 24
Finished Apr 18 02:27:26 PM PDT 24
Peak memory 244204 kb
Host smart-d897e04c-4933-48e9-b6b2-600db9d49b89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855252078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_in
tg_err.855252078
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1558001808
Short name T1261
Test name
Test status
Simulation time 1173894407 ps
CPU time 2.79 seconds
Started Apr 18 02:27:09 PM PDT 24
Finished Apr 18 02:27:13 PM PDT 24
Peak memory 239452 kb
Host smart-35130bf6-dd5b-408e-a013-0cc45e3e1672
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558001808 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.1558001808
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.123001728
Short name T302
Test name
Test status
Simulation time 158281601 ps
CPU time 1.7 seconds
Started Apr 18 02:27:19 PM PDT 24
Finished Apr 18 02:27:21 PM PDT 24
Peak memory 241948 kb
Host smart-a697a435-18ab-4ea0-a797-66919b04bcea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123001728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.123001728
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.4219881606
Short name T1215
Test name
Test status
Simulation time 74195833 ps
CPU time 1.52 seconds
Started Apr 18 02:27:12 PM PDT 24
Finished Apr 18 02:27:14 PM PDT 24
Peak memory 231112 kb
Host smart-b085ddcb-9d02-47d7-9e5f-42ada1d4a626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219881606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.4219881606
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3976378971
Short name T311
Test name
Test status
Simulation time 71465489 ps
CPU time 2.15 seconds
Started Apr 18 02:27:11 PM PDT 24
Finished Apr 18 02:27:14 PM PDT 24
Peak memory 239460 kb
Host smart-3643afc8-9404-4432-8caf-45f21c1c455c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976378971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.3976378971
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.4214663678
Short name T1253
Test name
Test status
Simulation time 141834839 ps
CPU time 5.13 seconds
Started Apr 18 02:27:09 PM PDT 24
Finished Apr 18 02:27:14 PM PDT 24
Peak memory 239548 kb
Host smart-49e527e1-ef3d-4a9f-b393-6d80f25cb9e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214663678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.4214663678
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2526142609
Short name T1293
Test name
Test status
Simulation time 1765408397 ps
CPU time 5.15 seconds
Started Apr 18 02:27:09 PM PDT 24
Finished Apr 18 02:27:15 PM PDT 24
Peak memory 246796 kb
Host smart-fb0bdc3a-68d3-45fb-adde-c277d3497c76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526142609 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.2526142609
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.601749348
Short name T317
Test name
Test status
Simulation time 47690335 ps
CPU time 1.72 seconds
Started Apr 18 02:27:18 PM PDT 24
Finished Apr 18 02:27:20 PM PDT 24
Peak memory 241620 kb
Host smart-29edf66f-f1b1-4f43-9c7b-60170b8eecbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601749348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.601749348
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.2447049402
Short name T1199
Test name
Test status
Simulation time 36393320 ps
CPU time 1.47 seconds
Started Apr 18 02:27:19 PM PDT 24
Finished Apr 18 02:27:21 PM PDT 24
Peak memory 231128 kb
Host smart-f9b1ef11-37ca-4ee5-9aaa-19a8ea90c5c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447049402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.2447049402
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2489111600
Short name T314
Test name
Test status
Simulation time 74208615 ps
CPU time 2.47 seconds
Started Apr 18 02:27:19 PM PDT 24
Finished Apr 18 02:27:22 PM PDT 24
Peak memory 239312 kb
Host smart-403a8442-38b7-4dda-b2c1-1add36edd12a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489111600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.2489111600
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.173858550
Short name T1283
Test name
Test status
Simulation time 1575009811 ps
CPU time 5.71 seconds
Started Apr 18 02:27:10 PM PDT 24
Finished Apr 18 02:27:16 PM PDT 24
Peak memory 246816 kb
Host smart-e22fe3bc-2675-496e-803f-4be9b629d70c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173858550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.173858550
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.395695691
Short name T343
Test name
Test status
Simulation time 2515706137 ps
CPU time 21.93 seconds
Started Apr 18 02:27:10 PM PDT 24
Finished Apr 18 02:27:33 PM PDT 24
Peak memory 244268 kb
Host smart-6de1a23a-370e-42d2-8ce7-0deed6ae04dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395695691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_in
tg_err.395695691
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.640635291
Short name T1218
Test name
Test status
Simulation time 1741747712 ps
CPU time 3.53 seconds
Started Apr 18 02:27:16 PM PDT 24
Finished Apr 18 02:27:20 PM PDT 24
Peak memory 239528 kb
Host smart-703218b8-34fb-40cc-a2de-74c259ef5116
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640635291 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.640635291
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.831931284
Short name T294
Test name
Test status
Simulation time 71277897 ps
CPU time 1.76 seconds
Started Apr 18 02:27:10 PM PDT 24
Finished Apr 18 02:27:12 PM PDT 24
Peak memory 239420 kb
Host smart-8395cc8d-4fa4-4618-ad07-7738304268d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831931284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.831931284
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.3369738987
Short name T1202
Test name
Test status
Simulation time 71041048 ps
CPU time 1.39 seconds
Started Apr 18 02:27:10 PM PDT 24
Finished Apr 18 02:27:12 PM PDT 24
Peak memory 230060 kb
Host smart-ce324665-b414-43e0-a70c-4342410c845d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369738987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.3369738987
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1162776109
Short name T1236
Test name
Test status
Simulation time 177856361 ps
CPU time 2.11 seconds
Started Apr 18 02:27:12 PM PDT 24
Finished Apr 18 02:27:15 PM PDT 24
Peak memory 239324 kb
Host smart-298392a0-fc27-454f-84a7-c1d8302cc493
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162776109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.1162776109
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3024315994
Short name T1249
Test name
Test status
Simulation time 204119345 ps
CPU time 3.39 seconds
Started Apr 18 02:27:11 PM PDT 24
Finished Apr 18 02:27:15 PM PDT 24
Peak memory 246184 kb
Host smart-acb17cc4-008b-42db-a287-a42dc7b57c70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024315994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.3024315994
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3864003573
Short name T1274
Test name
Test status
Simulation time 408761632 ps
CPU time 4.45 seconds
Started Apr 18 02:27:12 PM PDT 24
Finished Apr 18 02:27:17 PM PDT 24
Peak memory 247588 kb
Host smart-cfc4a7d4-b63d-439b-b5c3-babb934ceb7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864003573 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.3864003573
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.2469018299
Short name T309
Test name
Test status
Simulation time 80446672 ps
CPU time 1.85 seconds
Started Apr 18 02:27:12 PM PDT 24
Finished Apr 18 02:27:15 PM PDT 24
Peak memory 240568 kb
Host smart-4b0e0332-2a9d-4d02-bcba-e9f1546f4fea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469018299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.2469018299
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.868502420
Short name T1270
Test name
Test status
Simulation time 40786303 ps
CPU time 1.4 seconds
Started Apr 18 02:27:09 PM PDT 24
Finished Apr 18 02:27:11 PM PDT 24
Peak memory 231056 kb
Host smart-72fad899-4a0c-4974-9c82-75711eb4a04a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868502420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.868502420
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.4067382798
Short name T1318
Test name
Test status
Simulation time 131767417 ps
CPU time 2.24 seconds
Started Apr 18 02:27:12 PM PDT 24
Finished Apr 18 02:27:15 PM PDT 24
Peak memory 239264 kb
Host smart-dca6b17e-286c-4110-b87d-4a6955c0572f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067382798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.4067382798
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.4289873803
Short name T1256
Test name
Test status
Simulation time 287506259 ps
CPU time 4.73 seconds
Started Apr 18 02:27:12 PM PDT 24
Finished Apr 18 02:27:17 PM PDT 24
Peak memory 246904 kb
Host smart-3e6b664c-f623-491d-92a2-6a613d95f0cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289873803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.4289873803
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1930518854
Short name T341
Test name
Test status
Simulation time 707590606 ps
CPU time 9.59 seconds
Started Apr 18 02:27:18 PM PDT 24
Finished Apr 18 02:27:28 PM PDT 24
Peak memory 239336 kb
Host smart-2e5d4446-8b06-4d61-bec1-b96f955ad6ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930518854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.1930518854
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.702132251
Short name T1277
Test name
Test status
Simulation time 139268394 ps
CPU time 2.57 seconds
Started Apr 18 02:27:10 PM PDT 24
Finished Apr 18 02:27:13 PM PDT 24
Peak memory 247656 kb
Host smart-17ff1247-7784-4ee6-a285-65200e00b095
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702132251 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.702132251
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3920471644
Short name T289
Test name
Test status
Simulation time 561604346 ps
CPU time 2.2 seconds
Started Apr 18 02:27:15 PM PDT 24
Finished Apr 18 02:27:18 PM PDT 24
Peak memory 239808 kb
Host smart-3ce1bc86-ec45-4ef4-a621-8c5a72fd8248
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920471644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.3920471644
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.2253538
Short name T1201
Test name
Test status
Simulation time 39933335 ps
CPU time 1.38 seconds
Started Apr 18 02:27:09 PM PDT 24
Finished Apr 18 02:27:11 PM PDT 24
Peak memory 231176 kb
Host smart-1df9e779-8a7d-4f95-b868-d9822a627ae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.2253538
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.2183620897
Short name T1280
Test name
Test status
Simulation time 91789616 ps
CPU time 2.77 seconds
Started Apr 18 02:27:12 PM PDT 24
Finished Apr 18 02:27:15 PM PDT 24
Peak memory 238232 kb
Host smart-57f50b16-7b22-4d11-b4d4-2d3c9c2babcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183620897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.2183620897
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3138484281
Short name T1272
Test name
Test status
Simulation time 145912209 ps
CPU time 4.65 seconds
Started Apr 18 02:27:16 PM PDT 24
Finished Apr 18 02:27:21 PM PDT 24
Peak memory 247028 kb
Host smart-a640c434-8e16-42a1-ac58-3ae5cf90fe7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138484281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.3138484281
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3468364635
Short name T308
Test name
Test status
Simulation time 159656176 ps
CPU time 4.82 seconds
Started Apr 18 02:26:55 PM PDT 24
Finished Apr 18 02:27:01 PM PDT 24
Peak memory 231196 kb
Host smart-5a32dbaa-9272-40f0-b851-b43c0e220d26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468364635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.3468364635
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2524600550
Short name T305
Test name
Test status
Simulation time 128730945 ps
CPU time 6.14 seconds
Started Apr 18 02:26:53 PM PDT 24
Finished Apr 18 02:27:01 PM PDT 24
Peak memory 239452 kb
Host smart-3325abbd-c387-43ea-b37d-b54400e5e80e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524600550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.2524600550
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2806482033
Short name T300
Test name
Test status
Simulation time 65601607 ps
CPU time 1.86 seconds
Started Apr 18 02:26:55 PM PDT 24
Finished Apr 18 02:26:58 PM PDT 24
Peak memory 239428 kb
Host smart-961fac40-c0eb-4d8f-84a9-29e3b6a384bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806482033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.2806482033
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.795819141
Short name T1204
Test name
Test status
Simulation time 280922773 ps
CPU time 2.86 seconds
Started Apr 18 02:26:59 PM PDT 24
Finished Apr 18 02:27:03 PM PDT 24
Peak memory 245664 kb
Host smart-bae36784-37d4-4c3c-bc34-790b3b89ab93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795819141 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.795819141
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.633984039
Short name T1275
Test name
Test status
Simulation time 535285013 ps
CPU time 2.06 seconds
Started Apr 18 02:26:50 PM PDT 24
Finished Apr 18 02:26:54 PM PDT 24
Peak memory 239380 kb
Host smart-54408de1-388e-486c-befd-a359941aa9ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633984039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.633984039
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.1392212984
Short name T1278
Test name
Test status
Simulation time 78222862 ps
CPU time 1.54 seconds
Started Apr 18 02:26:54 PM PDT 24
Finished Apr 18 02:26:56 PM PDT 24
Peak memory 231160 kb
Host smart-aa395e54-fe03-47cf-a581-f00361062428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392212984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.1392212984
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.263265106
Short name T1254
Test name
Test status
Simulation time 74055584 ps
CPU time 1.34 seconds
Started Apr 18 02:27:00 PM PDT 24
Finished Apr 18 02:27:02 PM PDT 24
Peak memory 230528 kb
Host smart-22cab156-9126-4563-af8e-030f73dc3d7f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263265106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl
_mem_partial_access.263265106
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.4092295863
Short name T1305
Test name
Test status
Simulation time 70274472 ps
CPU time 1.41 seconds
Started Apr 18 02:26:55 PM PDT 24
Finished Apr 18 02:26:57 PM PDT 24
Peak memory 230708 kb
Host smart-a58dcb75-50a5-4cc3-9d7d-f6d2a95a7d8f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092295863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.4092295863
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2246501384
Short name T313
Test name
Test status
Simulation time 160821516 ps
CPU time 2.76 seconds
Started Apr 18 02:26:56 PM PDT 24
Finished Apr 18 02:27:00 PM PDT 24
Peak memory 239568 kb
Host smart-2be85caf-0b7d-428b-a084-a567529e7b0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246501384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.2246501384
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.922734304
Short name T1212
Test name
Test status
Simulation time 1226439291 ps
CPU time 4 seconds
Started Apr 18 02:26:50 PM PDT 24
Finished Apr 18 02:26:55 PM PDT 24
Peak memory 246652 kb
Host smart-9d7ff0aa-f759-441b-a3b2-246e4adec8de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922734304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.922734304
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.735823856
Short name T344
Test name
Test status
Simulation time 2418676996 ps
CPU time 18.07 seconds
Started Apr 18 02:26:49 PM PDT 24
Finished Apr 18 02:27:09 PM PDT 24
Peak memory 239508 kb
Host smart-0da66bd5-4e35-412c-a7c9-c85ec4c10085
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735823856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_int
g_err.735823856
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.523555535
Short name T1324
Test name
Test status
Simulation time 42889966 ps
CPU time 1.45 seconds
Started Apr 18 02:27:19 PM PDT 24
Finished Apr 18 02:27:21 PM PDT 24
Peak memory 229728 kb
Host smart-8f841ea6-4c07-4a50-8e3b-5666d4968a08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523555535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.523555535
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.849825750
Short name T1264
Test name
Test status
Simulation time 134499113 ps
CPU time 1.47 seconds
Started Apr 18 02:27:12 PM PDT 24
Finished Apr 18 02:27:14 PM PDT 24
Peak memory 231196 kb
Host smart-18b1bf81-e775-4fd8-962a-097fe3453229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849825750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.849825750
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1429262792
Short name T1220
Test name
Test status
Simulation time 73010836 ps
CPU time 1.43 seconds
Started Apr 18 02:27:13 PM PDT 24
Finished Apr 18 02:27:15 PM PDT 24
Peak memory 229792 kb
Host smart-5bbf8f2a-5f46-4c1a-a668-95f4a399611e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429262792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.1429262792
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2714917256
Short name T1257
Test name
Test status
Simulation time 41223536 ps
CPU time 1.42 seconds
Started Apr 18 02:27:28 PM PDT 24
Finished Apr 18 02:27:31 PM PDT 24
Peak memory 231160 kb
Host smart-f6f67f01-9cfe-42dd-9c59-d4790c7d6f30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714917256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.2714917256
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3165360645
Short name T1271
Test name
Test status
Simulation time 150408764 ps
CPU time 1.42 seconds
Started Apr 18 02:27:16 PM PDT 24
Finished Apr 18 02:27:18 PM PDT 24
Peak memory 231116 kb
Host smart-95fe9435-1505-48ac-b153-578560c45ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165360645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3165360645
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.3681727867
Short name T1210
Test name
Test status
Simulation time 75566713 ps
CPU time 1.47 seconds
Started Apr 18 02:27:15 PM PDT 24
Finished Apr 18 02:27:17 PM PDT 24
Peak memory 230996 kb
Host smart-37dd4917-fcc0-4a9c-85cc-606e326d62fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681727867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.3681727867
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.3818476558
Short name T1209
Test name
Test status
Simulation time 37336709 ps
CPU time 1.46 seconds
Started Apr 18 02:27:17 PM PDT 24
Finished Apr 18 02:27:19 PM PDT 24
Peak memory 231072 kb
Host smart-73dc42f7-7b68-449d-b4fc-533489f84a4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818476558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.3818476558
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1355163002
Short name T1306
Test name
Test status
Simulation time 38629285 ps
CPU time 1.47 seconds
Started Apr 18 02:27:14 PM PDT 24
Finished Apr 18 02:27:16 PM PDT 24
Peak memory 229848 kb
Host smart-08f87a4c-5e39-427c-8225-b7edb068ed0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355163002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.1355163002
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1373870414
Short name T1243
Test name
Test status
Simulation time 140481453 ps
CPU time 1.48 seconds
Started Apr 18 02:27:19 PM PDT 24
Finished Apr 18 02:27:22 PM PDT 24
Peak memory 231232 kb
Host smart-da92c3a2-65bd-49cc-9d38-88efec6b80af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373870414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.1373870414
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1260737132
Short name T1319
Test name
Test status
Simulation time 571818117 ps
CPU time 1.69 seconds
Started Apr 18 02:27:17 PM PDT 24
Finished Apr 18 02:27:20 PM PDT 24
Peak memory 231176 kb
Host smart-24d5d5cc-c1f4-437d-94b4-b4a50137be10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260737132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1260737132
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.71137251
Short name T1292
Test name
Test status
Simulation time 98559277 ps
CPU time 3.67 seconds
Started Apr 18 02:26:53 PM PDT 24
Finished Apr 18 02:26:58 PM PDT 24
Peak memory 238564 kb
Host smart-df09d3b2-83b2-44f7-9a4a-e506d74fca59
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71137251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasi
ng.71137251
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3496677827
Short name T1312
Test name
Test status
Simulation time 235954113 ps
CPU time 3.98 seconds
Started Apr 18 02:26:53 PM PDT 24
Finished Apr 18 02:26:57 PM PDT 24
Peak memory 240508 kb
Host smart-af2438dc-09db-4245-98f6-41f950cafd99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496677827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.3496677827
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1839024070
Short name T1237
Test name
Test status
Simulation time 92914623 ps
CPU time 2.41 seconds
Started Apr 18 02:26:55 PM PDT 24
Finished Apr 18 02:26:58 PM PDT 24
Peak memory 237964 kb
Host smart-346c1953-b136-45f6-8828-3736958ae9e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839024070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.1839024070
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2260361031
Short name T1231
Test name
Test status
Simulation time 76276790 ps
CPU time 2.29 seconds
Started Apr 18 02:26:55 PM PDT 24
Finished Apr 18 02:26:58 PM PDT 24
Peak memory 246684 kb
Host smart-23fc2328-bdf4-4374-ace8-6a1802e2a787
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260361031 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.2260361031
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3400342324
Short name T301
Test name
Test status
Simulation time 158809016 ps
CPU time 1.81 seconds
Started Apr 18 02:27:00 PM PDT 24
Finished Apr 18 02:27:03 PM PDT 24
Peak memory 241652 kb
Host smart-550cafa6-336b-437f-94f5-e3f289e9deb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400342324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.3400342324
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.3857202995
Short name T1281
Test name
Test status
Simulation time 57122228 ps
CPU time 1.44 seconds
Started Apr 18 02:26:53 PM PDT 24
Finished Apr 18 02:26:56 PM PDT 24
Peak memory 231004 kb
Host smart-d23595d3-8ed9-4490-af2f-56c5927e3ac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857202995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.3857202995
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1023396208
Short name T1217
Test name
Test status
Simulation time 533338826 ps
CPU time 1.44 seconds
Started Apr 18 02:26:53 PM PDT 24
Finished Apr 18 02:26:55 PM PDT 24
Peak memory 230888 kb
Host smart-5f747ef4-b839-429e-a31c-249f3b300ac8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023396208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.1023396208
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3134074923
Short name T1255
Test name
Test status
Simulation time 131576824 ps
CPU time 1.36 seconds
Started Apr 18 02:26:53 PM PDT 24
Finished Apr 18 02:26:56 PM PDT 24
Peak memory 230936 kb
Host smart-93e3526d-958e-4bed-938a-4f9663224a9c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134074923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.3134074923
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.363456336
Short name T1286
Test name
Test status
Simulation time 246277544 ps
CPU time 3.53 seconds
Started Apr 18 02:26:56 PM PDT 24
Finished Apr 18 02:27:01 PM PDT 24
Peak memory 239400 kb
Host smart-f83ae42b-b750-44ef-b52b-2068a3e01dfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363456336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ct
rl_same_csr_outstanding.363456336
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.918627480
Short name T1302
Test name
Test status
Simulation time 651762773 ps
CPU time 7.09 seconds
Started Apr 18 02:26:55 PM PDT 24
Finished Apr 18 02:27:03 PM PDT 24
Peak memory 239404 kb
Host smart-6f7e37f4-37b1-479e-863c-67dbd547d4cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918627480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.918627480
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.2742038755
Short name T1273
Test name
Test status
Simulation time 41275933 ps
CPU time 1.41 seconds
Started Apr 18 02:27:19 PM PDT 24
Finished Apr 18 02:27:21 PM PDT 24
Peak memory 231220 kb
Host smart-d52cf9ea-edaf-441a-a1b5-53ecadb136e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742038755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.2742038755
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.781378992
Short name T1265
Test name
Test status
Simulation time 43440662 ps
CPU time 1.52 seconds
Started Apr 18 02:27:17 PM PDT 24
Finished Apr 18 02:27:20 PM PDT 24
Peak memory 230092 kb
Host smart-8cb7e2c9-8cf8-49d3-8eb5-2592b55c76c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781378992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.781378992
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2240230797
Short name T1205
Test name
Test status
Simulation time 559831453 ps
CPU time 1.57 seconds
Started Apr 18 02:27:19 PM PDT 24
Finished Apr 18 02:27:22 PM PDT 24
Peak memory 230124 kb
Host smart-b89521c9-27c9-41c7-8cb8-558bc7e13f68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240230797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.2240230797
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.2777847895
Short name T1322
Test name
Test status
Simulation time 73013923 ps
CPU time 1.47 seconds
Started Apr 18 02:27:16 PM PDT 24
Finished Apr 18 02:27:18 PM PDT 24
Peak memory 231200 kb
Host smart-110c3aaa-d86f-4811-aee2-ae8e5bfb0a2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777847895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.2777847895
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.2046348659
Short name T1232
Test name
Test status
Simulation time 41564707 ps
CPU time 1.52 seconds
Started Apr 18 02:27:16 PM PDT 24
Finished Apr 18 02:27:18 PM PDT 24
Peak memory 231132 kb
Host smart-e7475a2c-2493-4837-b45a-0d236a938937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046348659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.2046348659
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.1659310416
Short name T1300
Test name
Test status
Simulation time 39768436 ps
CPU time 1.36 seconds
Started Apr 18 02:27:14 PM PDT 24
Finished Apr 18 02:27:16 PM PDT 24
Peak memory 231384 kb
Host smart-dfffc641-825a-4104-aeff-653fdd82feed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659310416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.1659310416
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.346230091
Short name T1213
Test name
Test status
Simulation time 543269670 ps
CPU time 1.46 seconds
Started Apr 18 02:27:17 PM PDT 24
Finished Apr 18 02:27:19 PM PDT 24
Peak memory 231176 kb
Host smart-e41bfa6b-81f2-4374-8cc4-fda884a73fa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346230091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.346230091
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3436401923
Short name T1311
Test name
Test status
Simulation time 53826728 ps
CPU time 1.47 seconds
Started Apr 18 02:27:19 PM PDT 24
Finished Apr 18 02:27:21 PM PDT 24
Peak memory 231144 kb
Host smart-f0ccad4e-5b49-488b-99b1-b7b96130474a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436401923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.3436401923
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.1220667036
Short name T1207
Test name
Test status
Simulation time 81860950 ps
CPU time 1.49 seconds
Started Apr 18 02:27:14 PM PDT 24
Finished Apr 18 02:27:16 PM PDT 24
Peak memory 231148 kb
Host smart-1eb904a2-5a6d-4740-a29b-c82cb4649fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220667036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.1220667036
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.1709389139
Short name T1298
Test name
Test status
Simulation time 47387347 ps
CPU time 1.59 seconds
Started Apr 18 02:27:17 PM PDT 24
Finished Apr 18 02:27:20 PM PDT 24
Peak memory 229764 kb
Host smart-0bc5643f-b5b5-444d-816c-aa6042ab6151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709389139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.1709389139
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1380091520
Short name T304
Test name
Test status
Simulation time 173997180 ps
CPU time 5.73 seconds
Started Apr 18 02:27:00 PM PDT 24
Finished Apr 18 02:27:07 PM PDT 24
Peak memory 239360 kb
Host smart-3d789316-c0d9-4b26-bb8c-6449f9ff7e2c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380091520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.1380091520
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.985365728
Short name T1247
Test name
Test status
Simulation time 1612177905 ps
CPU time 10.15 seconds
Started Apr 18 02:26:56 PM PDT 24
Finished Apr 18 02:27:08 PM PDT 24
Peak memory 238276 kb
Host smart-c5623507-a158-4433-a9e1-9c07e2e95768
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985365728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_b
ash.985365728
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.744646973
Short name T1240
Test name
Test status
Simulation time 118515194 ps
CPU time 2.45 seconds
Started Apr 18 02:26:53 PM PDT 24
Finished Apr 18 02:26:56 PM PDT 24
Peak memory 239460 kb
Host smart-dc566d75-ff36-4a82-8be2-77a3bb555932
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744646973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_re
set.744646973
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3344286392
Short name T1226
Test name
Test status
Simulation time 205908853 ps
CPU time 2.99 seconds
Started Apr 18 02:26:56 PM PDT 24
Finished Apr 18 02:27:00 PM PDT 24
Peak memory 247704 kb
Host smart-46574afc-b8c7-4064-b4ef-39ad6aad5e34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344286392 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.3344286392
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3672441232
Short name T295
Test name
Test status
Simulation time 609878448 ps
CPU time 2.48 seconds
Started Apr 18 02:26:54 PM PDT 24
Finished Apr 18 02:26:58 PM PDT 24
Peak memory 240700 kb
Host smart-cdd8fb50-7261-4ba4-8158-fc6aeeac4daf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672441232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.3672441232
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.3405066947
Short name T1239
Test name
Test status
Simulation time 139428862 ps
CPU time 1.57 seconds
Started Apr 18 02:26:58 PM PDT 24
Finished Apr 18 02:27:00 PM PDT 24
Peak memory 231160 kb
Host smart-fa669033-92da-41b8-8def-eef905e7d262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405066947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.3405066947
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.513144215
Short name T1279
Test name
Test status
Simulation time 532529488 ps
CPU time 1.95 seconds
Started Apr 18 02:26:55 PM PDT 24
Finished Apr 18 02:26:58 PM PDT 24
Peak memory 230916 kb
Host smart-5943323f-6ce4-4de1-a8b8-cf6ee5823962
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513144215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl
_mem_partial_access.513144215
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.1855704394
Short name T1206
Test name
Test status
Simulation time 47470810 ps
CPU time 1.37 seconds
Started Apr 18 02:27:00 PM PDT 24
Finished Apr 18 02:27:02 PM PDT 24
Peak memory 230904 kb
Host smart-305e286d-c7dd-49ab-8285-50d9fb4656f8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855704394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.1855704394
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2617049884
Short name T1323
Test name
Test status
Simulation time 72953166 ps
CPU time 2.48 seconds
Started Apr 18 02:26:57 PM PDT 24
Finished Apr 18 02:27:00 PM PDT 24
Peak memory 238052 kb
Host smart-7c280343-0868-4a2b-928e-2b1d4b9dc161
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617049884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.2617049884
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.36528430
Short name T1262
Test name
Test status
Simulation time 164363183 ps
CPU time 6.03 seconds
Started Apr 18 02:26:58 PM PDT 24
Finished Apr 18 02:27:04 PM PDT 24
Peak memory 246272 kb
Host smart-256933ae-471e-4649-a493-4dcb15a5a0a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36528430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.36528430
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.887872828
Short name T261
Test name
Test status
Simulation time 783079180 ps
CPU time 11.39 seconds
Started Apr 18 02:26:57 PM PDT 24
Finished Apr 18 02:27:09 PM PDT 24
Peak memory 244728 kb
Host smart-480220a8-33e7-4b65-a886-d2edf4f898f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887872828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_int
g_err.887872828
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.1314570395
Short name T1251
Test name
Test status
Simulation time 41526599 ps
CPU time 1.42 seconds
Started Apr 18 02:27:17 PM PDT 24
Finished Apr 18 02:27:20 PM PDT 24
Peak memory 229788 kb
Host smart-245f3c59-ae0c-4bb4-bda2-fa7e77d33ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314570395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.1314570395
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.2122820161
Short name T1200
Test name
Test status
Simulation time 39158323 ps
CPU time 1.45 seconds
Started Apr 18 02:27:14 PM PDT 24
Finished Apr 18 02:27:16 PM PDT 24
Peak memory 229792 kb
Host smart-dd46ed90-116b-4635-a3f4-c8135b81ce5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122820161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.2122820161
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1089504421
Short name T1225
Test name
Test status
Simulation time 117029112 ps
CPU time 1.52 seconds
Started Apr 18 02:27:21 PM PDT 24
Finished Apr 18 02:27:23 PM PDT 24
Peak memory 229772 kb
Host smart-4f391e8c-644c-4732-9c82-f5b896ce8e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089504421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.1089504421
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.2009737932
Short name T1211
Test name
Test status
Simulation time 74820743 ps
CPU time 1.5 seconds
Started Apr 18 02:27:17 PM PDT 24
Finished Apr 18 02:27:19 PM PDT 24
Peak memory 231152 kb
Host smart-fbc6eeb7-9c3d-4f5d-a227-50f4a72c5ca1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009737932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.2009737932
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3673585316
Short name T1296
Test name
Test status
Simulation time 41835543 ps
CPU time 1.51 seconds
Started Apr 18 02:27:22 PM PDT 24
Finished Apr 18 02:27:25 PM PDT 24
Peak memory 231112 kb
Host smart-ab4f98e8-a3fd-4243-b647-cfc9281e8dc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673585316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.3673585316
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.3505721120
Short name T1325
Test name
Test status
Simulation time 553297170 ps
CPU time 1.75 seconds
Started Apr 18 02:27:14 PM PDT 24
Finished Apr 18 02:27:16 PM PDT 24
Peak memory 231064 kb
Host smart-45a22d0b-f5bb-4930-b65d-3d4c43b56e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505721120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.3505721120
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2754908631
Short name T1301
Test name
Test status
Simulation time 40265559 ps
CPU time 1.46 seconds
Started Apr 18 02:27:19 PM PDT 24
Finished Apr 18 02:27:21 PM PDT 24
Peak memory 229784 kb
Host smart-e09910ac-05a0-4a1e-a6b8-c165f76305c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754908631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.2754908631
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.145529578
Short name T1276
Test name
Test status
Simulation time 553362533 ps
CPU time 1.93 seconds
Started Apr 18 02:27:17 PM PDT 24
Finished Apr 18 02:27:20 PM PDT 24
Peak memory 229796 kb
Host smart-09646e53-62bb-43cb-a9e9-e69a85abbd35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145529578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.145529578
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2191475581
Short name T1219
Test name
Test status
Simulation time 144541847 ps
CPU time 1.48 seconds
Started Apr 18 02:27:16 PM PDT 24
Finished Apr 18 02:27:18 PM PDT 24
Peak memory 229800 kb
Host smart-790c8dee-d4bd-4acc-aa26-f7072ea46f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191475581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.2191475581
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.1771140254
Short name T1222
Test name
Test status
Simulation time 41221186 ps
CPU time 1.44 seconds
Started Apr 18 02:27:18 PM PDT 24
Finished Apr 18 02:27:20 PM PDT 24
Peak memory 231224 kb
Host smart-89587f0e-3668-4f48-82e1-c761f6fdb197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771140254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.1771140254
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.1960665254
Short name T1263
Test name
Test status
Simulation time 1703715541 ps
CPU time 4.98 seconds
Started Apr 18 02:27:01 PM PDT 24
Finished Apr 18 02:27:06 PM PDT 24
Peak memory 247640 kb
Host smart-64c395a2-0489-4f6c-a030-0840bea1118b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960665254 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.1960665254
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3347869909
Short name T315
Test name
Test status
Simulation time 46142763 ps
CPU time 1.58 seconds
Started Apr 18 02:26:56 PM PDT 24
Finished Apr 18 02:26:59 PM PDT 24
Peak memory 240508 kb
Host smart-d6458ea2-ceb0-406f-a39a-f57aec8a6363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347869909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.3347869909
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.2335330975
Short name T1307
Test name
Test status
Simulation time 531421296 ps
CPU time 1.41 seconds
Started Apr 18 02:26:55 PM PDT 24
Finished Apr 18 02:26:57 PM PDT 24
Peak memory 231204 kb
Host smart-c9711b11-29c7-4341-99de-fdd7f2e6a7dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335330975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.2335330975
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3178514769
Short name T1288
Test name
Test status
Simulation time 108568167 ps
CPU time 2.24 seconds
Started Apr 18 02:26:54 PM PDT 24
Finished Apr 18 02:26:57 PM PDT 24
Peak memory 239428 kb
Host smart-5c3a2562-190e-4a94-ac51-b01bd214ee8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178514769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.3178514769
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3329836768
Short name T1260
Test name
Test status
Simulation time 1564116749 ps
CPU time 4.33 seconds
Started Apr 18 02:26:55 PM PDT 24
Finished Apr 18 02:27:00 PM PDT 24
Peak memory 246856 kb
Host smart-fc2169cd-ba87-4e0b-8cb8-dbc00b982a6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329836768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.3329836768
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.4098567701
Short name T349
Test name
Test status
Simulation time 3531167318 ps
CPU time 16.99 seconds
Started Apr 18 02:27:01 PM PDT 24
Finished Apr 18 02:27:18 PM PDT 24
Peak memory 245664 kb
Host smart-76c8b654-8dd0-41d7-bd60-5654520998d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098567701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.4098567701
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2537931448
Short name T1258
Test name
Test status
Simulation time 142861934 ps
CPU time 2.43 seconds
Started Apr 18 02:26:59 PM PDT 24
Finished Apr 18 02:27:03 PM PDT 24
Peak memory 246460 kb
Host smart-159803aa-88ad-4ce5-a9a8-e3be84f125cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537931448 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.2537931448
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2938986500
Short name T265
Test name
Test status
Simulation time 42150808 ps
CPU time 1.56 seconds
Started Apr 18 02:26:58 PM PDT 24
Finished Apr 18 02:27:00 PM PDT 24
Peak memory 241504 kb
Host smart-25988aa9-73cc-4316-9550-fde03254e7c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938986500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2938986500
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.819840233
Short name T1309
Test name
Test status
Simulation time 74209219 ps
CPU time 1.47 seconds
Started Apr 18 02:27:03 PM PDT 24
Finished Apr 18 02:27:06 PM PDT 24
Peak memory 229948 kb
Host smart-3edd739f-5fe6-41c2-8a54-05f49faddb33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819840233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.819840233
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3294219992
Short name T310
Test name
Test status
Simulation time 79601453 ps
CPU time 2.43 seconds
Started Apr 18 02:27:00 PM PDT 24
Finished Apr 18 02:27:03 PM PDT 24
Peak memory 239456 kb
Host smart-c91d4293-4321-4459-b5a9-eacfde89a0ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294219992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.3294219992
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1498587156
Short name T1216
Test name
Test status
Simulation time 645665326 ps
CPU time 7.36 seconds
Started Apr 18 02:27:00 PM PDT 24
Finished Apr 18 02:27:08 PM PDT 24
Peak memory 246480 kb
Host smart-1fc1a3c4-2e7f-452a-bfd9-e36dc3adeaeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498587156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.1498587156
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2167142902
Short name T338
Test name
Test status
Simulation time 1302853926 ps
CPU time 10.97 seconds
Started Apr 18 02:26:59 PM PDT 24
Finished Apr 18 02:27:11 PM PDT 24
Peak memory 243756 kb
Host smart-382916d1-8a2a-4697-a67b-3df2006d51ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167142902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.2167142902
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3681022328
Short name T1252
Test name
Test status
Simulation time 255563970 ps
CPU time 2.57 seconds
Started Apr 18 02:27:00 PM PDT 24
Finished Apr 18 02:27:03 PM PDT 24
Peak memory 247628 kb
Host smart-dec9f2b8-7547-4111-94e0-431b83b857af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681022328 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.3681022328
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.1069890466
Short name T1234
Test name
Test status
Simulation time 144408409 ps
CPU time 1.58 seconds
Started Apr 18 02:27:08 PM PDT 24
Finished Apr 18 02:27:11 PM PDT 24
Peak memory 240208 kb
Host smart-34918d2b-94bb-47e0-8f53-98a6edc4d497
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069890466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.1069890466
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3711119917
Short name T1229
Test name
Test status
Simulation time 145333306 ps
CPU time 1.43 seconds
Started Apr 18 02:27:01 PM PDT 24
Finished Apr 18 02:27:03 PM PDT 24
Peak memory 230068 kb
Host smart-d79ca602-2646-4d8b-be3c-326aaa5284a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711119917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3711119917
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.2373227689
Short name T1287
Test name
Test status
Simulation time 85395300 ps
CPU time 2.82 seconds
Started Apr 18 02:27:00 PM PDT 24
Finished Apr 18 02:27:03 PM PDT 24
Peak memory 237968 kb
Host smart-9838e649-dfad-4c4f-8042-4102904004ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373227689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.2373227689
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.4234936372
Short name T1238
Test name
Test status
Simulation time 60238233 ps
CPU time 3.43 seconds
Started Apr 18 02:27:00 PM PDT 24
Finished Apr 18 02:27:04 PM PDT 24
Peak memory 239552 kb
Host smart-af1db8e8-6af9-466b-b19b-a9a6fcd04c01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234936372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.4234936372
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3587678203
Short name T348
Test name
Test status
Simulation time 691945230 ps
CPU time 10.07 seconds
Started Apr 18 02:26:59 PM PDT 24
Finished Apr 18 02:27:10 PM PDT 24
Peak memory 244304 kb
Host smart-1f305252-1da0-4149-9a61-4fac6c3bb020
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587678203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.3587678203
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3093933979
Short name T1245
Test name
Test status
Simulation time 259485984 ps
CPU time 2.96 seconds
Started Apr 18 02:26:57 PM PDT 24
Finished Apr 18 02:27:01 PM PDT 24
Peak memory 246844 kb
Host smart-8b9dc8a2-1280-4d27-b3d2-df3d61697b54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093933979 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.3093933979
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1416653335
Short name T1310
Test name
Test status
Simulation time 77268926 ps
CPU time 1.59 seconds
Started Apr 18 02:27:01 PM PDT 24
Finished Apr 18 02:27:03 PM PDT 24
Peak memory 240476 kb
Host smart-078a13b9-0b5a-4883-98a3-61ab03453cd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416653335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.1416653335
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.1070815706
Short name T1221
Test name
Test status
Simulation time 127417433 ps
CPU time 1.47 seconds
Started Apr 18 02:27:04 PM PDT 24
Finished Apr 18 02:27:06 PM PDT 24
Peak memory 231216 kb
Host smart-09adba11-99a8-4040-b4e9-fe0eaa68c52b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070815706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.1070815706
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.866353431
Short name T1224
Test name
Test status
Simulation time 87969749 ps
CPU time 1.99 seconds
Started Apr 18 02:27:08 PM PDT 24
Finished Apr 18 02:27:11 PM PDT 24
Peak memory 239368 kb
Host smart-fb862803-7c2e-459a-a47f-5a80d0ee1834
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866353431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ct
rl_same_csr_outstanding.866353431
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.746018392
Short name T1269
Test name
Test status
Simulation time 104553012 ps
CPU time 3.24 seconds
Started Apr 18 02:27:01 PM PDT 24
Finished Apr 18 02:27:05 PM PDT 24
Peak memory 246972 kb
Host smart-7a222fc6-e2a1-48aa-b4c5-946a50fd2448
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746018392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.746018392
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2738872675
Short name T337
Test name
Test status
Simulation time 9798326069 ps
CPU time 22.04 seconds
Started Apr 18 02:27:08 PM PDT 24
Finished Apr 18 02:27:31 PM PDT 24
Peak memory 239496 kb
Host smart-840254fb-2c1f-456c-9105-2c19199c1b23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738872675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.2738872675
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.4009040956
Short name T367
Test name
Test status
Simulation time 103148566 ps
CPU time 3.64 seconds
Started Apr 18 02:27:04 PM PDT 24
Finished Apr 18 02:27:08 PM PDT 24
Peak memory 247684 kb
Host smart-7d0561d3-fa09-48fb-b6c6-785290fb6998
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009040956 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.4009040956
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2854273797
Short name T297
Test name
Test status
Simulation time 40379337 ps
CPU time 1.58 seconds
Started Apr 18 02:27:07 PM PDT 24
Finished Apr 18 02:27:09 PM PDT 24
Peak memory 241436 kb
Host smart-0d8dee18-7c09-407c-8bf8-2ff3155645a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854273797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.2854273797
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.897465642
Short name T1246
Test name
Test status
Simulation time 40057388 ps
CPU time 1.47 seconds
Started Apr 18 02:27:00 PM PDT 24
Finished Apr 18 02:27:02 PM PDT 24
Peak memory 231052 kb
Host smart-efe740d9-0859-4359-a4e7-f63330a73cd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897465642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.897465642
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1512061764
Short name T1266
Test name
Test status
Simulation time 104233825 ps
CPU time 2.52 seconds
Started Apr 18 02:27:02 PM PDT 24
Finished Apr 18 02:27:05 PM PDT 24
Peak memory 239408 kb
Host smart-3ae31726-2122-454a-811c-6b564786aa6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512061764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.1512061764
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.479926787
Short name T1230
Test name
Test status
Simulation time 54247535 ps
CPU time 2.85 seconds
Started Apr 18 02:27:00 PM PDT 24
Finished Apr 18 02:27:04 PM PDT 24
Peak memory 239380 kb
Host smart-3ef22aa8-a108-4290-89e1-85f4bc635883
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479926787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.479926787
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.3441956175
Short name T186
Test name
Test status
Simulation time 278780749 ps
CPU time 3.7 seconds
Started Apr 18 03:36:12 PM PDT 24
Finished Apr 18 03:36:16 PM PDT 24
Peak memory 240448 kb
Host smart-0a7ef698-6b46-433c-b109-6f7bcd4909e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441956175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.3441956175
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.3372113959
Short name T620
Test name
Test status
Simulation time 5538577630 ps
CPU time 47.03 seconds
Started Apr 18 03:35:47 PM PDT 24
Finished Apr 18 03:36:35 PM PDT 24
Peak memory 242284 kb
Host smart-11665105-40b9-4182-a568-a6e9d0f970d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372113959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.3372113959
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.4255440693
Short name T767
Test name
Test status
Simulation time 3200284284 ps
CPU time 37.87 seconds
Started Apr 18 03:35:57 PM PDT 24
Finished Apr 18 03:36:35 PM PDT 24
Peak memory 247100 kb
Host smart-1455cff5-45e6-421f-b614-0bc240a2edf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255440693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.4255440693
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.2258596906
Short name T895
Test name
Test status
Simulation time 2148272814 ps
CPU time 15.44 seconds
Started Apr 18 03:35:57 PM PDT 24
Finished Apr 18 03:36:13 PM PDT 24
Peak memory 242712 kb
Host smart-45c0783c-4ee6-4b25-9bba-1ef47506b4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258596906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.2258596906
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.261751835
Short name T1193
Test name
Test status
Simulation time 252040440 ps
CPU time 3.93 seconds
Started Apr 18 03:35:51 PM PDT 24
Finished Apr 18 03:35:56 PM PDT 24
Peak memory 241768 kb
Host smart-01e57a5b-83fb-40f5-b76b-559c94d6138f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261751835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.261751835
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.2926080386
Short name T929
Test name
Test status
Simulation time 3021236672 ps
CPU time 13.58 seconds
Started Apr 18 03:35:50 PM PDT 24
Finished Apr 18 03:36:04 PM PDT 24
Peak memory 241436 kb
Host smart-3548692d-7cd5-4e56-9060-34d6240e833b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926080386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.2926080386
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.2298802859
Short name T719
Test name
Test status
Simulation time 2145519288 ps
CPU time 15.9 seconds
Started Apr 18 03:36:08 PM PDT 24
Finished Apr 18 03:36:24 PM PDT 24
Peak memory 243840 kb
Host smart-ceed4319-4c93-4bad-b6a3-101cf3fe62ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298802859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.2298802859
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.4047820764
Short name T936
Test name
Test status
Simulation time 403507077 ps
CPU time 6.88 seconds
Started Apr 18 03:36:09 PM PDT 24
Finished Apr 18 03:36:16 PM PDT 24
Peak memory 241776 kb
Host smart-87d5c644-9076-425c-9ed2-8f6844fcbb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047820764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.4047820764
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.773634132
Short name T611
Test name
Test status
Simulation time 236622406 ps
CPU time 13.99 seconds
Started Apr 18 03:35:53 PM PDT 24
Finished Apr 18 03:36:08 PM PDT 24
Peak memory 241684 kb
Host smart-0e8395fa-91bc-463f-8213-04cb97896641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773634132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.773634132
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.337935668
Short name T957
Test name
Test status
Simulation time 2215964751 ps
CPU time 20.69 seconds
Started Apr 18 03:35:54 PM PDT 24
Finished Apr 18 03:36:15 PM PDT 24
Peak memory 241816 kb
Host smart-89537f52-a437-4eb2-bc5c-ea87a63aaea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337935668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.337935668
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.457643756
Short name T477
Test name
Test status
Simulation time 2380812562 ps
CPU time 21.09 seconds
Started Apr 18 03:35:51 PM PDT 24
Finished Apr 18 03:36:12 PM PDT 24
Peak memory 241436 kb
Host smart-442cc8d2-bb22-41a1-9164-47970152a4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457643756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.457643756
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.569422361
Short name T1102
Test name
Test status
Simulation time 388601495 ps
CPU time 6.38 seconds
Started Apr 18 03:36:10 PM PDT 24
Finished Apr 18 03:36:17 PM PDT 24
Peak memory 242252 kb
Host smart-1b213e06-9689-4853-a7c0-f90066f84293
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=569422361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.569422361
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.353917868
Short name T24
Test name
Test status
Simulation time 21018311953 ps
CPU time 195.76 seconds
Started Apr 18 03:36:14 PM PDT 24
Finished Apr 18 03:39:30 PM PDT 24
Peak memory 271984 kb
Host smart-436454a6-ec6d-4da2-8302-20dc79bb4aa0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353917868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.353917868
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.591571395
Short name T950
Test name
Test status
Simulation time 375926229 ps
CPU time 9.84 seconds
Started Apr 18 03:35:48 PM PDT 24
Finished Apr 18 03:35:58 PM PDT 24
Peak memory 241848 kb
Host smart-7a6f4f85-c8b2-4ed7-b4ef-62471569405b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591571395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.591571395
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.898102204
Short name T953
Test name
Test status
Simulation time 69409913682 ps
CPU time 110.89 seconds
Started Apr 18 03:36:15 PM PDT 24
Finished Apr 18 03:38:06 PM PDT 24
Peak memory 266300 kb
Host smart-62dbf377-9389-4a7d-9edb-ef924607c7a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898102204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.898102204
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.421770417
Short name T888
Test name
Test status
Simulation time 907592284858 ps
CPU time 2203.23 seconds
Started Apr 18 03:36:16 PM PDT 24
Finished Apr 18 04:13:00 PM PDT 24
Peak memory 560220 kb
Host smart-e1bb57ba-4e6c-48dc-8b16-6cdee710773e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421770417 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.421770417
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.820741810
Short name T378
Test name
Test status
Simulation time 2215763903 ps
CPU time 21.81 seconds
Started Apr 18 03:36:10 PM PDT 24
Finished Apr 18 03:36:32 PM PDT 24
Peak memory 242324 kb
Host smart-e70dfd60-1298-4fa5-a76d-cb40f63846ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820741810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.820741810
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.1818130784
Short name T426
Test name
Test status
Simulation time 104445954 ps
CPU time 1.74 seconds
Started Apr 18 03:35:42 PM PDT 24
Finished Apr 18 03:35:44 PM PDT 24
Peak memory 240316 kb
Host smart-9a693ec6-664d-4a34-aed5-ed6067c4970c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1818130784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.1818130784
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.1995283369
Short name T621
Test name
Test status
Simulation time 74851562 ps
CPU time 1.85 seconds
Started Apr 18 03:36:38 PM PDT 24
Finished Apr 18 03:36:41 PM PDT 24
Peak memory 240140 kb
Host smart-f785a055-aa48-4e2c-8e66-4fd88f424772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995283369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.1995283369
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.494636770
Short name T1178
Test name
Test status
Simulation time 966064414 ps
CPU time 33.61 seconds
Started Apr 18 03:36:18 PM PDT 24
Finished Apr 18 03:36:53 PM PDT 24
Peak memory 241840 kb
Host smart-dc7824d9-66fc-4536-b785-ae242badac42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494636770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.494636770
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.1847211575
Short name T75
Test name
Test status
Simulation time 448557634 ps
CPU time 14.99 seconds
Started Apr 18 03:36:24 PM PDT 24
Finished Apr 18 03:36:39 PM PDT 24
Peak memory 242272 kb
Host smart-3bfc903f-71bb-4838-92f0-76e0edc93846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847211575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1847211575
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.1253679633
Short name T994
Test name
Test status
Simulation time 1718528540 ps
CPU time 28.29 seconds
Started Apr 18 03:36:23 PM PDT 24
Finished Apr 18 03:36:52 PM PDT 24
Peak memory 242120 kb
Host smart-e023be53-6f57-4198-942a-dfe51cc37c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253679633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.1253679633
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.2025853556
Short name T927
Test name
Test status
Simulation time 453557503 ps
CPU time 6.91 seconds
Started Apr 18 03:36:18 PM PDT 24
Finished Apr 18 03:36:25 PM PDT 24
Peak memory 248660 kb
Host smart-959d3d9f-beaf-4763-97ed-b5903bcbc8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025853556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.2025853556
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.3621974936
Short name T551
Test name
Test status
Simulation time 2968714804 ps
CPU time 7.58 seconds
Started Apr 18 03:36:23 PM PDT 24
Finished Apr 18 03:36:31 PM PDT 24
Peak memory 241912 kb
Host smart-e60dc139-ded0-4025-8750-d9e316955500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621974936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.3621974936
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.2048512266
Short name T1051
Test name
Test status
Simulation time 18274286370 ps
CPU time 51.2 seconds
Started Apr 18 03:36:29 PM PDT 24
Finished Apr 18 03:37:21 PM PDT 24
Peak memory 243252 kb
Host smart-8181329a-39a1-46b1-9f4f-e79bda359e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048512266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.2048512266
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.915761775
Short name T173
Test name
Test status
Simulation time 521445662 ps
CPU time 13.73 seconds
Started Apr 18 03:36:18 PM PDT 24
Finished Apr 18 03:36:33 PM PDT 24
Peak memory 241728 kb
Host smart-2e4bbe09-0f4e-46ad-9472-016a6079dfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915761775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.915761775
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.3414649286
Short name T538
Test name
Test status
Simulation time 807653319 ps
CPU time 21.01 seconds
Started Apr 18 03:36:17 PM PDT 24
Finished Apr 18 03:36:39 PM PDT 24
Peak memory 241724 kb
Host smart-f6158b09-2caf-487b-a867-2aee0adf1c4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3414649286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.3414649286
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.823241732
Short name T351
Test name
Test status
Simulation time 4428848039 ps
CPU time 14.36 seconds
Started Apr 18 03:36:32 PM PDT 24
Finished Apr 18 03:36:47 PM PDT 24
Peak memory 242296 kb
Host smart-c2d4eda3-3fed-437a-9ee1-c14c67baac04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=823241732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.823241732
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.4255093882
Short name T588
Test name
Test status
Simulation time 196431198 ps
CPU time 4.49 seconds
Started Apr 18 03:36:17 PM PDT 24
Finished Apr 18 03:36:22 PM PDT 24
Peak memory 241828 kb
Host smart-cf18b183-2e7b-4e46-8ef9-bf511778fc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255093882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.4255093882
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.763597872
Short name T1170
Test name
Test status
Simulation time 21176602002 ps
CPU time 142.62 seconds
Started Apr 18 03:36:35 PM PDT 24
Finished Apr 18 03:38:58 PM PDT 24
Peak memory 255272 kb
Host smart-0b398617-4213-49a2-960a-2aedd18d7aa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763597872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.763597872
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.2081494986
Short name T790
Test name
Test status
Simulation time 579031868263 ps
CPU time 1002.74 seconds
Started Apr 18 03:36:33 PM PDT 24
Finished Apr 18 03:53:16 PM PDT 24
Peak memory 289872 kb
Host smart-87d4d02a-376c-48bd-abb7-70dd446cb562
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081494986 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.2081494986
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.3188566927
Short name T4
Test name
Test status
Simulation time 2550634127 ps
CPU time 5.74 seconds
Started Apr 18 03:36:29 PM PDT 24
Finished Apr 18 03:36:35 PM PDT 24
Peak memory 242200 kb
Host smart-874d6828-e776-4a48-88f1-45d0e588af47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188566927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.3188566927
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.3424279836
Short name T677
Test name
Test status
Simulation time 770314706 ps
CPU time 2.77 seconds
Started Apr 18 03:38:54 PM PDT 24
Finished Apr 18 03:38:57 PM PDT 24
Peak memory 240052 kb
Host smart-a1426b22-9897-44a4-a9bd-a85125ef73db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424279836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.3424279836
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.2246401945
Short name T394
Test name
Test status
Simulation time 1316563980 ps
CPU time 18.5 seconds
Started Apr 18 03:38:41 PM PDT 24
Finished Apr 18 03:39:00 PM PDT 24
Peak memory 241800 kb
Host smart-9fc24e1c-ef97-4c4c-9fe8-56763943575a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246401945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.2246401945
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.13033157
Short name T440
Test name
Test status
Simulation time 1413420417 ps
CPU time 21.78 seconds
Started Apr 18 03:38:41 PM PDT 24
Finished Apr 18 03:39:03 PM PDT 24
Peak memory 241816 kb
Host smart-9a30cf57-f92d-4e38-95ce-5af0c8f5dc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13033157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.13033157
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.2677915309
Short name T731
Test name
Test status
Simulation time 284162160 ps
CPU time 3.28 seconds
Started Apr 18 03:38:42 PM PDT 24
Finished Apr 18 03:38:46 PM PDT 24
Peak memory 241908 kb
Host smart-536e3fc6-1a7b-4098-89f5-36b59f039a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677915309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.2677915309
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.4245136801
Short name T766
Test name
Test status
Simulation time 1468148252 ps
CPU time 23.36 seconds
Started Apr 18 03:38:45 PM PDT 24
Finished Apr 18 03:39:09 PM PDT 24
Peak memory 243892 kb
Host smart-1c44548f-8928-4151-9942-40c40cf67df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245136801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.4245136801
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.1449018400
Short name T212
Test name
Test status
Simulation time 1370091093 ps
CPU time 23.07 seconds
Started Apr 18 03:38:46 PM PDT 24
Finished Apr 18 03:39:09 PM PDT 24
Peak memory 242328 kb
Host smart-00e37a99-2ebb-4012-ba80-c79edca758cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449018400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.1449018400
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.1325456864
Short name T385
Test name
Test status
Simulation time 751292927 ps
CPU time 11.37 seconds
Started Apr 18 03:38:41 PM PDT 24
Finished Apr 18 03:38:53 PM PDT 24
Peak memory 241760 kb
Host smart-a44f6ad8-b354-4b41-8957-ada9682181e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325456864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.1325456864
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.2187004279
Short name T824
Test name
Test status
Simulation time 1286517367 ps
CPU time 13.66 seconds
Started Apr 18 03:38:40 PM PDT 24
Finished Apr 18 03:38:54 PM PDT 24
Peak memory 241920 kb
Host smart-bdbcabc1-f37b-4451-99e1-9ac960b16ea4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2187004279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.2187004279
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.2828887989
Short name T1000
Test name
Test status
Simulation time 569064501 ps
CPU time 5.63 seconds
Started Apr 18 03:38:42 PM PDT 24
Finished Apr 18 03:38:48 PM PDT 24
Peak memory 241784 kb
Host smart-f730b204-bcc3-499d-933e-bb993aaa9a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828887989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.2828887989
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.3709234863
Short name T125
Test name
Test status
Simulation time 15955114201 ps
CPU time 140.55 seconds
Started Apr 18 03:38:55 PM PDT 24
Finished Apr 18 03:41:16 PM PDT 24
Peak memory 257112 kb
Host smart-51c77e45-d478-4801-bce2-9293a83cb8c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709234863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.3709234863
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.360524619
Short name T286
Test name
Test status
Simulation time 906903732177 ps
CPU time 1637.6 seconds
Started Apr 18 03:38:53 PM PDT 24
Finished Apr 18 04:06:12 PM PDT 24
Peak memory 347284 kb
Host smart-b421e16d-9b52-428c-ac6f-345334ff3237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360524619 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.360524619
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.1455236875
Short name T712
Test name
Test status
Simulation time 818655394 ps
CPU time 11.86 seconds
Started Apr 18 03:38:45 PM PDT 24
Finished Apr 18 03:38:57 PM PDT 24
Peak memory 241832 kb
Host smart-7cfd4758-a5c1-4841-ad0c-6af708f8ca2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455236875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.1455236875
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.217341645
Short name T900
Test name
Test status
Simulation time 138485652 ps
CPU time 3.34 seconds
Started Apr 18 03:45:03 PM PDT 24
Finished Apr 18 03:45:06 PM PDT 24
Peak memory 241916 kb
Host smart-9f0f14c7-aeb1-40ef-aa4d-e081fff3dc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217341645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.217341645
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.3495585050
Short name T273
Test name
Test status
Simulation time 481668362 ps
CPU time 13.07 seconds
Started Apr 18 03:45:04 PM PDT 24
Finished Apr 18 03:45:18 PM PDT 24
Peak memory 241824 kb
Host smart-2dde5c44-69a4-411e-8e30-ec16222f8eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495585050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.3495585050
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.2835065077
Short name T921
Test name
Test status
Simulation time 2125159756 ps
CPU time 6.33 seconds
Started Apr 18 03:45:01 PM PDT 24
Finished Apr 18 03:45:08 PM PDT 24
Peak memory 242160 kb
Host smart-1b1b6a2a-9e72-44ca-9bb4-ac96330f7cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835065077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.2835065077
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.2309049389
Short name T1181
Test name
Test status
Simulation time 206725387 ps
CPU time 11.67 seconds
Started Apr 18 03:45:03 PM PDT 24
Finished Apr 18 03:45:15 PM PDT 24
Peak memory 242088 kb
Host smart-e4b4f18f-9312-4de7-a272-c80506a1e945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309049389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.2309049389
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.3064731832
Short name T97
Test name
Test status
Simulation time 1486972469 ps
CPU time 4.82 seconds
Started Apr 18 03:45:01 PM PDT 24
Finished Apr 18 03:45:06 PM PDT 24
Peak memory 241772 kb
Host smart-46b97a66-8c74-42bc-a696-f85365859890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064731832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.3064731832
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.4280473656
Short name T560
Test name
Test status
Simulation time 451247421 ps
CPU time 13.62 seconds
Started Apr 18 03:45:02 PM PDT 24
Finished Apr 18 03:45:16 PM PDT 24
Peak memory 241920 kb
Host smart-ff55e98f-343b-4b2c-8845-09dce49cbad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280473656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.4280473656
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.186240113
Short name T1176
Test name
Test status
Simulation time 2305055936 ps
CPU time 6.15 seconds
Started Apr 18 03:45:08 PM PDT 24
Finished Apr 18 03:45:14 PM PDT 24
Peak memory 241996 kb
Host smart-95440f3a-12b4-4adb-9034-33d509ebd987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186240113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.186240113
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.2373410489
Short name T1134
Test name
Test status
Simulation time 546955137 ps
CPU time 4.28 seconds
Started Apr 18 03:45:08 PM PDT 24
Finished Apr 18 03:45:13 PM PDT 24
Peak memory 242184 kb
Host smart-5fb4f1bf-ddda-4cd0-9bb9-784db2af8b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373410489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.2373410489
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.1667797172
Short name T189
Test name
Test status
Simulation time 255752407 ps
CPU time 3.69 seconds
Started Apr 18 03:45:06 PM PDT 24
Finished Apr 18 03:45:10 PM PDT 24
Peak memory 241880 kb
Host smart-191dad4c-330d-4725-a0c9-7a00c29844bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667797172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1667797172
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.3443284601
Short name T319
Test name
Test status
Simulation time 854688276 ps
CPU time 8.12 seconds
Started Apr 18 03:45:07 PM PDT 24
Finished Apr 18 03:45:16 PM PDT 24
Peak memory 241900 kb
Host smart-582c79ce-658d-43b4-bdb9-a005c246f5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443284601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3443284601
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.1492704098
Short name T773
Test name
Test status
Simulation time 188052601 ps
CPU time 4.71 seconds
Started Apr 18 03:45:05 PM PDT 24
Finished Apr 18 03:45:11 PM PDT 24
Peak memory 241928 kb
Host smart-2d519f70-bde1-4526-a229-56903244ed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492704098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1492704098
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.1286154601
Short name T453
Test name
Test status
Simulation time 255379057 ps
CPU time 6.17 seconds
Started Apr 18 03:45:05 PM PDT 24
Finished Apr 18 03:45:12 PM PDT 24
Peak memory 241880 kb
Host smart-48114e0e-fb29-4795-aa8a-f7d2c58e6ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286154601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.1286154601
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.3984438007
Short name T745
Test name
Test status
Simulation time 628693328 ps
CPU time 4.88 seconds
Started Apr 18 03:45:05 PM PDT 24
Finished Apr 18 03:45:11 PM PDT 24
Peak memory 241576 kb
Host smart-75b709f8-e5cd-4371-a57f-2dce7040e717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984438007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.3984438007
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.715064121
Short name T665
Test name
Test status
Simulation time 249337659 ps
CPU time 3.38 seconds
Started Apr 18 03:45:13 PM PDT 24
Finished Apr 18 03:45:17 PM PDT 24
Peak memory 242140 kb
Host smart-7fa6d6c5-5b6d-4e06-a84a-1e2f2033a55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715064121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.715064121
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.3931597621
Short name T841
Test name
Test status
Simulation time 1335153676 ps
CPU time 19.28 seconds
Started Apr 18 03:45:11 PM PDT 24
Finished Apr 18 03:45:31 PM PDT 24
Peak memory 241776 kb
Host smart-3d76ad7b-4af7-409f-94eb-f9f51423804c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931597621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3931597621
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.3984070754
Short name T53
Test name
Test status
Simulation time 167970702 ps
CPU time 4.93 seconds
Started Apr 18 03:45:11 PM PDT 24
Finished Apr 18 03:45:17 PM PDT 24
Peak memory 242160 kb
Host smart-75eb0552-5f02-4be6-b50b-df9678187cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984070754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.3984070754
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.318007200
Short name T688
Test name
Test status
Simulation time 47080437 ps
CPU time 1.72 seconds
Started Apr 18 03:38:55 PM PDT 24
Finished Apr 18 03:38:58 PM PDT 24
Peak memory 240204 kb
Host smart-1022c541-4f18-4ad1-9f4d-16adc427228b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318007200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.318007200
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.2228866535
Short name T1027
Test name
Test status
Simulation time 204240611 ps
CPU time 4.96 seconds
Started Apr 18 03:38:56 PM PDT 24
Finished Apr 18 03:39:02 PM PDT 24
Peak memory 242152 kb
Host smart-51d62c91-5fa8-4c2e-ad35-28de1a9dff32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228866535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2228866535
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.2211697588
Short name T629
Test name
Test status
Simulation time 1507998960 ps
CPU time 24.95 seconds
Started Apr 18 03:38:57 PM PDT 24
Finished Apr 18 03:39:22 PM PDT 24
Peak memory 241756 kb
Host smart-a5712f6e-df7d-4067-8503-cd6d9edb37c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211697588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.2211697588
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.4072733756
Short name T673
Test name
Test status
Simulation time 456568422 ps
CPU time 10.01 seconds
Started Apr 18 03:38:51 PM PDT 24
Finished Apr 18 03:39:02 PM PDT 24
Peak memory 242184 kb
Host smart-22a89996-a371-4f25-8d33-588281c453f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072733756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.4072733756
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.3640540891
Short name T722
Test name
Test status
Simulation time 151634956 ps
CPU time 4.13 seconds
Started Apr 18 03:38:51 PM PDT 24
Finished Apr 18 03:38:56 PM PDT 24
Peak memory 241864 kb
Host smart-921179ff-70b4-4a4d-a722-3fce2809b58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640540891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.3640540891
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.3491784672
Short name T1052
Test name
Test status
Simulation time 2219523556 ps
CPU time 25.76 seconds
Started Apr 18 03:38:59 PM PDT 24
Finished Apr 18 03:39:25 PM PDT 24
Peak memory 248740 kb
Host smart-1ecbff4e-1c87-4831-8cf4-5438e6037885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491784672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.3491784672
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.4072847254
Short name T914
Test name
Test status
Simulation time 1381017542 ps
CPU time 12.65 seconds
Started Apr 18 03:38:57 PM PDT 24
Finished Apr 18 03:39:10 PM PDT 24
Peak memory 241928 kb
Host smart-909a738f-7a3b-4079-b591-37a1dcf4fe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072847254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.4072847254
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.91599951
Short name T1075
Test name
Test status
Simulation time 1382538103 ps
CPU time 10.95 seconds
Started Apr 18 03:38:51 PM PDT 24
Finished Apr 18 03:39:03 PM PDT 24
Peak memory 241680 kb
Host smart-6a83a712-ae94-461e-b6f7-1ff455118d91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91599951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.91599951
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.1225795596
Short name T716
Test name
Test status
Simulation time 124696847 ps
CPU time 4.36 seconds
Started Apr 18 03:38:58 PM PDT 24
Finished Apr 18 03:39:03 PM PDT 24
Peak memory 241816 kb
Host smart-d31464b3-18fc-43a7-aa75-e9cf38e1f187
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225795596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.1225795596
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.1002235732
Short name T1015
Test name
Test status
Simulation time 567553793 ps
CPU time 12.53 seconds
Started Apr 18 03:38:54 PM PDT 24
Finished Apr 18 03:39:07 PM PDT 24
Peak memory 241852 kb
Host smart-8a051f65-2f8d-49bc-8fb1-fef492da57b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002235732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.1002235732
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.323051520
Short name T510
Test name
Test status
Simulation time 2707368626 ps
CPU time 40.8 seconds
Started Apr 18 03:38:57 PM PDT 24
Finished Apr 18 03:39:39 PM PDT 24
Peak memory 246472 kb
Host smart-d4e535ab-90bf-4bd3-af60-bb475f8297d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323051520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.
323051520
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.3434543336
Short name T425
Test name
Test status
Simulation time 678163338 ps
CPU time 18.89 seconds
Started Apr 18 03:38:56 PM PDT 24
Finished Apr 18 03:39:16 PM PDT 24
Peak memory 241876 kb
Host smart-82c6a369-ed16-471d-8da0-ace7298ca675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434543336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.3434543336
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.3542730221
Short name T331
Test name
Test status
Simulation time 5506811549 ps
CPU time 14.1 seconds
Started Apr 18 03:45:12 PM PDT 24
Finished Apr 18 03:45:27 PM PDT 24
Peak memory 242012 kb
Host smart-bbaf0f92-786a-4b55-a9d7-af5692b3478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542730221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.3542730221
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.1009813576
Short name T1132
Test name
Test status
Simulation time 604998133 ps
CPU time 4.69 seconds
Started Apr 18 03:45:11 PM PDT 24
Finished Apr 18 03:45:16 PM PDT 24
Peak memory 241928 kb
Host smart-d0e9bcaa-d774-4d47-8049-20ed151d0f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009813576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.1009813576
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.2635555446
Short name T691
Test name
Test status
Simulation time 185442790 ps
CPU time 2.73 seconds
Started Apr 18 03:45:13 PM PDT 24
Finished Apr 18 03:45:16 PM PDT 24
Peak memory 242244 kb
Host smart-4665902f-ccfb-4945-a348-e96118b4b8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635555446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.2635555446
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.4148763858
Short name T473
Test name
Test status
Simulation time 119996767 ps
CPU time 5.06 seconds
Started Apr 18 03:45:12 PM PDT 24
Finished Apr 18 03:45:17 PM PDT 24
Peak memory 241884 kb
Host smart-959e6cc6-b755-4e1e-b9a2-0e039f745312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148763858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.4148763858
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.3240780634
Short name T272
Test name
Test status
Simulation time 703500253 ps
CPU time 9.35 seconds
Started Apr 18 03:45:12 PM PDT 24
Finished Apr 18 03:45:22 PM PDT 24
Peak memory 241692 kb
Host smart-cf060b67-753d-462d-b4a9-dcaa4e828b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240780634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3240780634
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.1863868794
Short name T977
Test name
Test status
Simulation time 423831298 ps
CPU time 3.47 seconds
Started Apr 18 03:45:17 PM PDT 24
Finished Apr 18 03:45:21 PM PDT 24
Peak memory 242064 kb
Host smart-6d45a150-4ef0-4a85-90b3-3476ddac89e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863868794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.1863868794
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.3681758996
Short name T368
Test name
Test status
Simulation time 736535632 ps
CPU time 11.38 seconds
Started Apr 18 03:45:18 PM PDT 24
Finished Apr 18 03:45:29 PM PDT 24
Peak memory 242108 kb
Host smart-57e29432-59ef-47e3-9026-aa4a3d994acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681758996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.3681758996
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.26663897
Short name T1010
Test name
Test status
Simulation time 1889073471 ps
CPU time 4.64 seconds
Started Apr 18 03:45:16 PM PDT 24
Finished Apr 18 03:45:21 PM PDT 24
Peak memory 242172 kb
Host smart-1e3ca4a4-94b5-4461-bb83-7181de0e8d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26663897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.26663897
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.4115190332
Short name T592
Test name
Test status
Simulation time 221368747 ps
CPU time 10.1 seconds
Started Apr 18 03:45:22 PM PDT 24
Finished Apr 18 03:45:32 PM PDT 24
Peak memory 241668 kb
Host smart-cd247b50-b3ef-45d3-9459-9efa091109c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115190332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.4115190332
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.2084875457
Short name T320
Test name
Test status
Simulation time 720815014 ps
CPU time 9.21 seconds
Started Apr 18 03:45:21 PM PDT 24
Finished Apr 18 03:45:31 PM PDT 24
Peak memory 241820 kb
Host smart-56988110-37d2-46c6-b083-44c3ea2ae7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084875457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.2084875457
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.1588530257
Short name T505
Test name
Test status
Simulation time 2061375538 ps
CPU time 6.06 seconds
Started Apr 18 03:45:19 PM PDT 24
Finished Apr 18 03:45:25 PM PDT 24
Peak memory 241820 kb
Host smart-bdede528-328f-4948-9067-e6ae6ad1b2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588530257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.1588530257
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.651151081
Short name T257
Test name
Test status
Simulation time 751900209 ps
CPU time 13.16 seconds
Started Apr 18 03:45:18 PM PDT 24
Finished Apr 18 03:45:32 PM PDT 24
Peak memory 242096 kb
Host smart-7292eb84-3273-40ea-adc1-39d7ef04e61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651151081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.651151081
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.2687732882
Short name T215
Test name
Test status
Simulation time 137116769 ps
CPU time 3.51 seconds
Started Apr 18 03:45:18 PM PDT 24
Finished Apr 18 03:45:22 PM PDT 24
Peak memory 241920 kb
Host smart-28d54db6-e503-435d-a491-73e253db069c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687732882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.2687732882
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.2331603357
Short name T1068
Test name
Test status
Simulation time 171799049 ps
CPU time 4.16 seconds
Started Apr 18 03:45:22 PM PDT 24
Finished Apr 18 03:45:26 PM PDT 24
Peak memory 241652 kb
Host smart-13278e9c-ce05-4519-91f4-042ed0983c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331603357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.2331603357
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.314518170
Short name T1099
Test name
Test status
Simulation time 327031770 ps
CPU time 4.28 seconds
Started Apr 18 03:45:24 PM PDT 24
Finished Apr 18 03:45:29 PM PDT 24
Peak memory 242132 kb
Host smart-452260b4-39d0-4a1c-8b62-2ea74ae90e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314518170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.314518170
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.349831911
Short name T593
Test name
Test status
Simulation time 666573163 ps
CPU time 19.51 seconds
Started Apr 18 03:45:16 PM PDT 24
Finished Apr 18 03:45:37 PM PDT 24
Peak memory 241692 kb
Host smart-e108507e-04c2-4df6-865f-72cbcc586302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349831911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.349831911
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.3195861191
Short name T1139
Test name
Test status
Simulation time 717592711 ps
CPU time 5.65 seconds
Started Apr 18 03:45:15 PM PDT 24
Finished Apr 18 03:45:22 PM PDT 24
Peak memory 242104 kb
Host smart-fd21709f-46a4-450c-b0c0-6ce0891a4042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195861191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.3195861191
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.1412252325
Short name T435
Test name
Test status
Simulation time 196881921 ps
CPU time 4.29 seconds
Started Apr 18 03:45:16 PM PDT 24
Finished Apr 18 03:45:21 PM PDT 24
Peak memory 241888 kb
Host smart-58c95534-b18e-44dd-beb9-1ea90a8110ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412252325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.1412252325
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.1258467714
Short name T421
Test name
Test status
Simulation time 58336802 ps
CPU time 1.88 seconds
Started Apr 18 03:39:14 PM PDT 24
Finished Apr 18 03:39:16 PM PDT 24
Peak memory 240064 kb
Host smart-226f3f7e-219c-449a-bcac-801a7efaf799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258467714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.1258467714
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.2141021760
Short name T1096
Test name
Test status
Simulation time 14018192146 ps
CPU time 29.46 seconds
Started Apr 18 03:39:09 PM PDT 24
Finished Apr 18 03:39:39 PM PDT 24
Peak memory 243036 kb
Host smart-b628cccc-0d58-4c6a-bb66-e34a5b66f50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141021760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.2141021760
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.3078284135
Short name T520
Test name
Test status
Simulation time 764009607 ps
CPU time 10.56 seconds
Started Apr 18 03:39:11 PM PDT 24
Finished Apr 18 03:39:21 PM PDT 24
Peak memory 241780 kb
Host smart-1d9147f2-50eb-4efd-84aa-7eb9d85e6b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078284135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.3078284135
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.2922668376
Short name T375
Test name
Test status
Simulation time 665760884 ps
CPU time 17.1 seconds
Started Apr 18 03:39:09 PM PDT 24
Finished Apr 18 03:39:26 PM PDT 24
Peak memory 242088 kb
Host smart-2feb67a7-9c84-4db8-888e-eaee241d0027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922668376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.2922668376
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.3635974927
Short name T863
Test name
Test status
Simulation time 335165588 ps
CPU time 4.73 seconds
Started Apr 18 03:39:07 PM PDT 24
Finished Apr 18 03:39:12 PM PDT 24
Peak memory 241756 kb
Host smart-3ca61bd6-c018-411a-b58b-bf6b061ad485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635974927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.3635974927
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.3381135548
Short name T165
Test name
Test status
Simulation time 3695762391 ps
CPU time 22.74 seconds
Started Apr 18 03:39:12 PM PDT 24
Finished Apr 18 03:39:35 PM PDT 24
Peak memory 242952 kb
Host smart-99f5837e-719c-49ec-b6e0-9d9800630e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381135548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.3381135548
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.269399665
Short name T686
Test name
Test status
Simulation time 3735632822 ps
CPU time 12.53 seconds
Started Apr 18 03:39:09 PM PDT 24
Finished Apr 18 03:39:22 PM PDT 24
Peak memory 242244 kb
Host smart-97759af6-23da-400f-b729-bde23ef55e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269399665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.269399665
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.2805513330
Short name T720
Test name
Test status
Simulation time 502060871 ps
CPU time 10.6 seconds
Started Apr 18 03:39:12 PM PDT 24
Finished Apr 18 03:39:23 PM PDT 24
Peak memory 241700 kb
Host smart-95c05045-db60-41b9-867b-337b04658662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805513330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.2805513330
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.260773038
Short name T1149
Test name
Test status
Simulation time 5812243963 ps
CPU time 10.36 seconds
Started Apr 18 03:39:10 PM PDT 24
Finished Apr 18 03:39:20 PM PDT 24
Peak memory 248664 kb
Host smart-375becb3-454e-4a90-a4bd-dfa7c5a01ee4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=260773038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.260773038
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.2891128906
Short name T350
Test name
Test status
Simulation time 410651441 ps
CPU time 4.32 seconds
Started Apr 18 03:39:12 PM PDT 24
Finished Apr 18 03:39:16 PM PDT 24
Peak memory 242172 kb
Host smart-436ca0bd-167e-4cca-9893-06bd6e169b1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2891128906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2891128906
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.2747093668
Short name T554
Test name
Test status
Simulation time 1019042131 ps
CPU time 5.82 seconds
Started Apr 18 03:39:02 PM PDT 24
Finished Apr 18 03:39:09 PM PDT 24
Peak memory 248648 kb
Host smart-6ce52415-8c0c-4b9e-9cb7-d67869aaa3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747093668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.2747093668
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.527501995
Short name T334
Test name
Test status
Simulation time 19311822387 ps
CPU time 236.56 seconds
Started Apr 18 03:39:16 PM PDT 24
Finished Apr 18 03:43:13 PM PDT 24
Peak memory 266036 kb
Host smart-b8d00eb7-c53e-4e20-a377-60d458f97b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527501995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.
527501995
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.1901900517
Short name T18
Test name
Test status
Simulation time 528106184646 ps
CPU time 1827.24 seconds
Started Apr 18 03:39:08 PM PDT 24
Finished Apr 18 04:09:36 PM PDT 24
Peak memory 306936 kb
Host smart-11ea9ba4-fdfa-4dd1-9bb8-4cfbf04eb6e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901900517 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.1901900517
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.2691745342
Short name T865
Test name
Test status
Simulation time 1314089623 ps
CPU time 20.17 seconds
Started Apr 18 03:39:09 PM PDT 24
Finished Apr 18 03:39:30 PM PDT 24
Peak memory 248628 kb
Host smart-44684d5f-7470-4e78-b5d9-36024ffb9246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691745342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.2691745342
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.4092012357
Short name T1197
Test name
Test status
Simulation time 396209711 ps
CPU time 4.29 seconds
Started Apr 18 03:45:23 PM PDT 24
Finished Apr 18 03:45:28 PM PDT 24
Peak memory 242060 kb
Host smart-32155b21-5f89-41ca-a4a5-73d5d73c8e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092012357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.4092012357
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.4235922615
Short name T253
Test name
Test status
Simulation time 157175579 ps
CPU time 4.04 seconds
Started Apr 18 03:45:22 PM PDT 24
Finished Apr 18 03:45:26 PM PDT 24
Peak memory 241892 kb
Host smart-1d82032d-f47c-41a3-88a9-c9b8346b008c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235922615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.4235922615
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.2339554256
Short name T240
Test name
Test status
Simulation time 297834977 ps
CPU time 4.29 seconds
Started Apr 18 03:45:23 PM PDT 24
Finished Apr 18 03:45:27 PM PDT 24
Peak memory 241920 kb
Host smart-3870281c-5f40-461e-baef-2f09e5507161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339554256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.2339554256
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.1681977626
Short name T406
Test name
Test status
Simulation time 449940214 ps
CPU time 3.93 seconds
Started Apr 18 03:45:20 PM PDT 24
Finished Apr 18 03:45:25 PM PDT 24
Peak memory 241820 kb
Host smart-71da8f63-804a-4aed-b38f-8b062a6b975c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681977626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.1681977626
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.94894255
Short name T164
Test name
Test status
Simulation time 360287350 ps
CPU time 4 seconds
Started Apr 18 03:45:21 PM PDT 24
Finished Apr 18 03:45:26 PM PDT 24
Peak memory 242100 kb
Host smart-2c08b6d1-6d81-4666-b05a-837ee84ba628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94894255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.94894255
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.1345774401
Short name T730
Test name
Test status
Simulation time 329203636 ps
CPU time 5.07 seconds
Started Apr 18 03:45:22 PM PDT 24
Finished Apr 18 03:45:28 PM PDT 24
Peak memory 241876 kb
Host smart-5e6b6fe7-3266-408d-845f-3a4828011449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345774401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.1345774401
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.1554751234
Short name T1117
Test name
Test status
Simulation time 2568319764 ps
CPU time 7.77 seconds
Started Apr 18 03:45:27 PM PDT 24
Finished Apr 18 03:45:36 PM PDT 24
Peak memory 242060 kb
Host smart-4b63c5e9-fdd4-46a4-8a3b-77dd01d12169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554751234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.1554751234
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.1375242576
Short name T306
Test name
Test status
Simulation time 8919339957 ps
CPU time 20.73 seconds
Started Apr 18 03:45:30 PM PDT 24
Finished Apr 18 03:45:52 PM PDT 24
Peak memory 242148 kb
Host smart-e44b6300-4287-4600-a40f-c62d066ed7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375242576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.1375242576
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.4286404234
Short name T71
Test name
Test status
Simulation time 152014396 ps
CPU time 4.33 seconds
Started Apr 18 03:45:31 PM PDT 24
Finished Apr 18 03:45:35 PM PDT 24
Peak memory 241844 kb
Host smart-895d4575-458d-4dc6-a0b7-8fa181ab23f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286404234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.4286404234
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.4066021486
Short name T381
Test name
Test status
Simulation time 1315260984 ps
CPU time 9.31 seconds
Started Apr 18 03:45:33 PM PDT 24
Finished Apr 18 03:45:43 PM PDT 24
Peak memory 241764 kb
Host smart-aa66a6a8-6b2c-44ca-a38c-f038b6249175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066021486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.4066021486
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.3867721346
Short name T862
Test name
Test status
Simulation time 352118605 ps
CPU time 4.33 seconds
Started Apr 18 03:45:27 PM PDT 24
Finished Apr 18 03:45:33 PM PDT 24
Peak memory 242148 kb
Host smart-c173b397-7403-49ba-9b94-43d0af3c6cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867721346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3867721346
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.4281974898
Short name T619
Test name
Test status
Simulation time 266372369 ps
CPU time 6.53 seconds
Started Apr 18 03:45:29 PM PDT 24
Finished Apr 18 03:45:36 PM PDT 24
Peak memory 242132 kb
Host smart-92d6eb0e-6dd6-4b90-9a1f-ecbb51e046cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281974898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.4281974898
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.3804524808
Short name T566
Test name
Test status
Simulation time 1588075044 ps
CPU time 4.32 seconds
Started Apr 18 03:45:33 PM PDT 24
Finished Apr 18 03:45:38 PM PDT 24
Peak memory 242120 kb
Host smart-77b73ac0-b01d-407d-9e37-b7ccdef43450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804524808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.3804524808
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.1445372615
Short name T534
Test name
Test status
Simulation time 2108980006 ps
CPU time 7.34 seconds
Started Apr 18 03:45:28 PM PDT 24
Finished Apr 18 03:45:36 PM PDT 24
Peak memory 242024 kb
Host smart-a72df90c-707a-4c0c-8c33-96c09ed14d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445372615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.1445372615
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.3970387472
Short name T1189
Test name
Test status
Simulation time 325679900 ps
CPU time 4.4 seconds
Started Apr 18 03:45:30 PM PDT 24
Finished Apr 18 03:45:35 PM PDT 24
Peak memory 241828 kb
Host smart-e76e1323-78e0-465a-8336-097a31b6bcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970387472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.3970387472
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.560819240
Short name T690
Test name
Test status
Simulation time 162905217 ps
CPU time 4.67 seconds
Started Apr 18 03:45:30 PM PDT 24
Finished Apr 18 03:45:36 PM PDT 24
Peak memory 241756 kb
Host smart-92afc215-1037-482f-a275-159f194548a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560819240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.560819240
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.2862042039
Short name T703
Test name
Test status
Simulation time 2007236145 ps
CPU time 4.63 seconds
Started Apr 18 03:45:28 PM PDT 24
Finished Apr 18 03:45:33 PM PDT 24
Peak memory 241800 kb
Host smart-64331f1c-806d-4a99-ba37-1bed8cefaeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862042039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.2862042039
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.2330326951
Short name T780
Test name
Test status
Simulation time 2848936027 ps
CPU time 7.26 seconds
Started Apr 18 03:45:27 PM PDT 24
Finished Apr 18 03:45:35 PM PDT 24
Peak memory 242140 kb
Host smart-a5f45ac2-fcc7-4639-8c08-ef4310643877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330326951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.2330326951
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.554614114
Short name T774
Test name
Test status
Simulation time 798359324 ps
CPU time 2.06 seconds
Started Apr 18 03:39:19 PM PDT 24
Finished Apr 18 03:39:22 PM PDT 24
Peak memory 240316 kb
Host smart-ab92a78e-8259-4a09-ba4c-aa413f5495c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554614114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.554614114
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.2115942795
Short name T1179
Test name
Test status
Simulation time 380704285 ps
CPU time 11.85 seconds
Started Apr 18 03:39:17 PM PDT 24
Finished Apr 18 03:39:29 PM PDT 24
Peak memory 248592 kb
Host smart-5c29f63d-8414-4d10-b29b-2718a07c89eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115942795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.2115942795
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.1469764098
Short name T419
Test name
Test status
Simulation time 2507133312 ps
CPU time 33.81 seconds
Started Apr 18 03:39:17 PM PDT 24
Finished Apr 18 03:39:51 PM PDT 24
Peak memory 242128 kb
Host smart-9ec5d494-a82c-47d7-ba2e-dfdf65b25ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469764098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.1469764098
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.2121956397
Short name T232
Test name
Test status
Simulation time 2023946894 ps
CPU time 42.93 seconds
Started Apr 18 03:39:13 PM PDT 24
Finished Apr 18 03:39:56 PM PDT 24
Peak memory 242316 kb
Host smart-2ab7443f-16d6-44f8-9eb4-bed597b1e60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121956397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.2121956397
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.1716927554
Short name T51
Test name
Test status
Simulation time 2644240463 ps
CPU time 7.72 seconds
Started Apr 18 03:39:13 PM PDT 24
Finished Apr 18 03:39:21 PM PDT 24
Peak memory 241984 kb
Host smart-b0ea64a2-e9f0-4e87-8645-35ad97107b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716927554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.1716927554
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.4223485405
Short name T1165
Test name
Test status
Simulation time 1221403740 ps
CPU time 25.91 seconds
Started Apr 18 03:39:15 PM PDT 24
Finished Apr 18 03:39:41 PM PDT 24
Peak memory 246328 kb
Host smart-7dffe084-a753-4394-9f09-4453a7587949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223485405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.4223485405
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.3302449876
Short name T249
Test name
Test status
Simulation time 4982267717 ps
CPU time 15.42 seconds
Started Apr 18 03:39:19 PM PDT 24
Finished Apr 18 03:39:35 PM PDT 24
Peak memory 243056 kb
Host smart-624d2c81-69c6-4579-8b95-0b19fc481074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302449876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.3302449876
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.1430165214
Short name T666
Test name
Test status
Simulation time 498479461 ps
CPU time 5.02 seconds
Started Apr 18 03:39:13 PM PDT 24
Finished Apr 18 03:39:19 PM PDT 24
Peak memory 242216 kb
Host smart-23e1e8ef-992e-449f-9faf-be477d0c8944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430165214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1430165214
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.3725630892
Short name T1036
Test name
Test status
Simulation time 630841060 ps
CPU time 11.67 seconds
Started Apr 18 03:39:19 PM PDT 24
Finished Apr 18 03:39:32 PM PDT 24
Peak memory 241840 kb
Host smart-becd9e4d-23fa-4a96-8a34-c8a82ebcd49b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725630892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.3725630892
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.510991057
Short name T537
Test name
Test status
Simulation time 740002220 ps
CPU time 8.91 seconds
Started Apr 18 03:39:17 PM PDT 24
Finished Apr 18 03:39:27 PM PDT 24
Peak memory 242056 kb
Host smart-539c9cb7-310d-4bcf-865c-b0b304709a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510991057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.510991057
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.756689788
Short name T627
Test name
Test status
Simulation time 189789671564 ps
CPU time 2036.65 seconds
Started Apr 18 03:39:19 PM PDT 24
Finished Apr 18 04:13:17 PM PDT 24
Peak memory 403112 kb
Host smart-6872546b-35ea-43a9-861a-9ac23047198f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756689788 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.756689788
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.3822167272
Short name T1195
Test name
Test status
Simulation time 774543601 ps
CPU time 13.28 seconds
Started Apr 18 03:39:21 PM PDT 24
Finished Apr 18 03:39:35 PM PDT 24
Peak memory 242212 kb
Host smart-1668ac73-14bd-4ed0-9246-65919ee1fb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822167272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.3822167272
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.1479822927
Short name T67
Test name
Test status
Simulation time 632124086 ps
CPU time 4.78 seconds
Started Apr 18 03:45:34 PM PDT 24
Finished Apr 18 03:45:39 PM PDT 24
Peak memory 241956 kb
Host smart-a10f87d0-0ca2-4230-8e1b-77d746d5c718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479822927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.1479822927
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.3053449372
Short name T1174
Test name
Test status
Simulation time 214198025 ps
CPU time 2.87 seconds
Started Apr 18 03:45:35 PM PDT 24
Finished Apr 18 03:45:38 PM PDT 24
Peak memory 241928 kb
Host smart-cb1388a8-e961-4473-8303-6b86a79560ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053449372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.3053449372
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.2348171845
Short name T646
Test name
Test status
Simulation time 399333225 ps
CPU time 4.69 seconds
Started Apr 18 03:45:33 PM PDT 24
Finished Apr 18 03:45:39 PM PDT 24
Peak memory 241760 kb
Host smart-946fd18f-ad41-4921-83cf-5b068c88e550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348171845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.2348171845
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.186025704
Short name T95
Test name
Test status
Simulation time 569675690 ps
CPU time 14.53 seconds
Started Apr 18 03:45:34 PM PDT 24
Finished Apr 18 03:45:49 PM PDT 24
Peak memory 241816 kb
Host smart-2801d467-791d-4f4f-b1f6-a049288b3946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186025704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.186025704
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.2666999464
Short name T45
Test name
Test status
Simulation time 143044926 ps
CPU time 3.76 seconds
Started Apr 18 03:45:34 PM PDT 24
Finished Apr 18 03:45:39 PM PDT 24
Peak memory 242164 kb
Host smart-7974e62a-7fd9-444a-b70f-cf892cc00db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666999464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.2666999464
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.2332501120
Short name T786
Test name
Test status
Simulation time 3118790267 ps
CPU time 11.68 seconds
Started Apr 18 03:45:34 PM PDT 24
Finished Apr 18 03:45:46 PM PDT 24
Peak memory 241772 kb
Host smart-272af479-3353-4e0e-90b3-1334841631b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332501120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.2332501120
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.3843572190
Short name T1177
Test name
Test status
Simulation time 140958338 ps
CPU time 4.14 seconds
Started Apr 18 03:45:35 PM PDT 24
Finished Apr 18 03:45:40 PM PDT 24
Peak memory 242104 kb
Host smart-ef77dd5d-37ac-46e5-86ad-00145f158e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843572190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.3843572190
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.1220384539
Short name T439
Test name
Test status
Simulation time 116560777 ps
CPU time 4.51 seconds
Started Apr 18 03:45:34 PM PDT 24
Finished Apr 18 03:45:40 PM PDT 24
Peak memory 241764 kb
Host smart-ad0a2f79-4317-4535-aa5f-fd6c98d61824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220384539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.1220384539
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.2621330975
Short name T221
Test name
Test status
Simulation time 390769969 ps
CPU time 5.11 seconds
Started Apr 18 03:45:35 PM PDT 24
Finished Apr 18 03:45:41 PM PDT 24
Peak memory 242088 kb
Host smart-1eb51782-201d-4011-9640-b5e301fc864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621330975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.2621330975
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.2412449137
Short name T182
Test name
Test status
Simulation time 395387012 ps
CPU time 11.19 seconds
Started Apr 18 03:45:34 PM PDT 24
Finished Apr 18 03:45:46 PM PDT 24
Peak memory 241808 kb
Host smart-6a7cd8fa-1cbd-4a84-9b48-ec03ae125020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412449137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2412449137
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.796228459
Short name T211
Test name
Test status
Simulation time 175938235 ps
CPU time 4.1 seconds
Started Apr 18 03:45:34 PM PDT 24
Finished Apr 18 03:45:39 PM PDT 24
Peak memory 242176 kb
Host smart-25822fe5-311b-473c-a43e-72b1c27628fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796228459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.796228459
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.3536116835
Short name T1018
Test name
Test status
Simulation time 199104218 ps
CPU time 6.87 seconds
Started Apr 18 03:45:33 PM PDT 24
Finished Apr 18 03:45:40 PM PDT 24
Peak memory 241852 kb
Host smart-1c69da3a-86e8-49c9-9e0d-a25b575ae037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536116835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.3536116835
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.3120180809
Short name T764
Test name
Test status
Simulation time 1844452552 ps
CPU time 7.02 seconds
Started Apr 18 03:45:33 PM PDT 24
Finished Apr 18 03:45:40 PM PDT 24
Peak memory 241904 kb
Host smart-5a1dcfb5-8732-49c8-a3fa-70bc2f49e29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120180809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.3120180809
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.690711835
Short name T251
Test name
Test status
Simulation time 739100799 ps
CPU time 23.71 seconds
Started Apr 18 03:45:38 PM PDT 24
Finished Apr 18 03:46:02 PM PDT 24
Peak memory 241780 kb
Host smart-b3a18d3e-98c6-4a90-ac31-f1ee1a542e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690711835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.690711835
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.3853185383
Short name T898
Test name
Test status
Simulation time 316794771 ps
CPU time 4.33 seconds
Started Apr 18 03:45:40 PM PDT 24
Finished Apr 18 03:45:45 PM PDT 24
Peak memory 241956 kb
Host smart-d5b9b347-75a4-4910-9862-563f83c86fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853185383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.3853185383
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.50127073
Short name T726
Test name
Test status
Simulation time 3764394531 ps
CPU time 20.58 seconds
Started Apr 18 03:45:41 PM PDT 24
Finished Apr 18 03:46:02 PM PDT 24
Peak memory 241916 kb
Host smart-f0b877e9-0167-4b6d-ade5-204ea00fed86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50127073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.50127073
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.2653627242
Short name T1175
Test name
Test status
Simulation time 124104695 ps
CPU time 4.72 seconds
Started Apr 18 03:45:38 PM PDT 24
Finished Apr 18 03:45:43 PM PDT 24
Peak memory 242192 kb
Host smart-a626fa34-0f92-4162-8459-f7b0f218bd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653627242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2653627242
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.3466670422
Short name T930
Test name
Test status
Simulation time 435292206 ps
CPU time 8.64 seconds
Started Apr 18 03:45:40 PM PDT 24
Finished Apr 18 03:45:49 PM PDT 24
Peak memory 242048 kb
Host smart-ff49a9de-5da8-4761-8361-9ce57f5fb8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466670422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.3466670422
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.495319432
Short name T542
Test name
Test status
Simulation time 1996642267 ps
CPU time 6.9 seconds
Started Apr 18 03:45:40 PM PDT 24
Finished Apr 18 03:45:47 PM PDT 24
Peak memory 241904 kb
Host smart-b765fe95-0d3c-40a5-8677-c7ed9409ae82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495319432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.495319432
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.2351986083
Short name T1098
Test name
Test status
Simulation time 185995075 ps
CPU time 4.73 seconds
Started Apr 18 03:45:39 PM PDT 24
Finished Apr 18 03:45:45 PM PDT 24
Peak memory 241692 kb
Host smart-4b9737d5-6690-4450-b398-fc568aed4831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351986083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.2351986083
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.1128194206
Short name T615
Test name
Test status
Simulation time 112545476 ps
CPU time 1.67 seconds
Started Apr 18 03:39:29 PM PDT 24
Finished Apr 18 03:39:31 PM PDT 24
Peak memory 240132 kb
Host smart-c95e6ba6-9e01-474d-bbca-5a883cde40c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128194206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.1128194206
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.3070387329
Short name T121
Test name
Test status
Simulation time 713509000 ps
CPU time 16.21 seconds
Started Apr 18 03:39:30 PM PDT 24
Finished Apr 18 03:39:47 PM PDT 24
Peak memory 248608 kb
Host smart-8993bcd4-02c8-4a2e-88c1-63811699cbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070387329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.3070387329
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.124339102
Short name T474
Test name
Test status
Simulation time 873869040 ps
CPU time 15.06 seconds
Started Apr 18 03:39:30 PM PDT 24
Finished Apr 18 03:39:46 PM PDT 24
Peak memory 241668 kb
Host smart-51ae75d7-26ca-4d90-a271-c6ca3d4d4e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124339102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.124339102
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.839681802
Short name T854
Test name
Test status
Simulation time 1191626318 ps
CPU time 28.17 seconds
Started Apr 18 03:39:29 PM PDT 24
Finished Apr 18 03:39:58 PM PDT 24
Peak memory 248628 kb
Host smart-8595e284-28b4-4b40-b593-8e3c007e10dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839681802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.839681802
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.3800025001
Short name T744
Test name
Test status
Simulation time 143782725 ps
CPU time 3.03 seconds
Started Apr 18 03:39:22 PM PDT 24
Finished Apr 18 03:39:26 PM PDT 24
Peak memory 242176 kb
Host smart-7a97715d-ff47-4190-8635-e78bcf01d726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800025001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.3800025001
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.1968961936
Short name T913
Test name
Test status
Simulation time 284347140 ps
CPU time 6.74 seconds
Started Apr 18 03:39:30 PM PDT 24
Finished Apr 18 03:39:37 PM PDT 24
Peak memory 241836 kb
Host smart-3603bfa9-9015-442a-873f-9d7e811a640e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968961936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1968961936
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.4122160639
Short name T548
Test name
Test status
Simulation time 991208951 ps
CPU time 32.95 seconds
Started Apr 18 03:39:34 PM PDT 24
Finished Apr 18 03:40:07 PM PDT 24
Peak memory 241752 kb
Host smart-a2b23495-8a38-4bab-9d9e-314e9432e5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122160639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.4122160639
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.1449018867
Short name T1049
Test name
Test status
Simulation time 1930119407 ps
CPU time 15.8 seconds
Started Apr 18 03:39:34 PM PDT 24
Finished Apr 18 03:39:51 PM PDT 24
Peak memory 241888 kb
Host smart-bb9cf723-565d-4f07-8fd3-03731367d70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449018867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.1449018867
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.2398472933
Short name T1198
Test name
Test status
Simulation time 785921699 ps
CPU time 19.44 seconds
Started Apr 18 03:39:23 PM PDT 24
Finished Apr 18 03:39:43 PM PDT 24
Peak memory 241708 kb
Host smart-c138b701-1ded-4ee0-be48-38dc61a0874e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398472933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.2398472933
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.1288141114
Short name T552
Test name
Test status
Simulation time 852645388 ps
CPU time 6.43 seconds
Started Apr 18 03:39:23 PM PDT 24
Finished Apr 18 03:39:30 PM PDT 24
Peak memory 241808 kb
Host smart-1453c0a9-6fc7-480f-8be3-5b9c8536311a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288141114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.1288141114
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.566178970
Short name T318
Test name
Test status
Simulation time 82402926754 ps
CPU time 1524 seconds
Started Apr 18 03:39:30 PM PDT 24
Finished Apr 18 04:04:55 PM PDT 24
Peak memory 404740 kb
Host smart-6798ebcb-1971-4ed7-982d-655760f87a10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566178970 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.566178970
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.1139970048
Short name T604
Test name
Test status
Simulation time 1552178437 ps
CPU time 30.24 seconds
Started Apr 18 03:39:28 PM PDT 24
Finished Apr 18 03:39:59 PM PDT 24
Peak memory 242340 kb
Host smart-88aa3aa6-61ad-4c5f-a19d-aca6eaad096a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139970048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.1139970048
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.2091984475
Short name T718
Test name
Test status
Simulation time 2428305796 ps
CPU time 6.03 seconds
Started Apr 18 03:45:40 PM PDT 24
Finished Apr 18 03:45:46 PM PDT 24
Peak memory 242216 kb
Host smart-c392f9d1-e5de-4ad4-88d8-4bacd385503f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091984475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2091984475
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.2297988997
Short name T692
Test name
Test status
Simulation time 634435728 ps
CPU time 5.75 seconds
Started Apr 18 03:45:38 PM PDT 24
Finished Apr 18 03:45:45 PM PDT 24
Peak memory 241616 kb
Host smart-4635fd13-34a9-4046-b807-2bae566af59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297988997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.2297988997
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.4063949130
Short name T398
Test name
Test status
Simulation time 198181451 ps
CPU time 3.39 seconds
Started Apr 18 03:45:40 PM PDT 24
Finished Apr 18 03:45:44 PM PDT 24
Peak memory 241804 kb
Host smart-7229fb08-32b8-4e1f-b5cc-bded3e078198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063949130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.4063949130
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.2780227372
Short name T497
Test name
Test status
Simulation time 1876622784 ps
CPU time 9.1 seconds
Started Apr 18 03:45:38 PM PDT 24
Finished Apr 18 03:45:48 PM PDT 24
Peak memory 242036 kb
Host smart-742bc61c-d1fe-49c5-8390-5f516d800271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780227372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.2780227372
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.1728921965
Short name T101
Test name
Test status
Simulation time 495498457 ps
CPU time 3.69 seconds
Started Apr 18 03:45:44 PM PDT 24
Finished Apr 18 03:45:48 PM PDT 24
Peak memory 242104 kb
Host smart-6e2cc4b2-bc77-41c3-8e93-94ec8c7f69da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728921965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.1728921965
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.3406316771
Short name T625
Test name
Test status
Simulation time 291770287 ps
CPU time 3.07 seconds
Started Apr 18 03:45:46 PM PDT 24
Finished Apr 18 03:45:49 PM PDT 24
Peak memory 242088 kb
Host smart-e311a5b2-7ee8-4d79-982b-aaee7977fd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406316771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.3406316771
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.405616190
Short name T817
Test name
Test status
Simulation time 1939562557 ps
CPU time 6.65 seconds
Started Apr 18 03:45:45 PM PDT 24
Finished Apr 18 03:45:52 PM PDT 24
Peak memory 241812 kb
Host smart-f3945344-f55c-460c-9f93-0f3015b95337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405616190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.405616190
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.3132876540
Short name T830
Test name
Test status
Simulation time 784251708 ps
CPU time 18.82 seconds
Started Apr 18 03:45:46 PM PDT 24
Finished Apr 18 03:46:05 PM PDT 24
Peak memory 242116 kb
Host smart-1c9674b6-b494-474b-b558-2a72c40eb1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132876540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3132876540
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.4137977901
Short name T800
Test name
Test status
Simulation time 287609617 ps
CPU time 3.81 seconds
Started Apr 18 03:45:43 PM PDT 24
Finished Apr 18 03:45:48 PM PDT 24
Peak memory 241896 kb
Host smart-07ba6f35-f578-484a-8ff8-9cd6087287de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137977901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.4137977901
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.1507008609
Short name T918
Test name
Test status
Simulation time 9627003308 ps
CPU time 32.71 seconds
Started Apr 18 03:45:42 PM PDT 24
Finished Apr 18 03:46:15 PM PDT 24
Peak memory 242008 kb
Host smart-d5f10e6d-e1a2-4332-aefa-1a2a6cc31e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507008609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1507008609
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.766716266
Short name T1163
Test name
Test status
Simulation time 471410425 ps
CPU time 5.82 seconds
Started Apr 18 03:45:44 PM PDT 24
Finished Apr 18 03:45:50 PM PDT 24
Peak memory 241772 kb
Host smart-a7ed16fc-279e-45fb-9d3a-67dc69374762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766716266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.766716266
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.3166404253
Short name T567
Test name
Test status
Simulation time 1493602820 ps
CPU time 21.26 seconds
Started Apr 18 03:45:43 PM PDT 24
Finished Apr 18 03:46:05 PM PDT 24
Peak memory 241744 kb
Host smart-f9f84e0b-c451-4c78-b319-c2f02b766fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166404253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.3166404253
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.2838937055
Short name T55
Test name
Test status
Simulation time 185973117 ps
CPU time 4.07 seconds
Started Apr 18 03:45:45 PM PDT 24
Finished Apr 18 03:45:49 PM PDT 24
Peak memory 241840 kb
Host smart-ac9c39de-dfbb-4159-8b1f-d9b63abe6cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838937055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2838937055
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.2394735468
Short name T1011
Test name
Test status
Simulation time 4713405834 ps
CPU time 13.98 seconds
Started Apr 18 03:45:44 PM PDT 24
Finished Apr 18 03:45:58 PM PDT 24
Peak memory 241776 kb
Host smart-95486794-3e7a-4ac6-b324-bc0c29572810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394735468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.2394735468
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.1843783473
Short name T622
Test name
Test status
Simulation time 243290068 ps
CPU time 5.48 seconds
Started Apr 18 03:45:49 PM PDT 24
Finished Apr 18 03:45:56 PM PDT 24
Peak memory 242000 kb
Host smart-356bbabf-70f7-47fa-ba04-96a5608127cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843783473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.1843783473
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.1517521707
Short name T489
Test name
Test status
Simulation time 193103346 ps
CPU time 4.72 seconds
Started Apr 18 03:45:48 PM PDT 24
Finished Apr 18 03:45:53 PM PDT 24
Peak memory 242012 kb
Host smart-49b4a892-a8c8-4f65-8e61-2c51f56dcc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517521707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.1517521707
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.3916103350
Short name T229
Test name
Test status
Simulation time 701382172 ps
CPU time 4.6 seconds
Started Apr 18 03:45:49 PM PDT 24
Finished Apr 18 03:45:55 PM PDT 24
Peak memory 242040 kb
Host smart-7147d221-84f4-4425-bb74-d2a496d0d63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916103350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.3916103350
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.3970139696
Short name T49
Test name
Test status
Simulation time 262009268 ps
CPU time 3.86 seconds
Started Apr 18 03:45:50 PM PDT 24
Finished Apr 18 03:45:54 PM PDT 24
Peak memory 241732 kb
Host smart-f57b44ff-a427-455e-9174-c57653530515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970139696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.3970139696
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.2454352294
Short name T1154
Test name
Test status
Simulation time 455399859 ps
CPU time 3.75 seconds
Started Apr 18 03:45:48 PM PDT 24
Finished Apr 18 03:45:52 PM PDT 24
Peak memory 241960 kb
Host smart-8679db3b-2b4e-4668-bc62-1a4cde97d947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454352294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.2454352294
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.67580812
Short name T399
Test name
Test status
Simulation time 122078446 ps
CPU time 1.95 seconds
Started Apr 18 03:39:36 PM PDT 24
Finished Apr 18 03:39:38 PM PDT 24
Peak memory 240044 kb
Host smart-8477bd61-8d61-491a-96f2-653f5e07530b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67580812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.67580812
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.933134836
Short name T964
Test name
Test status
Simulation time 1557601806 ps
CPU time 9.52 seconds
Started Apr 18 03:39:37 PM PDT 24
Finished Apr 18 03:39:48 PM PDT 24
Peak memory 248664 kb
Host smart-979c9f01-3c47-42ef-8305-b94b569b32cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933134836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.933134836
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.101621115
Short name T1118
Test name
Test status
Simulation time 462680540 ps
CPU time 12.67 seconds
Started Apr 18 03:39:34 PM PDT 24
Finished Apr 18 03:39:47 PM PDT 24
Peak memory 241840 kb
Host smart-c5fa908b-f54c-4cea-991f-097af332ec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101621115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.101621115
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.3071271247
Short name T501
Test name
Test status
Simulation time 1045261076 ps
CPU time 13.11 seconds
Started Apr 18 03:39:35 PM PDT 24
Finished Apr 18 03:39:49 PM PDT 24
Peak memory 241704 kb
Host smart-2664e621-e036-47df-b24c-9a057647ae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071271247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.3071271247
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.2429421609
Short name T823
Test name
Test status
Simulation time 106864383 ps
CPU time 4.04 seconds
Started Apr 18 03:39:35 PM PDT 24
Finished Apr 18 03:39:40 PM PDT 24
Peak memory 241848 kb
Host smart-6dd26c1b-d183-4a48-ab64-1447b2f37194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429421609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.2429421609
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.1061417502
Short name T1123
Test name
Test status
Simulation time 511529718 ps
CPU time 10.8 seconds
Started Apr 18 03:39:36 PM PDT 24
Finished Apr 18 03:39:47 PM PDT 24
Peak memory 242216 kb
Host smart-7f2842d9-f8b2-4723-bd08-63af39aaa564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061417502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1061417502
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.1537239975
Short name T571
Test name
Test status
Simulation time 3388798086 ps
CPU time 7.04 seconds
Started Apr 18 03:39:35 PM PDT 24
Finished Apr 18 03:39:43 PM PDT 24
Peak memory 242332 kb
Host smart-84dc8f69-8d81-4fa8-a9db-ea1d93ca005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537239975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.1537239975
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.2853241757
Short name T962
Test name
Test status
Simulation time 441920332 ps
CPU time 6.58 seconds
Started Apr 18 03:39:36 PM PDT 24
Finished Apr 18 03:39:43 PM PDT 24
Peak memory 248440 kb
Host smart-5f453db5-7a37-47a7-834e-51170c362298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853241757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.2853241757
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.2769507993
Short name T1137
Test name
Test status
Simulation time 1265140039 ps
CPU time 15.05 seconds
Started Apr 18 03:39:36 PM PDT 24
Finished Apr 18 03:39:52 PM PDT 24
Peak memory 241792 kb
Host smart-a4035308-b020-4c1a-9090-fb8d61d10688
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2769507993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.2769507993
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.430893563
Short name T1048
Test name
Test status
Simulation time 570137127 ps
CPU time 10.29 seconds
Started Apr 18 03:39:37 PM PDT 24
Finished Apr 18 03:39:48 PM PDT 24
Peak memory 242220 kb
Host smart-48fa0659-fa25-410a-9280-23fa2b325661
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=430893563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.430893563
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.2627660072
Short name T450
Test name
Test status
Simulation time 296845317 ps
CPU time 4.7 seconds
Started Apr 18 03:39:34 PM PDT 24
Finished Apr 18 03:39:39 PM PDT 24
Peak memory 242088 kb
Host smart-85cf8f13-5c42-4df2-b84a-87b8dfa7b228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627660072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.2627660072
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.2797745741
Short name T762
Test name
Test status
Simulation time 916636361 ps
CPU time 20.24 seconds
Started Apr 18 03:39:34 PM PDT 24
Finished Apr 18 03:39:55 PM PDT 24
Peak memory 242632 kb
Host smart-d134e75a-fc59-4782-8860-d349d7c62729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797745741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.2797745741
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.402969233
Short name T958
Test name
Test status
Simulation time 1982253185 ps
CPU time 4.34 seconds
Started Apr 18 03:45:49 PM PDT 24
Finished Apr 18 03:45:54 PM PDT 24
Peak memory 242108 kb
Host smart-ed0bb7b3-d917-4509-a3ea-d4ccf9a63d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402969233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.402969233
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.2710718364
Short name T110
Test name
Test status
Simulation time 583336059 ps
CPU time 8.23 seconds
Started Apr 18 03:45:48 PM PDT 24
Finished Apr 18 03:45:57 PM PDT 24
Peak memory 242104 kb
Host smart-e5c317a6-ec54-457d-8c67-69340008559c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710718364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.2710718364
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.3484066878
Short name T259
Test name
Test status
Simulation time 352864097 ps
CPU time 18.92 seconds
Started Apr 18 03:45:56 PM PDT 24
Finished Apr 18 03:46:16 PM PDT 24
Peak memory 241800 kb
Host smart-805ff0e3-9b77-46ec-a0cf-29429b888cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484066878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.3484066878
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.2672821790
Short name T1062
Test name
Test status
Simulation time 271182511 ps
CPU time 4.61 seconds
Started Apr 18 03:45:57 PM PDT 24
Finished Apr 18 03:46:02 PM PDT 24
Peak memory 242220 kb
Host smart-1685e27f-f7cb-431c-ab7a-251e98dd8203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672821790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.2672821790
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.2774624587
Short name T997
Test name
Test status
Simulation time 865937186 ps
CPU time 8.1 seconds
Started Apr 18 03:45:55 PM PDT 24
Finished Apr 18 03:46:04 PM PDT 24
Peak memory 241764 kb
Host smart-3227bf16-f1c7-428f-86f2-b60e5c5102ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774624587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.2774624587
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.3132907793
Short name T172
Test name
Test status
Simulation time 240257253 ps
CPU time 4.2 seconds
Started Apr 18 03:45:53 PM PDT 24
Finished Apr 18 03:45:58 PM PDT 24
Peak memory 241812 kb
Host smart-a7e29f56-4ed6-44a8-be1d-53f3a4139f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132907793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.3132907793
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.1464494031
Short name T582
Test name
Test status
Simulation time 696516276 ps
CPU time 18.11 seconds
Started Apr 18 03:45:54 PM PDT 24
Finished Apr 18 03:46:13 PM PDT 24
Peak memory 242016 kb
Host smart-e0233cad-28c0-435e-bdfc-d4fe7b521daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464494031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.1464494031
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.964849149
Short name T685
Test name
Test status
Simulation time 1742883514 ps
CPU time 5.91 seconds
Started Apr 18 03:45:53 PM PDT 24
Finished Apr 18 03:45:59 PM PDT 24
Peak memory 241920 kb
Host smart-c9be26b0-24ea-4065-8fa1-cfffa393047e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964849149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.964849149
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.1573125270
Short name T1024
Test name
Test status
Simulation time 1178553387 ps
CPU time 3.24 seconds
Started Apr 18 03:45:57 PM PDT 24
Finished Apr 18 03:46:01 PM PDT 24
Peak memory 242012 kb
Host smart-6406a15e-6c6e-4968-9652-4399db971334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573125270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.1573125270
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.323266692
Short name T122
Test name
Test status
Simulation time 311329836 ps
CPU time 3.58 seconds
Started Apr 18 03:45:53 PM PDT 24
Finished Apr 18 03:45:58 PM PDT 24
Peak memory 241864 kb
Host smart-3d1fde4c-4731-40b2-9505-9a9562023063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323266692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.323266692
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.3717935666
Short name T1013
Test name
Test status
Simulation time 1359803325 ps
CPU time 13.24 seconds
Started Apr 18 03:45:55 PM PDT 24
Finished Apr 18 03:46:09 PM PDT 24
Peak memory 241768 kb
Host smart-02d9282f-3e78-41d4-9c16-c0fe74e35087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717935666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3717935666
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.2567089821
Short name T911
Test name
Test status
Simulation time 106974946 ps
CPU time 4.26 seconds
Started Apr 18 03:45:56 PM PDT 24
Finished Apr 18 03:46:01 PM PDT 24
Peak memory 242132 kb
Host smart-bbe5d7df-3ecb-4af5-a584-129bd625dc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567089821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.2567089821
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.107904245
Short name T710
Test name
Test status
Simulation time 487352383 ps
CPU time 7.44 seconds
Started Apr 18 03:45:53 PM PDT 24
Finished Apr 18 03:46:01 PM PDT 24
Peak memory 242036 kb
Host smart-16a1f964-9bef-47b4-b6a7-ce9edd215dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107904245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.107904245
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.371313148
Short name T1089
Test name
Test status
Simulation time 630746670 ps
CPU time 4.95 seconds
Started Apr 18 03:45:56 PM PDT 24
Finished Apr 18 03:46:02 PM PDT 24
Peak memory 241732 kb
Host smart-fad15266-c463-475e-a557-86ce00481be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371313148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.371313148
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.169675307
Short name T680
Test name
Test status
Simulation time 194565941 ps
CPU time 5.15 seconds
Started Apr 18 03:45:54 PM PDT 24
Finished Apr 18 03:46:00 PM PDT 24
Peak memory 241780 kb
Host smart-b8f1dec8-8ec7-46cb-9804-1a37e5496401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169675307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.169675307
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.884461497
Short name T1025
Test name
Test status
Simulation time 321977162 ps
CPU time 9.91 seconds
Started Apr 18 03:45:53 PM PDT 24
Finished Apr 18 03:46:04 PM PDT 24
Peak memory 241876 kb
Host smart-2e740514-3275-492e-a048-46046f444458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884461497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.884461497
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.1815177383
Short name T522
Test name
Test status
Simulation time 2622417892 ps
CPU time 4.82 seconds
Started Apr 18 03:45:53 PM PDT 24
Finished Apr 18 03:45:59 PM PDT 24
Peak memory 241820 kb
Host smart-d6a7f47d-11e7-4619-b69e-c7ce2784e54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815177383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1815177383
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.1458120509
Short name T557
Test name
Test status
Simulation time 856891147 ps
CPU time 14.87 seconds
Started Apr 18 03:45:54 PM PDT 24
Finished Apr 18 03:46:10 PM PDT 24
Peak memory 242032 kb
Host smart-9e68312b-ff11-44cc-8ec3-0396ef5ce350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458120509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1458120509
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.548881757
Short name T998
Test name
Test status
Simulation time 792507696 ps
CPU time 2.53 seconds
Started Apr 18 03:39:44 PM PDT 24
Finished Apr 18 03:39:47 PM PDT 24
Peak memory 240128 kb
Host smart-f4ed18da-5491-432e-ada2-93c4e588fd46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548881757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.548881757
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.4222233531
Short name T523
Test name
Test status
Simulation time 1604644768 ps
CPU time 25.46 seconds
Started Apr 18 03:39:43 PM PDT 24
Finished Apr 18 03:40:09 PM PDT 24
Peak memory 242024 kb
Host smart-150f14c9-678b-4c15-9b0e-dcc26e45ede0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222233531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.4222233531
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.121100397
Short name T752
Test name
Test status
Simulation time 291687230 ps
CPU time 15.83 seconds
Started Apr 18 03:39:40 PM PDT 24
Finished Apr 18 03:39:56 PM PDT 24
Peak memory 242220 kb
Host smart-e5174374-a4c7-492c-bdac-9d9110fea1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121100397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.121100397
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.2502756835
Short name T528
Test name
Test status
Simulation time 1117761578 ps
CPU time 16.46 seconds
Started Apr 18 03:39:39 PM PDT 24
Finished Apr 18 03:39:56 PM PDT 24
Peak memory 242140 kb
Host smart-c92d82d3-d934-4b7a-8da5-3b9e8e8feda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502756835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.2502756835
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.3442351622
Short name T191
Test name
Test status
Simulation time 322959766 ps
CPU time 3.89 seconds
Started Apr 18 03:39:39 PM PDT 24
Finished Apr 18 03:39:43 PM PDT 24
Peak memory 242184 kb
Host smart-0fdc5221-d754-4d02-acf5-70969738cd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442351622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.3442351622
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.782378199
Short name T1005
Test name
Test status
Simulation time 3440623038 ps
CPU time 45.67 seconds
Started Apr 18 03:39:41 PM PDT 24
Finished Apr 18 03:40:27 PM PDT 24
Peak memory 257052 kb
Host smart-8c697b66-b4b5-4cad-a285-4687e99c45db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782378199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.782378199
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.3871066764
Short name T628
Test name
Test status
Simulation time 241578186 ps
CPU time 10.84 seconds
Started Apr 18 03:39:39 PM PDT 24
Finished Apr 18 03:39:51 PM PDT 24
Peak memory 241904 kb
Host smart-34e5192c-b6f9-43f0-af40-764c3cba426c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871066764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.3871066764
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.3743541714
Short name T667
Test name
Test status
Simulation time 1367331879 ps
CPU time 11.68 seconds
Started Apr 18 03:39:39 PM PDT 24
Finished Apr 18 03:39:51 PM PDT 24
Peak memory 241800 kb
Host smart-45caf3ad-feb4-40d3-adb8-0aac69d4ea08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3743541714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.3743541714
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.705652909
Short name T601
Test name
Test status
Simulation time 638948130 ps
CPU time 13.35 seconds
Started Apr 18 03:39:40 PM PDT 24
Finished Apr 18 03:39:54 PM PDT 24
Peak memory 241952 kb
Host smart-8e1d2ef0-0508-41ae-8a22-b224a2a17117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705652909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.705652909
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.3918196531
Short name T21
Test name
Test status
Simulation time 246787849304 ps
CPU time 1898.67 seconds
Started Apr 18 03:39:45 PM PDT 24
Finished Apr 18 04:11:24 PM PDT 24
Peak memory 281024 kb
Host smart-a2e9f18f-0ffa-4d30-947c-e8d12eb0d06e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918196531 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.3918196531
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.3532090120
Short name T184
Test name
Test status
Simulation time 1441798086 ps
CPU time 24.4 seconds
Started Apr 18 03:39:39 PM PDT 24
Finished Apr 18 03:40:04 PM PDT 24
Peak memory 242192 kb
Host smart-66c0d1f8-3d2b-417f-9f20-2bdbb297150a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532090120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.3532090120
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.3761283932
Short name T506
Test name
Test status
Simulation time 385389809 ps
CPU time 4.42 seconds
Started Apr 18 03:45:54 PM PDT 24
Finished Apr 18 03:45:59 PM PDT 24
Peak memory 241880 kb
Host smart-69e0dd97-3fbe-4cb4-9c01-07d1b75bc16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761283932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.3761283932
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.3948786328
Short name T1065
Test name
Test status
Simulation time 915217203 ps
CPU time 15.68 seconds
Started Apr 18 03:46:01 PM PDT 24
Finished Apr 18 03:46:18 PM PDT 24
Peak memory 241984 kb
Host smart-8f315846-3049-4483-8e69-f09f4a3a1c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948786328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3948786328
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.1861723879
Short name T714
Test name
Test status
Simulation time 125776733 ps
CPU time 3.39 seconds
Started Apr 18 03:45:58 PM PDT 24
Finished Apr 18 03:46:02 PM PDT 24
Peak memory 241924 kb
Host smart-130ffdbc-952a-4b90-84a1-58c20874e100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861723879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.1861723879
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.1485871534
Short name T2
Test name
Test status
Simulation time 4999626415 ps
CPU time 13.87 seconds
Started Apr 18 03:45:59 PM PDT 24
Finished Apr 18 03:46:14 PM PDT 24
Peak memory 242012 kb
Host smart-6992a041-6988-4813-9d05-868ad96795df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485871534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.1485871534
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.1382043481
Short name T725
Test name
Test status
Simulation time 373166910 ps
CPU time 4.52 seconds
Started Apr 18 03:45:59 PM PDT 24
Finished Apr 18 03:46:04 PM PDT 24
Peak memory 242088 kb
Host smart-a5ca6a4e-e23c-482d-aa6e-74cf0e022048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382043481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.1382043481
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.2645825876
Short name T218
Test name
Test status
Simulation time 384612750 ps
CPU time 20.98 seconds
Started Apr 18 03:46:04 PM PDT 24
Finished Apr 18 03:46:26 PM PDT 24
Peak memory 241608 kb
Host smart-b87ae2e5-b7e0-449f-99ca-b30b2a08dbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645825876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.2645825876
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.868971605
Short name T753
Test name
Test status
Simulation time 223461811 ps
CPU time 4.28 seconds
Started Apr 18 03:45:57 PM PDT 24
Finished Apr 18 03:46:02 PM PDT 24
Peak memory 241920 kb
Host smart-6a732020-29c1-4c63-85bf-7e8e2c7ede42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868971605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.868971605
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.1918469372
Short name T1152
Test name
Test status
Simulation time 97316656 ps
CPU time 4.4 seconds
Started Apr 18 03:46:00 PM PDT 24
Finished Apr 18 03:46:06 PM PDT 24
Peak memory 241692 kb
Host smart-1cb77982-1cec-4648-bb9a-bc04010e8ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918469372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.1918469372
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.3232019409
Short name T470
Test name
Test status
Simulation time 2539996064 ps
CPU time 22.58 seconds
Started Apr 18 03:45:58 PM PDT 24
Finished Apr 18 03:46:22 PM PDT 24
Peak memory 241864 kb
Host smart-2e6953be-dd8c-4d08-b1e9-f3995daf78b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232019409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.3232019409
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.2238329269
Short name T981
Test name
Test status
Simulation time 135225427 ps
CPU time 4.2 seconds
Started Apr 18 03:45:58 PM PDT 24
Finished Apr 18 03:46:03 PM PDT 24
Peak memory 242144 kb
Host smart-b6133db5-4e20-4db6-8ece-235339212b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238329269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2238329269
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.2074651589
Short name T11
Test name
Test status
Simulation time 9869654182 ps
CPU time 24.86 seconds
Started Apr 18 03:46:07 PM PDT 24
Finished Apr 18 03:46:32 PM PDT 24
Peak memory 242148 kb
Host smart-ffa97f67-813e-4d0a-a1f4-def44ffd1a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074651589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.2074651589
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.1619944205
Short name T130
Test name
Test status
Simulation time 105328922 ps
CPU time 4.03 seconds
Started Apr 18 03:45:58 PM PDT 24
Finished Apr 18 03:46:03 PM PDT 24
Peak memory 241796 kb
Host smart-27c65326-cc23-45c2-86cd-108815cbdfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619944205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.1619944205
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.916931752
Short name T866
Test name
Test status
Simulation time 145621616 ps
CPU time 7.8 seconds
Started Apr 18 03:46:15 PM PDT 24
Finished Apr 18 03:46:23 PM PDT 24
Peak memory 242032 kb
Host smart-e9adba93-480b-420d-bd28-cc861106264a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916931752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.916931752
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.2947289340
Short name T134
Test name
Test status
Simulation time 136025454 ps
CPU time 3.78 seconds
Started Apr 18 03:46:11 PM PDT 24
Finished Apr 18 03:46:16 PM PDT 24
Peak memory 241892 kb
Host smart-22fe27a9-0fd9-48bd-a525-90f9d949e9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947289340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.2947289340
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.2783821238
Short name T669
Test name
Test status
Simulation time 106623148 ps
CPU time 4.71 seconds
Started Apr 18 03:46:11 PM PDT 24
Finished Apr 18 03:46:16 PM PDT 24
Peak memory 241792 kb
Host smart-7b581e9a-85ac-4b6a-99d8-637d49da4956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783821238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.2783821238
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.990618386
Short name T852
Test name
Test status
Simulation time 1585902124 ps
CPU time 4.17 seconds
Started Apr 18 03:46:12 PM PDT 24
Finished Apr 18 03:46:17 PM PDT 24
Peak memory 241824 kb
Host smart-0c5e1fc0-d602-493e-a417-04d86627eec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990618386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.990618386
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.1984286464
Short name T729
Test name
Test status
Simulation time 6148586352 ps
CPU time 14.79 seconds
Started Apr 18 03:46:12 PM PDT 24
Finished Apr 18 03:46:28 PM PDT 24
Peak memory 242288 kb
Host smart-b9206341-3750-433f-a2bc-e6e4fa595e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984286464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.1984286464
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.3661780610
Short name T1135
Test name
Test status
Simulation time 397995020 ps
CPU time 4.02 seconds
Started Apr 18 03:46:10 PM PDT 24
Finished Apr 18 03:46:15 PM PDT 24
Peak memory 242192 kb
Host smart-96cc1267-2a00-4ea1-8d81-bfb3e14a25d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661780610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.3661780610
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.2465930056
Short name T853
Test name
Test status
Simulation time 1591655925 ps
CPU time 6.66 seconds
Started Apr 18 03:46:04 PM PDT 24
Finished Apr 18 03:46:12 PM PDT 24
Peak memory 241792 kb
Host smart-cd78b23e-095b-49b2-ba0e-d9fb7f0d8ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465930056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.2465930056
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.2417529260
Short name T1097
Test name
Test status
Simulation time 637421693 ps
CPU time 2.07 seconds
Started Apr 18 03:39:50 PM PDT 24
Finished Apr 18 03:39:52 PM PDT 24
Peak memory 240108 kb
Host smart-c811fce1-7d94-4598-b3c4-3c5669a656c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417529260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.2417529260
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.1435378049
Short name T131
Test name
Test status
Simulation time 1053999469 ps
CPU time 20.52 seconds
Started Apr 18 03:39:47 PM PDT 24
Finished Apr 18 03:40:08 PM PDT 24
Peak memory 243344 kb
Host smart-d810c326-c853-41e9-be9e-b8e2befd990d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435378049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.1435378049
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.542999006
Short name T991
Test name
Test status
Simulation time 11781262598 ps
CPU time 46.15 seconds
Started Apr 18 03:39:46 PM PDT 24
Finished Apr 18 03:40:33 PM PDT 24
Peak memory 243800 kb
Host smart-0c2e2ab0-b76c-48b1-ab93-228de42eeff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542999006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.542999006
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.3063827048
Short name T973
Test name
Test status
Simulation time 644133379 ps
CPU time 20.91 seconds
Started Apr 18 03:39:44 PM PDT 24
Finished Apr 18 03:40:05 PM PDT 24
Peak memory 241952 kb
Host smart-ea9debeb-d809-4727-b261-13c3ca4d0b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063827048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.3063827048
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.1970358336
Short name T556
Test name
Test status
Simulation time 1981542649 ps
CPU time 5.95 seconds
Started Apr 18 03:39:45 PM PDT 24
Finished Apr 18 03:39:51 PM PDT 24
Peak memory 242116 kb
Host smart-3e8f901f-8f2e-41f7-af12-8371f2456bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970358336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.1970358336
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.1000984675
Short name T200
Test name
Test status
Simulation time 530524820 ps
CPU time 8.56 seconds
Started Apr 18 03:39:49 PM PDT 24
Finished Apr 18 03:39:58 PM PDT 24
Peak memory 241884 kb
Host smart-0b9a49d4-5e07-40ef-98b3-be54eae550da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000984675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.1000984675
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.3942935447
Short name T1091
Test name
Test status
Simulation time 6527423138 ps
CPU time 10.11 seconds
Started Apr 18 03:39:48 PM PDT 24
Finished Apr 18 03:39:58 PM PDT 24
Peak memory 243128 kb
Host smart-07682116-59ab-4806-840b-f96ca1835392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942935447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.3942935447
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.672646729
Short name T260
Test name
Test status
Simulation time 405317861 ps
CPU time 4.8 seconds
Started Apr 18 03:39:47 PM PDT 24
Finished Apr 18 03:39:53 PM PDT 24
Peak memory 241784 kb
Host smart-3b790bdf-2b2b-4f24-a8f9-c2d660af6ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672646729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.672646729
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.1390001366
Short name T1047
Test name
Test status
Simulation time 270401585 ps
CPU time 7.03 seconds
Started Apr 18 03:39:50 PM PDT 24
Finished Apr 18 03:39:58 PM PDT 24
Peak memory 248588 kb
Host smart-cf32198c-24d2-438b-944e-b8f9d9578132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390001366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.1390001366
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.1488119517
Short name T1142
Test name
Test status
Simulation time 568241376 ps
CPU time 7.37 seconds
Started Apr 18 03:39:49 PM PDT 24
Finished Apr 18 03:39:57 PM PDT 24
Peak memory 241896 kb
Host smart-1611e6dd-461f-4acc-acbd-11511942120d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1488119517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.1488119517
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.3139704028
Short name T274
Test name
Test status
Simulation time 200180678 ps
CPU time 5.87 seconds
Started Apr 18 03:39:46 PM PDT 24
Finished Apr 18 03:39:52 PM PDT 24
Peak memory 241956 kb
Host smart-ce251701-8130-4ac4-8077-f76c32528093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139704028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.3139704028
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.1450963069
Short name T655
Test name
Test status
Simulation time 11846601937 ps
CPU time 219.44 seconds
Started Apr 18 03:39:49 PM PDT 24
Finished Apr 18 03:43:29 PM PDT 24
Peak memory 247420 kb
Host smart-9c6c68c2-d0f7-4ac2-8d76-491630008ed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450963069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.1450963069
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.3590543365
Short name T1138
Test name
Test status
Simulation time 77898189845 ps
CPU time 1861.61 seconds
Started Apr 18 03:39:50 PM PDT 24
Finished Apr 18 04:10:52 PM PDT 24
Peak memory 324080 kb
Host smart-62332f05-fb9c-4371-9652-612df7d8c146
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590543365 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.3590543365
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.4111666350
Short name T1128
Test name
Test status
Simulation time 999481199 ps
CPU time 12.62 seconds
Started Apr 18 03:39:55 PM PDT 24
Finished Apr 18 03:40:08 PM PDT 24
Peak memory 242148 kb
Host smart-f79da905-4899-41ce-90e0-9d6e5353ef99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111666350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.4111666350
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.3245338426
Short name T36
Test name
Test status
Simulation time 330190244 ps
CPU time 4.32 seconds
Started Apr 18 03:46:17 PM PDT 24
Finished Apr 18 03:46:22 PM PDT 24
Peak memory 242124 kb
Host smart-701b540f-d5be-4bb8-964f-638dfbbe48d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245338426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.3245338426
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.284217924
Short name T157
Test name
Test status
Simulation time 106870493 ps
CPU time 2.7 seconds
Started Apr 18 03:46:03 PM PDT 24
Finished Apr 18 03:46:06 PM PDT 24
Peak memory 241628 kb
Host smart-ec99b875-1d4d-44da-bed2-d7cb0fcd01c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284217924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.284217924
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.2891872043
Short name T1146
Test name
Test status
Simulation time 196041528 ps
CPU time 3.73 seconds
Started Apr 18 03:46:08 PM PDT 24
Finished Apr 18 03:46:12 PM PDT 24
Peak memory 241820 kb
Host smart-7b4c5848-bbeb-4aef-b203-09130a51fb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891872043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.2891872043
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.365569616
Short name T789
Test name
Test status
Simulation time 1271938308 ps
CPU time 22.01 seconds
Started Apr 18 03:46:04 PM PDT 24
Finished Apr 18 03:46:26 PM PDT 24
Peak memory 241716 kb
Host smart-fa58bfa1-428e-4224-8eb7-5ebeb295ab39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365569616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.365569616
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.4261940857
Short name T826
Test name
Test status
Simulation time 347422608 ps
CPU time 3.69 seconds
Started Apr 18 03:46:14 PM PDT 24
Finished Apr 18 03:46:18 PM PDT 24
Peak memory 242088 kb
Host smart-15bddaab-ace6-4986-bd92-e610debf23a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261940857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.4261940857
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.733307035
Short name T783
Test name
Test status
Simulation time 2299032723 ps
CPU time 9.47 seconds
Started Apr 18 03:46:10 PM PDT 24
Finished Apr 18 03:46:20 PM PDT 24
Peak memory 241816 kb
Host smart-5684aef8-e06d-4aa6-97b9-0fb6ee679165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733307035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.733307035
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.3386261502
Short name T503
Test name
Test status
Simulation time 281155338 ps
CPU time 3.44 seconds
Started Apr 18 03:46:17 PM PDT 24
Finished Apr 18 03:46:21 PM PDT 24
Peak memory 241800 kb
Host smart-8657b80a-c9be-4093-bdfb-53306700ceb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386261502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.3386261502
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.1622523247
Short name T154
Test name
Test status
Simulation time 195420448 ps
CPU time 7.34 seconds
Started Apr 18 03:46:08 PM PDT 24
Finished Apr 18 03:46:16 PM PDT 24
Peak memory 241616 kb
Host smart-ef45758f-841b-45b8-9ea4-b22a68278e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622523247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.1622523247
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.398159655
Short name T657
Test name
Test status
Simulation time 211021482 ps
CPU time 4.16 seconds
Started Apr 18 03:46:12 PM PDT 24
Finished Apr 18 03:46:17 PM PDT 24
Peak memory 242164 kb
Host smart-1158f744-999c-428e-8586-4c919be8545a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398159655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.398159655
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.3198273918
Short name T208
Test name
Test status
Simulation time 543010208 ps
CPU time 16.71 seconds
Started Apr 18 03:46:11 PM PDT 24
Finished Apr 18 03:46:28 PM PDT 24
Peak memory 241780 kb
Host smart-6d87bb3e-429e-4773-93ec-24427f29a53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198273918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.3198273918
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.3724322420
Short name T836
Test name
Test status
Simulation time 261687440 ps
CPU time 3.83 seconds
Started Apr 18 03:46:13 PM PDT 24
Finished Apr 18 03:46:18 PM PDT 24
Peak memory 241820 kb
Host smart-3d318106-bd1f-4e62-ba3a-06711279c5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724322420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.3724322420
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.2768875755
Short name T185
Test name
Test status
Simulation time 243002152 ps
CPU time 7.06 seconds
Started Apr 18 03:46:12 PM PDT 24
Finished Apr 18 03:46:20 PM PDT 24
Peak memory 241676 kb
Host smart-00804d90-b3a3-4fdc-922c-1b8be1a9f3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768875755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.2768875755
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.374256158
Short name T193
Test name
Test status
Simulation time 245258172 ps
CPU time 3.39 seconds
Started Apr 18 03:46:14 PM PDT 24
Finished Apr 18 03:46:18 PM PDT 24
Peak memory 241772 kb
Host smart-26649c68-7c34-47f3-990a-3a0373df77c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374256158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.374256158
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.2961650214
Short name T397
Test name
Test status
Simulation time 1828392355 ps
CPU time 29.34 seconds
Started Apr 18 03:46:09 PM PDT 24
Finished Apr 18 03:46:39 PM PDT 24
Peak memory 241756 kb
Host smart-4d9aaecc-d8f1-4182-a38f-9f25daf00a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961650214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.2961650214
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.4064607345
Short name T578
Test name
Test status
Simulation time 132299994 ps
CPU time 5.08 seconds
Started Apr 18 03:46:14 PM PDT 24
Finished Apr 18 03:46:20 PM PDT 24
Peak memory 241844 kb
Host smart-360c7689-5455-4a21-9772-8b2df13e5818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064607345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.4064607345
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.3585404756
Short name T961
Test name
Test status
Simulation time 439875362 ps
CPU time 12.06 seconds
Started Apr 18 03:46:11 PM PDT 24
Finished Apr 18 03:46:24 PM PDT 24
Peak memory 241880 kb
Host smart-6b09c2d2-e6c9-4f44-9bf2-eeb599664aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585404756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.3585404756
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.2448988102
Short name T96
Test name
Test status
Simulation time 560559687 ps
CPU time 6.11 seconds
Started Apr 18 03:46:10 PM PDT 24
Finished Apr 18 03:46:16 PM PDT 24
Peak memory 241684 kb
Host smart-a153d0a9-0944-4f6b-a6ec-5982593e8623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448988102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.2448988102
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.4156197973
Short name T137
Test name
Test status
Simulation time 206165277 ps
CPU time 4.19 seconds
Started Apr 18 03:46:12 PM PDT 24
Finished Apr 18 03:46:17 PM PDT 24
Peak memory 241904 kb
Host smart-94e94e93-40a4-429c-8aea-dd2747f02634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156197973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.4156197973
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.1891471953
Short name T417
Test name
Test status
Simulation time 843044726 ps
CPU time 5.72 seconds
Started Apr 18 03:46:16 PM PDT 24
Finished Apr 18 03:46:22 PM PDT 24
Peak memory 242096 kb
Host smart-4bbc8a14-c0c9-43fd-a135-2d298f3b11a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891471953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.1891471953
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.2937844077
Short name T938
Test name
Test status
Simulation time 75170403 ps
CPU time 2.06 seconds
Started Apr 18 03:39:58 PM PDT 24
Finished Apr 18 03:40:01 PM PDT 24
Peak memory 240120 kb
Host smart-c6efc524-beb7-4a4d-ab09-1ed06f23d656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937844077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.2937844077
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.1699860407
Short name T527
Test name
Test status
Simulation time 2253962871 ps
CPU time 23.48 seconds
Started Apr 18 03:39:56 PM PDT 24
Finished Apr 18 03:40:21 PM PDT 24
Peak memory 243868 kb
Host smart-2cdcfc5b-3061-49b7-849a-fae5be419797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699860407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.1699860407
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.4117787467
Short name T992
Test name
Test status
Simulation time 362062192 ps
CPU time 22.49 seconds
Started Apr 18 03:39:55 PM PDT 24
Finished Apr 18 03:40:18 PM PDT 24
Peak memory 241828 kb
Host smart-3329ff00-6c79-478f-a542-75b2d8e408a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117787467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.4117787467
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.3058005618
Short name T516
Test name
Test status
Simulation time 2410014119 ps
CPU time 24.39 seconds
Started Apr 18 03:39:56 PM PDT 24
Finished Apr 18 03:40:21 PM PDT 24
Peak memory 242812 kb
Host smart-91469365-e282-4300-8108-af8c3667a423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058005618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.3058005618
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.1907844082
Short name T782
Test name
Test status
Simulation time 507112837 ps
CPU time 4.49 seconds
Started Apr 18 03:39:56 PM PDT 24
Finished Apr 18 03:40:02 PM PDT 24
Peak memory 241852 kb
Host smart-771f73e7-1cc2-4c01-be25-330da08c9dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907844082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.1907844082
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.1041527994
Short name T209
Test name
Test status
Simulation time 4075434798 ps
CPU time 36 seconds
Started Apr 18 03:39:55 PM PDT 24
Finished Apr 18 03:40:32 PM PDT 24
Peak memory 256904 kb
Host smart-b507e357-6bc7-4bf0-b1dc-808cd2a593c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041527994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.1041527994
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.4186320783
Short name T561
Test name
Test status
Simulation time 1084750528 ps
CPU time 30.15 seconds
Started Apr 18 03:39:55 PM PDT 24
Finished Apr 18 03:40:25 PM PDT 24
Peak memory 242784 kb
Host smart-cc616f03-6382-4f50-a1e7-f547a4e25aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186320783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.4186320783
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.3753735878
Short name T889
Test name
Test status
Simulation time 322070897 ps
CPU time 6.29 seconds
Started Apr 18 03:39:56 PM PDT 24
Finished Apr 18 03:40:03 PM PDT 24
Peak memory 241660 kb
Host smart-285588e4-1bb6-466a-b0b3-b0c223a79923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753735878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.3753735878
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.177750763
Short name T242
Test name
Test status
Simulation time 622375833 ps
CPU time 15.14 seconds
Started Apr 18 03:39:55 PM PDT 24
Finished Apr 18 03:40:10 PM PDT 24
Peak memory 241800 kb
Host smart-6e6124fa-9eca-4ab6-bcf2-5ab5146b224c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=177750763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.177750763
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.47522677
Short name T689
Test name
Test status
Simulation time 1032718394 ps
CPU time 12.15 seconds
Started Apr 18 03:39:56 PM PDT 24
Finished Apr 18 03:40:09 PM PDT 24
Peak memory 241840 kb
Host smart-17a166c4-b9a6-4cf9-8748-40b8344eafe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=47522677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.47522677
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.3407653821
Short name T980
Test name
Test status
Simulation time 486617172 ps
CPU time 6.98 seconds
Started Apr 18 03:40:01 PM PDT 24
Finished Apr 18 03:40:08 PM PDT 24
Peak memory 241860 kb
Host smart-0c475395-be29-4944-8626-1b7b7117ba6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407653821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.3407653821
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.1324673746
Short name T640
Test name
Test status
Simulation time 553975682586 ps
CPU time 1400.25 seconds
Started Apr 18 03:39:55 PM PDT 24
Finished Apr 18 04:03:16 PM PDT 24
Peak memory 289212 kb
Host smart-3a985eb4-b4da-4506-aa9f-98aae5ec74c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324673746 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.1324673746
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.2848755065
Short name T541
Test name
Test status
Simulation time 1134820613 ps
CPU time 15.4 seconds
Started Apr 18 03:39:55 PM PDT 24
Finished Apr 18 03:40:11 PM PDT 24
Peak memory 242080 kb
Host smart-bee1fdda-47fe-4c73-b1fe-c9352acc7356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848755065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.2848755065
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.4025222863
Short name T8
Test name
Test status
Simulation time 335760982 ps
CPU time 3.97 seconds
Started Apr 18 03:46:10 PM PDT 24
Finished Apr 18 03:46:15 PM PDT 24
Peak memory 241812 kb
Host smart-50d0864a-0467-41e2-9dd0-e2b15c7ac7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025222863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.4025222863
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.3108329979
Short name T40
Test name
Test status
Simulation time 290639897 ps
CPU time 4.35 seconds
Started Apr 18 03:46:15 PM PDT 24
Finished Apr 18 03:46:20 PM PDT 24
Peak memory 241988 kb
Host smart-a6d977b3-3b52-40af-ae5c-015daee20736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108329979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3108329979
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.1446060803
Short name T661
Test name
Test status
Simulation time 3281647881 ps
CPU time 10.62 seconds
Started Apr 18 03:46:12 PM PDT 24
Finished Apr 18 03:46:23 PM PDT 24
Peak memory 242256 kb
Host smart-63c76e09-456f-4b16-ab8e-e29c378a002f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446060803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.1446060803
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.959988928
Short name T428
Test name
Test status
Simulation time 141610835 ps
CPU time 4.78 seconds
Started Apr 18 03:46:17 PM PDT 24
Finished Apr 18 03:46:23 PM PDT 24
Peak memory 241832 kb
Host smart-e03a54a9-06d8-451a-ae97-1b3a1ed9b600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959988928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.959988928
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.3504173774
Short name T330
Test name
Test status
Simulation time 517343330 ps
CPU time 7.86 seconds
Started Apr 18 03:46:16 PM PDT 24
Finished Apr 18 03:46:25 PM PDT 24
Peak memory 241760 kb
Host smart-5432bd68-f1bf-49cc-a344-fcb9f79d6a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504173774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.3504173774
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.2343498301
Short name T791
Test name
Test status
Simulation time 146546465 ps
CPU time 4.24 seconds
Started Apr 18 03:46:15 PM PDT 24
Finished Apr 18 03:46:20 PM PDT 24
Peak memory 242096 kb
Host smart-4dc0f87d-bc5e-4a29-b45e-ba2b94ccf972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343498301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.2343498301
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.3847075118
Short name T1050
Test name
Test status
Simulation time 732131202 ps
CPU time 6.74 seconds
Started Apr 18 03:46:28 PM PDT 24
Finished Apr 18 03:46:36 PM PDT 24
Peak memory 242024 kb
Host smart-e53f68f9-71ee-454a-8811-6bd716975b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847075118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.3847075118
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.384086677
Short name T1032
Test name
Test status
Simulation time 358953880 ps
CPU time 4.72 seconds
Started Apr 18 03:46:19 PM PDT 24
Finished Apr 18 03:46:24 PM PDT 24
Peak memory 242076 kb
Host smart-705d3642-cafb-4f5a-96f5-d83b6bd92097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384086677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.384086677
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.172193343
Short name T832
Test name
Test status
Simulation time 346501326 ps
CPU time 8.09 seconds
Started Apr 18 03:46:28 PM PDT 24
Finished Apr 18 03:46:37 PM PDT 24
Peak memory 241820 kb
Host smart-c954beb1-657c-4d3a-8dc9-d59b7f5c68ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172193343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.172193343
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.1572176684
Short name T226
Test name
Test status
Simulation time 403755525 ps
CPU time 3.96 seconds
Started Apr 18 03:46:18 PM PDT 24
Finished Apr 18 03:46:22 PM PDT 24
Peak memory 241804 kb
Host smart-c4bc877a-0c94-4801-8412-40a3fd15a172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572176684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.1572176684
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.3919584439
Short name T459
Test name
Test status
Simulation time 113440805 ps
CPU time 3.34 seconds
Started Apr 18 03:46:24 PM PDT 24
Finished Apr 18 03:46:28 PM PDT 24
Peak memory 242028 kb
Host smart-c637a1fb-e261-4842-95cc-9f2823155fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919584439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3919584439
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.1912369664
Short name T717
Test name
Test status
Simulation time 196198154 ps
CPU time 4.95 seconds
Started Apr 18 03:46:15 PM PDT 24
Finished Apr 18 03:46:20 PM PDT 24
Peak memory 241888 kb
Host smart-575549fc-59bf-4a0b-af0f-f4294cde1d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912369664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.1912369664
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.325874792
Short name T573
Test name
Test status
Simulation time 246347880 ps
CPU time 4.8 seconds
Started Apr 18 03:46:28 PM PDT 24
Finished Apr 18 03:46:34 PM PDT 24
Peak memory 242032 kb
Host smart-e6b2e599-b3ff-40d6-8526-885f1f9d9fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325874792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.325874792
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.2807024266
Short name T816
Test name
Test status
Simulation time 3063352931 ps
CPU time 29.72 seconds
Started Apr 18 03:46:20 PM PDT 24
Finished Apr 18 03:46:50 PM PDT 24
Peak memory 241836 kb
Host smart-5888155e-2f36-40d0-91b1-537992a69b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807024266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.2807024266
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.1548412275
Short name T985
Test name
Test status
Simulation time 1459613791 ps
CPU time 4.66 seconds
Started Apr 18 03:46:28 PM PDT 24
Finished Apr 18 03:46:34 PM PDT 24
Peak memory 241860 kb
Host smart-de1aa782-ecec-4d8d-bd26-418d3bf66033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548412275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.1548412275
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.2371906609
Short name T10
Test name
Test status
Simulation time 1142187309 ps
CPU time 9.48 seconds
Started Apr 18 03:46:20 PM PDT 24
Finished Apr 18 03:46:30 PM PDT 24
Peak memory 241768 kb
Host smart-5bbd1b3b-8681-419b-a879-c207861dda84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371906609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.2371906609
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.1049959528
Short name T214
Test name
Test status
Simulation time 171518152 ps
CPU time 3.85 seconds
Started Apr 18 03:46:43 PM PDT 24
Finished Apr 18 03:46:47 PM PDT 24
Peak memory 241960 kb
Host smart-7ff9560b-f12d-4c33-9f58-14c3d7a1591f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049959528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.1049959528
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.585376782
Short name T233
Test name
Test status
Simulation time 136480656 ps
CPU time 3.67 seconds
Started Apr 18 03:46:28 PM PDT 24
Finished Apr 18 03:46:33 PM PDT 24
Peak memory 241704 kb
Host smart-6cba3529-bb3d-44aa-9e72-175dec084fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585376782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.585376782
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.2608281203
Short name T1093
Test name
Test status
Simulation time 147172230 ps
CPU time 2.51 seconds
Started Apr 18 03:40:11 PM PDT 24
Finished Apr 18 03:40:14 PM PDT 24
Peak memory 240612 kb
Host smart-588f40f5-ccab-4d3c-82b1-3e44c0266482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608281203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.2608281203
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.1046616545
Short name T765
Test name
Test status
Simulation time 691888662 ps
CPU time 11.57 seconds
Started Apr 18 03:40:05 PM PDT 24
Finished Apr 18 03:40:17 PM PDT 24
Peak memory 241932 kb
Host smart-b6219094-c1e7-4a74-b47b-bf6c05c6f9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046616545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.1046616545
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.4256093426
Short name T335
Test name
Test status
Simulation time 1127421518 ps
CPU time 17.62 seconds
Started Apr 18 03:40:05 PM PDT 24
Finished Apr 18 03:40:23 PM PDT 24
Peak memory 241700 kb
Host smart-d0ad37d4-9b62-4870-8b66-b07b34d07fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256093426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.4256093426
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.2583587188
Short name T1
Test name
Test status
Simulation time 839764163 ps
CPU time 6.88 seconds
Started Apr 18 03:39:59 PM PDT 24
Finished Apr 18 03:40:06 PM PDT 24
Peak memory 248672 kb
Host smart-2ab25b19-46de-4c48-800b-3c485d89e325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583587188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.2583587188
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.1748301649
Short name T66
Test name
Test status
Simulation time 154582486 ps
CPU time 3.94 seconds
Started Apr 18 03:40:03 PM PDT 24
Finished Apr 18 03:40:08 PM PDT 24
Peak memory 241788 kb
Host smart-29d89e2b-5335-4a13-9be7-5e5598150c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748301649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.1748301649
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.3507281768
Short name T594
Test name
Test status
Simulation time 552824832 ps
CPU time 6.27 seconds
Started Apr 18 03:40:06 PM PDT 24
Finished Apr 18 03:40:12 PM PDT 24
Peak memory 242272 kb
Host smart-ad5b97d4-d3a9-4072-8cda-262d7733cf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507281768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.3507281768
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.2688802171
Short name T524
Test name
Test status
Simulation time 1514417633 ps
CPU time 17.53 seconds
Started Apr 18 03:40:04 PM PDT 24
Finished Apr 18 03:40:22 PM PDT 24
Peak memory 242064 kb
Host smart-b012c57d-192a-49a5-bac1-6628ccac180c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688802171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.2688802171
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.2325076495
Short name T532
Test name
Test status
Simulation time 1091432535 ps
CPU time 24.64 seconds
Started Apr 18 03:40:04 PM PDT 24
Finished Apr 18 03:40:29 PM PDT 24
Peak memory 241708 kb
Host smart-5c2354da-0ae2-44c5-bc6a-e73b27619948
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325076495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2325076495
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.3869144552
Short name T112
Test name
Test status
Simulation time 475837895 ps
CPU time 6.25 seconds
Started Apr 18 03:40:04 PM PDT 24
Finished Apr 18 03:40:11 PM PDT 24
Peak memory 241732 kb
Host smart-6983d9a5-8135-4c4f-ae0d-5e23fe043e91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3869144552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.3869144552
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.4055837998
Short name T404
Test name
Test status
Simulation time 565303687 ps
CPU time 7.14 seconds
Started Apr 18 03:40:04 PM PDT 24
Finished Apr 18 03:40:12 PM PDT 24
Peak memory 241820 kb
Host smart-f33e5d7a-5f1c-4c7d-968b-734128dd6ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055837998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.4055837998
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.3785271403
Short name T549
Test name
Test status
Simulation time 3502202259 ps
CPU time 113.94 seconds
Started Apr 18 03:40:13 PM PDT 24
Finished Apr 18 03:42:08 PM PDT 24
Peak memory 244440 kb
Host smart-ffcac3f8-f875-4edc-b1cc-dd37b6646649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785271403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.3785271403
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.3989542679
Short name T948
Test name
Test status
Simulation time 1288556343019 ps
CPU time 2133.99 seconds
Started Apr 18 03:40:04 PM PDT 24
Finished Apr 18 04:15:39 PM PDT 24
Peak memory 458204 kb
Host smart-1e0b56a4-72ca-41bc-8bdc-08f1b44fbf73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989542679 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.3989542679
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.1651155836
Short name T842
Test name
Test status
Simulation time 14051007567 ps
CPU time 39.38 seconds
Started Apr 18 03:40:06 PM PDT 24
Finished Apr 18 03:40:46 PM PDT 24
Peak memory 242400 kb
Host smart-731d4c74-2c74-46be-8911-60a8ea354ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651155836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.1651155836
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.156230984
Short name T794
Test name
Test status
Simulation time 287107774 ps
CPU time 3.89 seconds
Started Apr 18 03:46:23 PM PDT 24
Finished Apr 18 03:46:27 PM PDT 24
Peak memory 241824 kb
Host smart-0cae5ff5-a8ae-4cd6-bed3-465b509ed8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156230984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.156230984
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.2498853787
Short name T1002
Test name
Test status
Simulation time 3344194142 ps
CPU time 19.04 seconds
Started Apr 18 03:46:16 PM PDT 24
Finished Apr 18 03:46:36 PM PDT 24
Peak memory 241740 kb
Host smart-28210537-c2bb-490d-aa2d-ea9ddb2470bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498853787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.2498853787
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.2489020337
Short name T698
Test name
Test status
Simulation time 5921210588 ps
CPU time 11.35 seconds
Started Apr 18 03:46:29 PM PDT 24
Finished Apr 18 03:46:41 PM PDT 24
Peak memory 241916 kb
Host smart-827b8fc9-d256-4049-80fa-238b6ad92191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489020337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2489020337
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.2512820551
Short name T736
Test name
Test status
Simulation time 93564287 ps
CPU time 3.6 seconds
Started Apr 18 03:46:21 PM PDT 24
Finished Apr 18 03:46:25 PM PDT 24
Peak memory 241820 kb
Host smart-12c15541-0854-4344-a0a4-21cab3c5c27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512820551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2512820551
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.2182330137
Short name T446
Test name
Test status
Simulation time 754195877 ps
CPU time 5.2 seconds
Started Apr 18 03:46:24 PM PDT 24
Finished Apr 18 03:46:30 PM PDT 24
Peak memory 242216 kb
Host smart-f714feea-9d5b-4733-af55-f68823947bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182330137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.2182330137
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.1275618699
Short name T443
Test name
Test status
Simulation time 154140846 ps
CPU time 4.48 seconds
Started Apr 18 03:46:28 PM PDT 24
Finished Apr 18 03:46:34 PM PDT 24
Peak memory 241880 kb
Host smart-a1a7d035-cde5-475c-a51b-f0f063cb1725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275618699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.1275618699
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.1771436128
Short name T203
Test name
Test status
Simulation time 1204670690 ps
CPU time 9.79 seconds
Started Apr 18 03:46:24 PM PDT 24
Finished Apr 18 03:46:35 PM PDT 24
Peak memory 242104 kb
Host smart-2259eb45-0a23-4297-b149-c4327ee799c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771436128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.1771436128
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.359061693
Short name T647
Test name
Test status
Simulation time 408706472 ps
CPU time 4.86 seconds
Started Apr 18 03:46:18 PM PDT 24
Finished Apr 18 03:46:23 PM PDT 24
Peak memory 241760 kb
Host smart-c5b8172b-7bc7-4775-b480-7277a23fd12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359061693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.359061693
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.3267434829
Short name T768
Test name
Test status
Simulation time 773438401 ps
CPU time 10.67 seconds
Started Apr 18 03:46:21 PM PDT 24
Finished Apr 18 03:46:32 PM PDT 24
Peak memory 242156 kb
Host smart-f3ecd3fa-cd72-4052-bb90-7a60beaeae31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267434829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.3267434829
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.1351763355
Short name T737
Test name
Test status
Simulation time 113514892 ps
CPU time 4.1 seconds
Started Apr 18 03:46:23 PM PDT 24
Finished Apr 18 03:46:27 PM PDT 24
Peak memory 241924 kb
Host smart-a8d38841-47be-43ec-bfda-51eec4f073ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351763355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.1351763355
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.1084866684
Short name T682
Test name
Test status
Simulation time 1763279039 ps
CPU time 12.2 seconds
Started Apr 18 03:46:25 PM PDT 24
Finished Apr 18 03:46:38 PM PDT 24
Peak memory 242036 kb
Host smart-e41a5ac7-05e7-4ce2-9eef-1bf2ab0f21e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084866684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.1084866684
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.3979794983
Short name T188
Test name
Test status
Simulation time 471222045 ps
CPU time 5.34 seconds
Started Apr 18 03:46:23 PM PDT 24
Finished Apr 18 03:46:28 PM PDT 24
Peak memory 242088 kb
Host smart-6e2d4577-3496-4c89-9ff4-54e83d38e60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979794983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.3979794983
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.1395068619
Short name T742
Test name
Test status
Simulation time 382167952 ps
CPU time 6.15 seconds
Started Apr 18 03:46:24 PM PDT 24
Finished Apr 18 03:46:30 PM PDT 24
Peak memory 241672 kb
Host smart-3e6a5df3-27fe-4d98-bdab-965cfb159c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395068619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.1395068619
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.1266196125
Short name T509
Test name
Test status
Simulation time 143733966 ps
CPU time 4.04 seconds
Started Apr 18 03:46:27 PM PDT 24
Finished Apr 18 03:46:32 PM PDT 24
Peak memory 242168 kb
Host smart-0913f4d2-f227-4c79-a8d5-cd5c5fa307ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266196125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.1266196125
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.3808078461
Short name T583
Test name
Test status
Simulation time 1322928987 ps
CPU time 12.76 seconds
Started Apr 18 03:46:22 PM PDT 24
Finished Apr 18 03:46:35 PM PDT 24
Peak memory 242140 kb
Host smart-ca70e0fa-2ed5-4a3e-9e8c-7e64967e8117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808078461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.3808078461
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.1061500638
Short name T222
Test name
Test status
Simulation time 277998909 ps
CPU time 3.77 seconds
Started Apr 18 03:46:32 PM PDT 24
Finished Apr 18 03:46:36 PM PDT 24
Peak memory 241780 kb
Host smart-b84ca4b0-d81e-4528-9d67-c7441695ec3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061500638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1061500638
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.529027462
Short name T1094
Test name
Test status
Simulation time 379322403 ps
CPU time 5.22 seconds
Started Apr 18 03:46:32 PM PDT 24
Finished Apr 18 03:46:38 PM PDT 24
Peak memory 241856 kb
Host smart-b0084e52-0a09-466d-9f6f-6d19a9ad8cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529027462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.529027462
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.2468560500
Short name T405
Test name
Test status
Simulation time 498829287 ps
CPU time 10.74 seconds
Started Apr 18 03:46:28 PM PDT 24
Finished Apr 18 03:46:40 PM PDT 24
Peak memory 242108 kb
Host smart-8864ba62-b4b8-4241-b609-44bf304439bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468560500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.2468560500
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.2036406881
Short name T519
Test name
Test status
Simulation time 707258136 ps
CPU time 2.63 seconds
Started Apr 18 03:37:00 PM PDT 24
Finished Apr 18 03:37:03 PM PDT 24
Peak memory 240084 kb
Host smart-c1a6e184-6c97-4809-9210-9533fc91563f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036406881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2036406881
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.1781357813
Short name T1090
Test name
Test status
Simulation time 713439012 ps
CPU time 20.21 seconds
Started Apr 18 03:36:49 PM PDT 24
Finished Apr 18 03:37:10 PM PDT 24
Peak memory 241788 kb
Host smart-d612ab58-2857-4345-bf6b-a2ad91977db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781357813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1781357813
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.4157276569
Short name T634
Test name
Test status
Simulation time 10660644292 ps
CPU time 20.61 seconds
Started Apr 18 03:37:10 PM PDT 24
Finished Apr 18 03:37:31 PM PDT 24
Peak memory 248736 kb
Host smart-55e98324-4efb-41ee-b89e-27567a231841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157276569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.4157276569
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.418423242
Short name T612
Test name
Test status
Simulation time 3752274876 ps
CPU time 40.71 seconds
Started Apr 18 03:36:53 PM PDT 24
Finished Apr 18 03:37:35 PM PDT 24
Peak memory 248796 kb
Host smart-c114a65a-219f-4349-84e5-36c4316615a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418423242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.418423242
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.1863995476
Short name T614
Test name
Test status
Simulation time 1347691393 ps
CPU time 13.4 seconds
Started Apr 18 03:36:49 PM PDT 24
Finished Apr 18 03:37:03 PM PDT 24
Peak memory 241856 kb
Host smart-4eda80ad-58fa-4393-a61a-f7690d8b0b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863995476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.1863995476
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.1082863079
Short name T834
Test name
Test status
Simulation time 434028168 ps
CPU time 9.17 seconds
Started Apr 18 03:36:50 PM PDT 24
Finished Apr 18 03:36:59 PM PDT 24
Peak memory 241780 kb
Host smart-156a322b-5afe-4324-bd3e-df6ba3791830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082863079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.1082863079
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.2393011610
Short name T679
Test name
Test status
Simulation time 1748464308 ps
CPU time 16.13 seconds
Started Apr 18 03:36:54 PM PDT 24
Finished Apr 18 03:37:11 PM PDT 24
Peak memory 242064 kb
Host smart-31cba219-9c1b-44e8-831d-a778cd4c6f26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2393011610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.2393011610
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.1765084946
Short name T1127
Test name
Test status
Simulation time 310401779 ps
CPU time 10.81 seconds
Started Apr 18 03:36:55 PM PDT 24
Finished Apr 18 03:37:07 PM PDT 24
Peak memory 242184 kb
Host smart-5a1062f1-b62f-440d-9e79-2f56b91703e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1765084946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.1765084946
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.928441304
Short name T23
Test name
Test status
Simulation time 37833394440 ps
CPU time 187.78 seconds
Started Apr 18 03:38:05 PM PDT 24
Finished Apr 18 03:41:13 PM PDT 24
Peak memory 264304 kb
Host smart-b5036ea9-346e-4b78-ae1e-4e522fd1c153
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928441304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.928441304
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.1689949751
Short name T934
Test name
Test status
Simulation time 330223417 ps
CPU time 7.17 seconds
Started Apr 18 03:36:46 PM PDT 24
Finished Apr 18 03:36:53 PM PDT 24
Peak memory 242020 kb
Host smart-81da5db9-4bde-4184-826d-8aa7189f23fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689949751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1689949751
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.3235714953
Short name T951
Test name
Test status
Simulation time 13795251167 ps
CPU time 212.48 seconds
Started Apr 18 03:37:01 PM PDT 24
Finished Apr 18 03:40:34 PM PDT 24
Peak memory 261136 kb
Host smart-9c56d2a6-cb29-4bef-92ef-c3a005936ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235714953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
3235714953
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.2083570246
Short name T276
Test name
Test status
Simulation time 466757838054 ps
CPU time 1007.91 seconds
Started Apr 18 03:36:55 PM PDT 24
Finished Apr 18 03:53:43 PM PDT 24
Peak memory 285896 kb
Host smart-c714f3e4-7b4e-4d03-b6d7-414b0aa432d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083570246 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.2083570246
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.4197856367
Short name T525
Test name
Test status
Simulation time 2413290368 ps
CPU time 25.22 seconds
Started Apr 18 03:36:55 PM PDT 24
Finished Apr 18 03:37:21 PM PDT 24
Peak memory 242036 kb
Host smart-fb95ffa2-1d03-435a-923e-2e1e16998af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197856367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.4197856367
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.1518294294
Short name T906
Test name
Test status
Simulation time 167488985 ps
CPU time 2.28 seconds
Started Apr 18 03:40:16 PM PDT 24
Finished Apr 18 03:40:19 PM PDT 24
Peak memory 240120 kb
Host smart-89176ad0-5ff4-4939-b07a-c6f5a8baee4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518294294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.1518294294
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.2228201802
Short name T996
Test name
Test status
Simulation time 175376144 ps
CPU time 2.67 seconds
Started Apr 18 03:40:17 PM PDT 24
Finished Apr 18 03:40:20 PM PDT 24
Peak memory 246368 kb
Host smart-f54ee912-9a93-4ae7-9ca1-bbb9b1d29d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228201802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.2228201802
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.347184223
Short name T1039
Test name
Test status
Simulation time 768744728 ps
CPU time 17.21 seconds
Started Apr 18 03:40:12 PM PDT 24
Finished Apr 18 03:40:29 PM PDT 24
Peak memory 241556 kb
Host smart-dd5cc7e8-c70b-48d0-871f-a92e11bd886a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347184223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.347184223
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.173678578
Short name T916
Test name
Test status
Simulation time 3160306111 ps
CPU time 34.18 seconds
Started Apr 18 03:40:10 PM PDT 24
Finished Apr 18 03:40:45 PM PDT 24
Peak memory 242864 kb
Host smart-b9645194-d113-4eca-937c-8bb2badd2fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173678578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.173678578
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.469860615
Short name T546
Test name
Test status
Simulation time 389227629 ps
CPU time 5.29 seconds
Started Apr 18 03:40:11 PM PDT 24
Finished Apr 18 03:40:17 PM PDT 24
Peak memory 241932 kb
Host smart-98c669d4-72f8-4a1f-af63-d703828c03ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469860615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.469860615
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.434942266
Short name T1172
Test name
Test status
Simulation time 927011335 ps
CPU time 9.08 seconds
Started Apr 18 03:40:16 PM PDT 24
Finished Apr 18 03:40:26 PM PDT 24
Peak memory 242248 kb
Host smart-ba8c87f6-a897-4d2d-8a77-197a5b6c50ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434942266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.434942266
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.397388485
Short name T29
Test name
Test status
Simulation time 620792870 ps
CPU time 9.5 seconds
Started Apr 18 03:40:16 PM PDT 24
Finished Apr 18 03:40:26 PM PDT 24
Peak memory 248652 kb
Host smart-ed38a4ea-dbe2-40db-afb1-8cadcb946642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397388485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.397388485
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.1644429195
Short name T329
Test name
Test status
Simulation time 2958913996 ps
CPU time 12.83 seconds
Started Apr 18 03:40:10 PM PDT 24
Finished Apr 18 03:40:23 PM PDT 24
Peak memory 241880 kb
Host smart-0549872f-de5a-45a2-ac49-9e4548a34929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644429195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.1644429195
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.3625914447
Short name T1182
Test name
Test status
Simulation time 507143271 ps
CPU time 17.91 seconds
Started Apr 18 03:40:12 PM PDT 24
Finished Apr 18 03:40:30 PM PDT 24
Peak memory 241668 kb
Host smart-6173cd06-edca-43a9-8b1e-12b88eb24c1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625914447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.3625914447
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.3894912032
Short name T437
Test name
Test status
Simulation time 436404707 ps
CPU time 5.14 seconds
Started Apr 18 03:40:16 PM PDT 24
Finished Apr 18 03:40:21 PM PDT 24
Peak memory 241752 kb
Host smart-3a9a1b43-3ca9-4130-a6c8-547ecd2e54bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3894912032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.3894912032
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.1412594856
Short name T388
Test name
Test status
Simulation time 667212146 ps
CPU time 9.66 seconds
Started Apr 18 03:40:14 PM PDT 24
Finished Apr 18 03:40:24 PM PDT 24
Peak memory 248556 kb
Host smart-462cf86f-2727-4a55-b27e-51c4d92b32c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412594856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.1412594856
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.997751927
Short name T481
Test name
Test status
Simulation time 1180629041 ps
CPU time 26.69 seconds
Started Apr 18 03:40:15 PM PDT 24
Finished Apr 18 03:40:42 PM PDT 24
Peak memory 243616 kb
Host smart-b6e09f25-61c7-430b-b2a1-4bced2492878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997751927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.
997751927
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.2018944757
Short name T292
Test name
Test status
Simulation time 55765176320 ps
CPU time 1182.92 seconds
Started Apr 18 03:40:17 PM PDT 24
Finished Apr 18 04:00:01 PM PDT 24
Peak memory 289060 kb
Host smart-fc3ec1f1-5e3e-48d7-a578-9035f484ead5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018944757 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.2018944757
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.3686164925
Short name T1109
Test name
Test status
Simulation time 6446359567 ps
CPU time 35.56 seconds
Started Apr 18 03:40:16 PM PDT 24
Finished Apr 18 03:40:53 PM PDT 24
Peak memory 243516 kb
Host smart-0ac11594-a585-4d98-b0d0-4fd18f9b43d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686164925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.3686164925
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.3676669425
Short name T907
Test name
Test status
Simulation time 556908622 ps
CPU time 4.6 seconds
Started Apr 18 03:46:32 PM PDT 24
Finished Apr 18 03:46:37 PM PDT 24
Peak memory 241900 kb
Host smart-6c8bf888-6a24-45f4-8858-1f3cbcaf6b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676669425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.3676669425
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.13903053
Short name T569
Test name
Test status
Simulation time 298194207 ps
CPU time 3.71 seconds
Started Apr 18 03:46:25 PM PDT 24
Finished Apr 18 03:46:29 PM PDT 24
Peak memory 241760 kb
Host smart-7d24bcf9-6a32-4a28-8d50-05e814b1ac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13903053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.13903053
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.1705519877
Short name T831
Test name
Test status
Simulation time 365884600 ps
CPU time 4.43 seconds
Started Apr 18 03:46:25 PM PDT 24
Finished Apr 18 03:46:30 PM PDT 24
Peak memory 241860 kb
Host smart-a767830a-3a29-4de1-aa44-e7b74b5a36c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705519877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.1705519877
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.1619978183
Short name T56
Test name
Test status
Simulation time 144497156 ps
CPU time 4.79 seconds
Started Apr 18 03:46:24 PM PDT 24
Finished Apr 18 03:46:30 PM PDT 24
Peak memory 242152 kb
Host smart-75c2d308-4bb0-474b-9274-acba3e84016f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619978183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.1619978183
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.1949111534
Short name T849
Test name
Test status
Simulation time 1429359389 ps
CPU time 4.73 seconds
Started Apr 18 03:46:25 PM PDT 24
Finished Apr 18 03:46:30 PM PDT 24
Peak memory 241800 kb
Host smart-ed49d21d-32ea-47bd-ad5a-8d39473cca5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949111534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.1949111534
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.3691839443
Short name T844
Test name
Test status
Simulation time 1949843516 ps
CPU time 6.39 seconds
Started Apr 18 03:46:25 PM PDT 24
Finished Apr 18 03:46:32 PM PDT 24
Peak memory 241728 kb
Host smart-4a94245b-2b8d-4e85-9d4c-20b4b2630149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691839443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.3691839443
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.3575502968
Short name T517
Test name
Test status
Simulation time 1928215724 ps
CPU time 6.81 seconds
Started Apr 18 03:46:27 PM PDT 24
Finished Apr 18 03:46:34 PM PDT 24
Peak memory 241896 kb
Host smart-858e40e4-4885-40b3-a357-c4dca910647e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575502968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3575502968
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.3114780201
Short name T1194
Test name
Test status
Simulation time 2828095702 ps
CPU time 5.71 seconds
Started Apr 18 03:46:30 PM PDT 24
Finished Apr 18 03:46:36 PM PDT 24
Peak memory 241956 kb
Host smart-b92db102-cc44-4628-b4ca-40182051b8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114780201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3114780201
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.3803403908
Short name T758
Test name
Test status
Simulation time 216267126 ps
CPU time 2.23 seconds
Started Apr 18 03:40:25 PM PDT 24
Finished Apr 18 03:40:28 PM PDT 24
Peak memory 240136 kb
Host smart-4a1d473f-2744-463a-8d5a-821b921da8ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803403908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.3803403908
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.3137259875
Short name T821
Test name
Test status
Simulation time 973210534 ps
CPU time 20.61 seconds
Started Apr 18 03:40:25 PM PDT 24
Finished Apr 18 03:40:47 PM PDT 24
Peak memory 248720 kb
Host smart-b63455fc-fc54-46cb-a5d2-009f2cac66fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137259875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.3137259875
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.3939718165
Short name T848
Test name
Test status
Simulation time 1065094491 ps
CPU time 24.81 seconds
Started Apr 18 03:40:24 PM PDT 24
Finished Apr 18 03:40:50 PM PDT 24
Peak memory 242072 kb
Host smart-6ca37bc1-48ca-444e-87f1-33eed6631ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939718165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3939718165
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.543220742
Short name T856
Test name
Test status
Simulation time 13342912585 ps
CPU time 34.13 seconds
Started Apr 18 03:40:25 PM PDT 24
Finished Apr 18 03:40:59 PM PDT 24
Peak memory 242520 kb
Host smart-b6a37550-0c1f-414e-932b-5cb72abdead1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543220742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.543220742
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.4193363220
Short name T199
Test name
Test status
Simulation time 122092314 ps
CPU time 3.98 seconds
Started Apr 18 03:40:17 PM PDT 24
Finished Apr 18 03:40:21 PM PDT 24
Peak memory 241924 kb
Host smart-d9080240-efb2-47fd-85f8-2dabd3862a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193363220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.4193363220
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.1067207603
Short name T197
Test name
Test status
Simulation time 1839938895 ps
CPU time 28.44 seconds
Started Apr 18 03:40:24 PM PDT 24
Finished Apr 18 03:40:53 PM PDT 24
Peak memory 248752 kb
Host smart-81712a3e-e13c-4d20-a0a8-c9d61ff9ac88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067207603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.1067207603
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.2954157256
Short name T371
Test name
Test status
Simulation time 19470630821 ps
CPU time 47.74 seconds
Started Apr 18 03:40:24 PM PDT 24
Finished Apr 18 03:41:12 PM PDT 24
Peak memory 243220 kb
Host smart-a9fb7073-5c53-4c17-b277-1526d57f61ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954157256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.2954157256
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.2967590530
Short name T228
Test name
Test status
Simulation time 763267185 ps
CPU time 7.67 seconds
Started Apr 18 03:40:24 PM PDT 24
Finished Apr 18 03:40:32 PM PDT 24
Peak memory 241656 kb
Host smart-56bb55dc-1847-47af-8dc3-e8a000a0fe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967590530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.2967590530
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.4270311944
Short name T1081
Test name
Test status
Simulation time 353856790 ps
CPU time 10.53 seconds
Started Apr 18 03:40:16 PM PDT 24
Finished Apr 18 03:40:27 PM PDT 24
Peak memory 241828 kb
Host smart-7f0fd626-1e9a-4e18-8ef4-3725bb27a8a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270311944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.4270311944
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.3105272993
Short name T828
Test name
Test status
Simulation time 141207012 ps
CPU time 4.45 seconds
Started Apr 18 03:40:24 PM PDT 24
Finished Apr 18 03:40:29 PM PDT 24
Peak memory 241920 kb
Host smart-3b6aac2c-f241-4bbd-bc13-9f3903e0d047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3105272993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.3105272993
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.3883730257
Short name T1121
Test name
Test status
Simulation time 286633307 ps
CPU time 9.77 seconds
Started Apr 18 03:40:15 PM PDT 24
Finished Apr 18 03:40:26 PM PDT 24
Peak memory 241912 kb
Host smart-54bbf5f9-97b0-4f02-bdf2-028f55f6aa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883730257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.3883730257
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.482650966
Short name T458
Test name
Test status
Simulation time 8404573563 ps
CPU time 95.9 seconds
Started Apr 18 03:40:23 PM PDT 24
Finished Apr 18 03:41:59 PM PDT 24
Peak memory 248840 kb
Host smart-93806569-4d86-4481-ac00-5587068fd802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482650966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.
482650966
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.1223990801
Short name T245
Test name
Test status
Simulation time 80026797315 ps
CPU time 1236.28 seconds
Started Apr 18 03:40:24 PM PDT 24
Finished Apr 18 04:01:01 PM PDT 24
Peak memory 308476 kb
Host smart-c310a972-2560-44aa-b74e-54edb6d623a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223990801 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.1223990801
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.976466130
Short name T104
Test name
Test status
Simulation time 1694038276 ps
CPU time 17.71 seconds
Started Apr 18 03:40:25 PM PDT 24
Finished Apr 18 03:40:44 PM PDT 24
Peak memory 242160 kb
Host smart-f8c9b45d-fb34-4fc0-b5af-27688fb43aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976466130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.976466130
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.3880712954
Short name T793
Test name
Test status
Simulation time 450621540 ps
CPU time 5.22 seconds
Started Apr 18 03:46:31 PM PDT 24
Finished Apr 18 03:46:37 PM PDT 24
Peak memory 242020 kb
Host smart-ce42c2bf-8af2-45e8-90d8-315aa7935e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880712954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.3880712954
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.2645124812
Short name T220
Test name
Test status
Simulation time 436879253 ps
CPU time 4.09 seconds
Started Apr 18 03:46:30 PM PDT 24
Finished Apr 18 03:46:34 PM PDT 24
Peak memory 241816 kb
Host smart-810e4ac5-79b7-4679-8d1e-f076543c3757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645124812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2645124812
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.1247616175
Short name T491
Test name
Test status
Simulation time 126369857 ps
CPU time 3.52 seconds
Started Apr 18 03:46:29 PM PDT 24
Finished Apr 18 03:46:33 PM PDT 24
Peak memory 242056 kb
Host smart-782d4b1f-6d96-4776-8fde-39abe0e18127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247616175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.1247616175
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.2734281949
Short name T922
Test name
Test status
Simulation time 128070900 ps
CPU time 3.83 seconds
Started Apr 18 03:46:31 PM PDT 24
Finished Apr 18 03:46:35 PM PDT 24
Peak memory 241836 kb
Host smart-3121a421-4969-4233-a910-03185a458140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734281949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.2734281949
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.2201948519
Short name T449
Test name
Test status
Simulation time 366808644 ps
CPU time 4.47 seconds
Started Apr 18 03:46:31 PM PDT 24
Finished Apr 18 03:46:36 PM PDT 24
Peak memory 241816 kb
Host smart-c77693f6-b6a3-4c47-9c3c-179d981cc91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201948519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.2201948519
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.3445562722
Short name T708
Test name
Test status
Simulation time 2630534605 ps
CPU time 8.24 seconds
Started Apr 18 03:46:28 PM PDT 24
Finished Apr 18 03:46:37 PM PDT 24
Peak memory 241980 kb
Host smart-03a2b444-bf09-4aa5-a1f5-75f202b608f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445562722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.3445562722
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.1191717226
Short name T903
Test name
Test status
Simulation time 535760124 ps
CPU time 5.38 seconds
Started Apr 18 03:46:32 PM PDT 24
Finished Apr 18 03:46:38 PM PDT 24
Peak memory 241944 kb
Host smart-aa3d5536-0401-43ff-b960-de3a9523068e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191717226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.1191717226
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.2255431465
Short name T1034
Test name
Test status
Simulation time 123886373 ps
CPU time 4.88 seconds
Started Apr 18 03:46:34 PM PDT 24
Finished Apr 18 03:46:39 PM PDT 24
Peak memory 242016 kb
Host smart-314c9dad-1374-4799-9195-defba36d0830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255431465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.2255431465
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.940480401
Short name T741
Test name
Test status
Simulation time 119567036 ps
CPU time 5.07 seconds
Started Apr 18 03:46:30 PM PDT 24
Finished Apr 18 03:46:36 PM PDT 24
Peak memory 242120 kb
Host smart-9d18d3a7-bdc0-4bb7-9aa4-5b33ed7ff152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940480401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.940480401
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.1771917232
Short name T693
Test name
Test status
Simulation time 60779408 ps
CPU time 1.81 seconds
Started Apr 18 03:40:30 PM PDT 24
Finished Apr 18 03:40:32 PM PDT 24
Peak memory 240096 kb
Host smart-8d022cd4-be64-4982-9b54-5872bb51ee64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771917232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.1771917232
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.3666119024
Short name T42
Test name
Test status
Simulation time 1001304480 ps
CPU time 6.79 seconds
Started Apr 18 03:40:25 PM PDT 24
Finished Apr 18 03:40:32 PM PDT 24
Peak memory 241904 kb
Host smart-899931f2-057d-43a2-9e8d-5fee23c1227f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666119024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.3666119024
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.2743111986
Short name T217
Test name
Test status
Simulation time 219137776 ps
CPU time 12.8 seconds
Started Apr 18 03:40:25 PM PDT 24
Finished Apr 18 03:40:38 PM PDT 24
Peak memory 241892 kb
Host smart-ba8c6cc9-ce42-42d5-a759-12bb14b3c1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743111986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.2743111986
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.1694724715
Short name T1007
Test name
Test status
Simulation time 2970485855 ps
CPU time 37.26 seconds
Started Apr 18 03:40:26 PM PDT 24
Finished Apr 18 03:41:04 PM PDT 24
Peak memory 241852 kb
Host smart-357bc838-b04e-4a80-a969-d0a6568d0cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694724715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.1694724715
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.4199780792
Short name T861
Test name
Test status
Simulation time 150258325 ps
CPU time 4.34 seconds
Started Apr 18 03:40:26 PM PDT 24
Finished Apr 18 03:40:31 PM PDT 24
Peak memory 241900 kb
Host smart-aef046b5-68bf-4e6d-b241-21039c6dbb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199780792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.4199780792
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.1525776539
Short name T198
Test name
Test status
Simulation time 17196387422 ps
CPU time 34.47 seconds
Started Apr 18 03:40:29 PM PDT 24
Finished Apr 18 03:41:04 PM PDT 24
Peak memory 262112 kb
Host smart-965199b8-adcc-433a-b004-00feed9f7034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525776539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.1525776539
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.3107819754
Short name T869
Test name
Test status
Simulation time 393064965 ps
CPU time 9.46 seconds
Started Apr 18 03:40:28 PM PDT 24
Finished Apr 18 03:40:38 PM PDT 24
Peak memory 241876 kb
Host smart-b2df2484-02e2-4fac-b6e4-eb5031c43678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107819754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.3107819754
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.1871659303
Short name T533
Test name
Test status
Simulation time 1974840617 ps
CPU time 5.06 seconds
Started Apr 18 03:40:29 PM PDT 24
Finished Apr 18 03:40:34 PM PDT 24
Peak memory 241856 kb
Host smart-995b6f41-aa03-48ba-b937-dbe79af14f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871659303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.1871659303
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.2791828409
Short name T932
Test name
Test status
Simulation time 576459869 ps
CPU time 17.66 seconds
Started Apr 18 03:40:25 PM PDT 24
Finished Apr 18 03:40:44 PM PDT 24
Peak memory 241960 kb
Host smart-a268886d-612b-40e0-a4cf-a6d78275682e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791828409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.2791828409
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.1284909396
Short name T411
Test name
Test status
Simulation time 104322805 ps
CPU time 4.97 seconds
Started Apr 18 03:40:26 PM PDT 24
Finished Apr 18 03:40:31 PM PDT 24
Peak memory 241724 kb
Host smart-ae688217-44df-4b09-8977-8c5fad55956e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1284909396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1284909396
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.739804819
Short name T633
Test name
Test status
Simulation time 1221058804 ps
CPU time 11.48 seconds
Started Apr 18 03:40:28 PM PDT 24
Finished Apr 18 03:40:39 PM PDT 24
Peak memory 242180 kb
Host smart-d3e2ed4f-354b-4cee-8fdc-616f556c2931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739804819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.739804819
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.2934510896
Short name T99
Test name
Test status
Simulation time 927187453 ps
CPU time 17.52 seconds
Started Apr 18 03:40:29 PM PDT 24
Finished Apr 18 03:40:47 PM PDT 24
Peak memory 241996 kb
Host smart-93e3b057-927e-418e-b2b4-03578aae5871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934510896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.2934510896
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.3883942903
Short name T454
Test name
Test status
Simulation time 374114465 ps
CPU time 4.14 seconds
Started Apr 18 03:46:28 PM PDT 24
Finished Apr 18 03:46:33 PM PDT 24
Peak memory 242120 kb
Host smart-e5f62215-7926-4543-a6bc-dcc0f2be5ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883942903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.3883942903
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.624966937
Short name T120
Test name
Test status
Simulation time 263189249 ps
CPU time 4.07 seconds
Started Apr 18 03:46:30 PM PDT 24
Finished Apr 18 03:46:34 PM PDT 24
Peak memory 242172 kb
Host smart-59aeb817-61dd-4ab1-9c52-e87dbf0adc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624966937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.624966937
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.537414807
Short name T1190
Test name
Test status
Simulation time 638523443 ps
CPU time 4.68 seconds
Started Apr 18 03:46:31 PM PDT 24
Finished Apr 18 03:46:36 PM PDT 24
Peak memory 241912 kb
Host smart-9606d9bb-9a1b-46d9-8bf1-fe618e9a8435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537414807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.537414807
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.2661447639
Short name T46
Test name
Test status
Simulation time 118589950 ps
CPU time 4.85 seconds
Started Apr 18 03:46:36 PM PDT 24
Finished Apr 18 03:46:42 PM PDT 24
Peak memory 241796 kb
Host smart-d37b00cf-6d7f-4f9e-ad1b-0892d286b5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661447639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.2661447639
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.1739099831
Short name T187
Test name
Test status
Simulation time 2316835449 ps
CPU time 6.76 seconds
Started Apr 18 03:46:34 PM PDT 24
Finished Apr 18 03:46:41 PM PDT 24
Peak memory 241880 kb
Host smart-ceaacade-87e7-4723-9237-ba0aeaae56e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739099831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.1739099831
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.3597819929
Short name T954
Test name
Test status
Simulation time 228382476 ps
CPU time 4.51 seconds
Started Apr 18 03:46:34 PM PDT 24
Finished Apr 18 03:46:39 PM PDT 24
Peak memory 241788 kb
Host smart-bcb927f2-1c71-4cdb-b407-d15820617659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597819929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.3597819929
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.3735526466
Short name T809
Test name
Test status
Simulation time 107095894 ps
CPU time 4.03 seconds
Started Apr 18 03:46:36 PM PDT 24
Finished Apr 18 03:46:41 PM PDT 24
Peak memory 241828 kb
Host smart-173970bd-d12c-432d-a95d-aee78d4f7e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735526466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.3735526466
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.1690581766
Short name T476
Test name
Test status
Simulation time 461018879 ps
CPU time 4.45 seconds
Started Apr 18 03:46:34 PM PDT 24
Finished Apr 18 03:46:39 PM PDT 24
Peak memory 242080 kb
Host smart-f04c5c50-a8b8-4bc9-8197-23d54f5f3b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690581766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.1690581766
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.2544383110
Short name T1125
Test name
Test status
Simulation time 294735267 ps
CPU time 3.78 seconds
Started Apr 18 03:46:36 PM PDT 24
Finished Apr 18 03:46:40 PM PDT 24
Peak memory 241848 kb
Host smart-c24b682a-e43c-48a2-a41d-2cf498df174c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544383110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.2544383110
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.2607838072
Short name T167
Test name
Test status
Simulation time 389969436 ps
CPU time 3.47 seconds
Started Apr 18 03:46:36 PM PDT 24
Finished Apr 18 03:46:39 PM PDT 24
Peak memory 242200 kb
Host smart-2f92cabe-d5fe-476d-83ce-2b91b2fed760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607838072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.2607838072
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.1883820274
Short name T704
Test name
Test status
Simulation time 147479804 ps
CPU time 2.17 seconds
Started Apr 18 03:40:34 PM PDT 24
Finished Apr 18 03:40:37 PM PDT 24
Peak memory 240356 kb
Host smart-4290642b-5659-4448-bde6-a8270358269e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883820274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.1883820274
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.2375383833
Short name T94
Test name
Test status
Simulation time 3096199278 ps
CPU time 28.77 seconds
Started Apr 18 03:40:31 PM PDT 24
Finished Apr 18 03:41:01 PM PDT 24
Peak memory 248608 kb
Host smart-df44c167-38ca-49ce-b671-37044591423d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375383833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.2375383833
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.1992804841
Short name T485
Test name
Test status
Simulation time 1066803549 ps
CPU time 21.6 seconds
Started Apr 18 03:40:34 PM PDT 24
Finished Apr 18 03:40:56 PM PDT 24
Peak memory 241824 kb
Host smart-555d8679-260a-47d5-bd6e-41f5c587b66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992804841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.1992804841
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.3141301735
Short name T618
Test name
Test status
Simulation time 814636954 ps
CPU time 18.32 seconds
Started Apr 18 03:40:31 PM PDT 24
Finished Apr 18 03:40:50 PM PDT 24
Peak memory 241804 kb
Host smart-4eb18efc-7c05-4e65-98c5-cd949e06fa65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141301735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.3141301735
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.2637765507
Short name T27
Test name
Test status
Simulation time 244051032 ps
CPU time 4.6 seconds
Started Apr 18 03:40:32 PM PDT 24
Finished Apr 18 03:40:37 PM PDT 24
Peak memory 241936 kb
Host smart-b4c70a9d-fc0f-4838-9ab5-a104be3d1bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637765507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.2637765507
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.4245317717
Short name T1120
Test name
Test status
Simulation time 2268488512 ps
CPU time 24.64 seconds
Started Apr 18 03:40:30 PM PDT 24
Finished Apr 18 03:40:55 PM PDT 24
Peak memory 244244 kb
Host smart-294f254c-b292-4e68-ae5d-07adeaebe310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245317717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.4245317717
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.622128974
Short name T1074
Test name
Test status
Simulation time 1311096689 ps
CPU time 17.43 seconds
Started Apr 18 03:40:31 PM PDT 24
Finished Apr 18 03:40:49 PM PDT 24
Peak memory 242676 kb
Host smart-5dc647c2-d654-480c-b146-73cf07fc08ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622128974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.622128974
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.893971783
Short name T778
Test name
Test status
Simulation time 874897464 ps
CPU time 16.27 seconds
Started Apr 18 03:40:31 PM PDT 24
Finished Apr 18 03:40:48 PM PDT 24
Peak memory 241596 kb
Host smart-ba979cc4-72e9-4714-8d65-a47510fc99a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893971783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.893971783
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.3553215133
Short name T1095
Test name
Test status
Simulation time 2987227679 ps
CPU time 27.17 seconds
Started Apr 18 03:40:30 PM PDT 24
Finished Apr 18 03:40:58 PM PDT 24
Peak memory 241848 kb
Host smart-d03e9b1a-b6a6-44f2-b6ad-f6c404810f10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3553215133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.3553215133
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.3495772013
Short name T366
Test name
Test status
Simulation time 588824032 ps
CPU time 10.58 seconds
Started Apr 18 03:40:35 PM PDT 24
Finished Apr 18 03:40:46 PM PDT 24
Peak memory 241856 kb
Host smart-46c284f5-c911-48d6-b764-850fb1d87c7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3495772013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.3495772013
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.2231997166
Short name T493
Test name
Test status
Simulation time 167971953 ps
CPU time 3.78 seconds
Started Apr 18 03:40:32 PM PDT 24
Finished Apr 18 03:40:36 PM PDT 24
Peak memory 241808 kb
Host smart-f5538f78-117a-492b-88c4-603879034c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231997166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.2231997166
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.3148320343
Short name T145
Test name
Test status
Simulation time 124896174044 ps
CPU time 317.49 seconds
Started Apr 18 03:40:38 PM PDT 24
Finished Apr 18 03:45:56 PM PDT 24
Peak memory 268620 kb
Host smart-68115cf6-7200-442e-95a7-7be846c5fe88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148320343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.3148320343
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.4085956421
Short name T275
Test name
Test status
Simulation time 252426545459 ps
CPU time 1703.69 seconds
Started Apr 18 03:40:36 PM PDT 24
Finished Apr 18 04:09:00 PM PDT 24
Peak memory 291260 kb
Host smart-c57ab30f-daa4-4a90-a0c2-ff035cf11564
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085956421 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.4085956421
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.3826851068
Short name T734
Test name
Test status
Simulation time 528000900 ps
CPU time 13.51 seconds
Started Apr 18 03:40:35 PM PDT 24
Finished Apr 18 03:40:49 PM PDT 24
Peak memory 241756 kb
Host smart-89e284c8-35a1-46a4-b501-333070d4653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826851068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.3826851068
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.2537699370
Short name T190
Test name
Test status
Simulation time 2259937332 ps
CPU time 8.14 seconds
Started Apr 18 03:46:35 PM PDT 24
Finished Apr 18 03:46:44 PM PDT 24
Peak memory 241940 kb
Host smart-c10500ec-248b-463c-9c74-95ae9be0feed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537699370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.2537699370
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.1955908422
Short name T195
Test name
Test status
Simulation time 121848124 ps
CPU time 3.29 seconds
Started Apr 18 03:46:34 PM PDT 24
Finished Apr 18 03:46:38 PM PDT 24
Peak memory 241864 kb
Host smart-9bdf8a22-874f-4f05-819d-61ae89bc3cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955908422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.1955908422
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.3270351857
Short name T196
Test name
Test status
Simulation time 584235857 ps
CPU time 4.91 seconds
Started Apr 18 03:46:34 PM PDT 24
Finished Apr 18 03:46:40 PM PDT 24
Peak memory 241852 kb
Host smart-5988fd58-e54c-47fb-a704-0774cfd0d0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270351857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.3270351857
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.4152690809
Short name T1021
Test name
Test status
Simulation time 1782081404 ps
CPU time 6.28 seconds
Started Apr 18 03:46:35 PM PDT 24
Finished Apr 18 03:46:42 PM PDT 24
Peak memory 242096 kb
Host smart-25973a65-bd43-429b-a228-50086f1111a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152690809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.4152690809
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.2661735887
Short name T490
Test name
Test status
Simulation time 193995342 ps
CPU time 4.19 seconds
Started Apr 18 03:46:38 PM PDT 24
Finished Apr 18 03:46:43 PM PDT 24
Peak memory 241860 kb
Host smart-5620e5ba-c7a4-4dec-b7bb-8d093050f418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661735887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.2661735887
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.376819144
Short name T1060
Test name
Test status
Simulation time 539785121 ps
CPU time 4.48 seconds
Started Apr 18 03:46:43 PM PDT 24
Finished Apr 18 03:46:48 PM PDT 24
Peak memory 241884 kb
Host smart-26dbb405-181c-4217-85e8-dcf5abb7acac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376819144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.376819144
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.3776182643
Short name T565
Test name
Test status
Simulation time 170280610 ps
CPU time 4.35 seconds
Started Apr 18 03:46:38 PM PDT 24
Finished Apr 18 03:46:43 PM PDT 24
Peak memory 242208 kb
Host smart-d4ad529e-ab3b-44f0-9a5c-e8f4633747f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776182643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.3776182643
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.1627857545
Short name T974
Test name
Test status
Simulation time 295139829 ps
CPU time 3.37 seconds
Started Apr 18 03:46:41 PM PDT 24
Finished Apr 18 03:46:44 PM PDT 24
Peak memory 241884 kb
Host smart-156d738c-e22d-4d7a-87e4-5e6d4200bd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627857545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.1627857545
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.508285284
Short name T1056
Test name
Test status
Simulation time 110433137 ps
CPU time 2.49 seconds
Started Apr 18 03:40:46 PM PDT 24
Finished Apr 18 03:40:49 PM PDT 24
Peak memory 240404 kb
Host smart-288c2187-9b26-4c12-b314-d33f649bdafb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508285284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.508285284
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.2148236736
Short name T919
Test name
Test status
Simulation time 212084247 ps
CPU time 4.02 seconds
Started Apr 18 03:40:41 PM PDT 24
Finished Apr 18 03:40:45 PM PDT 24
Peak memory 248552 kb
Host smart-0447399a-d861-4827-afd1-9ae5b7dfbc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148236736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.2148236736
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.3745009989
Short name T732
Test name
Test status
Simulation time 4954584288 ps
CPU time 46.14 seconds
Started Apr 18 03:40:48 PM PDT 24
Finished Apr 18 03:41:35 PM PDT 24
Peak memory 252996 kb
Host smart-6631cdf0-2129-48a8-95cf-5cf4497be3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745009989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.3745009989
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.4194882050
Short name T518
Test name
Test status
Simulation time 1936148778 ps
CPU time 33.87 seconds
Started Apr 18 03:40:40 PM PDT 24
Finished Apr 18 03:41:15 PM PDT 24
Peak memory 241712 kb
Host smart-eed48cbd-4918-42d8-885f-0eb52b921f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194882050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.4194882050
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.4156934691
Short name T859
Test name
Test status
Simulation time 145413063 ps
CPU time 4.57 seconds
Started Apr 18 03:40:41 PM PDT 24
Finished Apr 18 03:40:46 PM PDT 24
Peak memory 241768 kb
Host smart-12522117-f3ca-4bad-b811-42e9b633eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156934691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.4156934691
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.1958910723
Short name T855
Test name
Test status
Simulation time 853296107 ps
CPU time 24.84 seconds
Started Apr 18 03:40:40 PM PDT 24
Finished Apr 18 03:41:05 PM PDT 24
Peak memory 249400 kb
Host smart-fb5abeb3-7258-4336-a694-a5682e205322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958910723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.1958910723
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.736274369
Short name T796
Test name
Test status
Simulation time 437279358 ps
CPU time 5.45 seconds
Started Apr 18 03:40:40 PM PDT 24
Finished Apr 18 03:40:46 PM PDT 24
Peak memory 241892 kb
Host smart-affe1d6e-f296-40bb-9fce-6632855a54ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736274369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.736274369
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.927806747
Short name T846
Test name
Test status
Simulation time 701666450 ps
CPU time 11.48 seconds
Started Apr 18 03:40:41 PM PDT 24
Finished Apr 18 03:40:52 PM PDT 24
Peak memory 241980 kb
Host smart-603f306e-9a17-435c-b524-1836f0c1bda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927806747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.927806747
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.3252330659
Short name T602
Test name
Test status
Simulation time 1053473815 ps
CPU time 14.24 seconds
Started Apr 18 03:40:40 PM PDT 24
Finished Apr 18 03:40:55 PM PDT 24
Peak memory 241708 kb
Host smart-8567690f-1883-4920-b568-303ac093679f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3252330659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.3252330659
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.220910594
Short name T352
Test name
Test status
Simulation time 561552435 ps
CPU time 9.16 seconds
Started Apr 18 03:40:40 PM PDT 24
Finished Apr 18 03:40:50 PM PDT 24
Peak memory 241900 kb
Host smart-91859596-8f08-46fe-a4c7-d33d68a3ec45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=220910594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.220910594
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.2659365041
Short name T1083
Test name
Test status
Simulation time 3859502366 ps
CPU time 7.53 seconds
Started Apr 18 03:40:41 PM PDT 24
Finished Apr 18 03:40:49 PM PDT 24
Peak memory 242164 kb
Host smart-068cb0e2-7be5-472b-9d2e-c1d86c0781db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659365041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.2659365041
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.2651463997
Short name T763
Test name
Test status
Simulation time 22321496614 ps
CPU time 216.92 seconds
Started Apr 18 03:40:45 PM PDT 24
Finished Apr 18 03:44:22 PM PDT 24
Peak memory 257092 kb
Host smart-7a29edf3-16a1-4080-b979-4e33832170b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651463997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.2651463997
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.2793374372
Short name T971
Test name
Test status
Simulation time 37435502295 ps
CPU time 621.62 seconds
Started Apr 18 03:40:44 PM PDT 24
Finished Apr 18 03:51:06 PM PDT 24
Peak memory 284044 kb
Host smart-50aa0fb1-0e62-4d50-b80c-3ac48ede4635
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793374372 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.2793374372
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.1002437005
Short name T513
Test name
Test status
Simulation time 3632411607 ps
CPU time 30.04 seconds
Started Apr 18 03:40:39 PM PDT 24
Finished Apr 18 03:41:10 PM PDT 24
Peak memory 242072 kb
Host smart-f5372585-4d21-4fbf-bc03-8929d03eb86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002437005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.1002437005
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.1317441982
Short name T126
Test name
Test status
Simulation time 683447600 ps
CPU time 5.51 seconds
Started Apr 18 03:46:40 PM PDT 24
Finished Apr 18 03:46:46 PM PDT 24
Peak memory 241836 kb
Host smart-05d29177-3d02-4d15-85c1-f2a88e0a7396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317441982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.1317441982
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.3548944893
Short name T595
Test name
Test status
Simulation time 292410762 ps
CPU time 4.36 seconds
Started Apr 18 03:46:38 PM PDT 24
Finished Apr 18 03:46:43 PM PDT 24
Peak memory 242148 kb
Host smart-08062d79-e782-422b-8feb-e69487cf424c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548944893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.3548944893
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.704139900
Short name T917
Test name
Test status
Simulation time 148524941 ps
CPU time 4.49 seconds
Started Apr 18 03:46:40 PM PDT 24
Finished Apr 18 03:46:45 PM PDT 24
Peak memory 242060 kb
Host smart-0a0a056c-0014-4348-890a-4b97b59f4044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704139900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.704139900
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.1854112411
Short name T482
Test name
Test status
Simulation time 110744314 ps
CPU time 4.23 seconds
Started Apr 18 03:46:40 PM PDT 24
Finished Apr 18 03:46:44 PM PDT 24
Peak memory 241844 kb
Host smart-0777df8b-f1c6-45be-aeec-7124d93f349d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854112411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.1854112411
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.3296435085
Short name T456
Test name
Test status
Simulation time 192842336 ps
CPU time 4.06 seconds
Started Apr 18 03:46:43 PM PDT 24
Finished Apr 18 03:46:47 PM PDT 24
Peak memory 241952 kb
Host smart-ea66881c-b710-45be-8d6b-e5317f49b08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296435085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.3296435085
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.3810330888
Short name T464
Test name
Test status
Simulation time 2212099306 ps
CPU time 5.98 seconds
Started Apr 18 03:46:40 PM PDT 24
Finished Apr 18 03:46:47 PM PDT 24
Peak memory 241996 kb
Host smart-1171cbee-c894-450a-a751-33cfd4544a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810330888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.3810330888
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.3257200752
Short name T175
Test name
Test status
Simulation time 218924773 ps
CPU time 3.35 seconds
Started Apr 18 03:46:40 PM PDT 24
Finished Apr 18 03:46:44 PM PDT 24
Peak memory 241748 kb
Host smart-a57fda49-d28b-43eb-aed5-404ec7356eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257200752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.3257200752
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.2039194212
Short name T933
Test name
Test status
Simulation time 129312227 ps
CPU time 3.74 seconds
Started Apr 18 03:46:40 PM PDT 24
Finished Apr 18 03:46:44 PM PDT 24
Peak memory 242068 kb
Host smart-f40c530d-81c3-4f6c-bfa9-876f96029b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039194212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.2039194212
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.415202225
Short name T969
Test name
Test status
Simulation time 294731388 ps
CPU time 4.66 seconds
Started Apr 18 03:46:38 PM PDT 24
Finished Apr 18 03:46:43 PM PDT 24
Peak memory 241796 kb
Host smart-f1cadc3f-fc86-4aa9-a413-f71f0df09ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415202225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.415202225
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.1641462383
Short name T857
Test name
Test status
Simulation time 86753446 ps
CPU time 1.56 seconds
Started Apr 18 03:40:55 PM PDT 24
Finished Apr 18 03:40:57 PM PDT 24
Peak memory 240140 kb
Host smart-ecb809db-2b72-4f68-b417-dcec5ad645a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641462383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.1641462383
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.2898201621
Short name T118
Test name
Test status
Simulation time 837682625 ps
CPU time 27.92 seconds
Started Apr 18 03:40:45 PM PDT 24
Finished Apr 18 03:41:14 PM PDT 24
Peak memory 243048 kb
Host smart-2f6d75f4-109f-4379-937b-97785df75b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898201621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.2898201621
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.481983830
Short name T1153
Test name
Test status
Simulation time 3938358934 ps
CPU time 17.46 seconds
Started Apr 18 03:40:45 PM PDT 24
Finished Apr 18 03:41:04 PM PDT 24
Peak memory 241888 kb
Host smart-3d4617c0-112a-4b8d-aa75-18701429a32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481983830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.481983830
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.1059889015
Short name T1019
Test name
Test status
Simulation time 558169123 ps
CPU time 9.84 seconds
Started Apr 18 03:40:46 PM PDT 24
Finished Apr 18 03:40:56 PM PDT 24
Peak memory 242168 kb
Host smart-617790e2-ee54-44fd-b3a5-3672a31c1a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059889015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.1059889015
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.735884835
Short name T86
Test name
Test status
Simulation time 1535662080 ps
CPU time 5.53 seconds
Started Apr 18 03:40:45 PM PDT 24
Finished Apr 18 03:40:51 PM PDT 24
Peak memory 241720 kb
Host smart-3f2cfc7d-fe55-4466-87b4-8b10a653c5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735884835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.735884835
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.4114857802
Short name T607
Test name
Test status
Simulation time 1092548804 ps
CPU time 9.42 seconds
Started Apr 18 03:40:46 PM PDT 24
Finished Apr 18 03:40:57 PM PDT 24
Peak memory 242256 kb
Host smart-e111036a-83e2-48fc-811c-67d8aa1021cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114857802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.4114857802
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.1284506942
Short name T178
Test name
Test status
Simulation time 1049464218 ps
CPU time 13.2 seconds
Started Apr 18 03:40:51 PM PDT 24
Finished Apr 18 03:41:05 PM PDT 24
Peak memory 242264 kb
Host smart-4f22e338-75c6-489e-8874-d2c51af9b19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284506942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.1284506942
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.4036154062
Short name T776
Test name
Test status
Simulation time 320593427 ps
CPU time 4.7 seconds
Started Apr 18 03:40:45 PM PDT 24
Finished Apr 18 03:40:51 PM PDT 24
Peak memory 242104 kb
Host smart-8eae3dac-77b9-4c74-af8c-bb5a43396d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036154062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.4036154062
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.3128039250
Short name T204
Test name
Test status
Simulation time 2822953968 ps
CPU time 30.33 seconds
Started Apr 18 03:40:43 PM PDT 24
Finished Apr 18 03:41:14 PM PDT 24
Peak memory 241888 kb
Host smart-feaab58c-e630-4452-9c0b-bbff94299e99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128039250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.3128039250
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.2876960023
Short name T358
Test name
Test status
Simulation time 210131483 ps
CPU time 5.6 seconds
Started Apr 18 03:40:50 PM PDT 24
Finished Apr 18 03:40:56 PM PDT 24
Peak memory 241900 kb
Host smart-c6460a22-d620-444e-a23b-53983830bf85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876960023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.2876960023
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.4287561216
Short name T433
Test name
Test status
Simulation time 230661217 ps
CPU time 5.76 seconds
Started Apr 18 03:40:45 PM PDT 24
Finished Apr 18 03:40:52 PM PDT 24
Peak memory 241936 kb
Host smart-c3d97983-8977-41c9-a338-475290ffd732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287561216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.4287561216
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.2470241476
Short name T897
Test name
Test status
Simulation time 11183340935 ps
CPU time 105.13 seconds
Started Apr 18 03:40:55 PM PDT 24
Finished Apr 18 03:42:40 PM PDT 24
Peak memory 248792 kb
Host smart-79bc79c4-6702-44ce-b7d3-da8cf877b6dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470241476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.2470241476
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.297970118
Short name T176
Test name
Test status
Simulation time 36630899321 ps
CPU time 548.97 seconds
Started Apr 18 03:40:50 PM PDT 24
Finished Apr 18 03:49:59 PM PDT 24
Peak memory 280704 kb
Host smart-c45bca89-a857-45a5-a1f8-d1887d053913
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297970118 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.297970118
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.1207121741
Short name T256
Test name
Test status
Simulation time 16129391430 ps
CPU time 34.3 seconds
Started Apr 18 03:40:49 PM PDT 24
Finished Apr 18 03:41:24 PM PDT 24
Peak memory 243148 kb
Host smart-8f279138-04e1-4eea-9200-a84fd6892aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207121741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.1207121741
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.2352375255
Short name T829
Test name
Test status
Simulation time 1844128692 ps
CPU time 5.92 seconds
Started Apr 18 03:46:38 PM PDT 24
Finished Apr 18 03:46:44 PM PDT 24
Peak memory 241884 kb
Host smart-30a8ee29-3f5a-4b01-b85c-996492723586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352375255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.2352375255
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.130527778
Short name T912
Test name
Test status
Simulation time 142361126 ps
CPU time 5.43 seconds
Started Apr 18 03:46:39 PM PDT 24
Finished Apr 18 03:46:44 PM PDT 24
Peak memory 241860 kb
Host smart-a4c6eafd-2977-47f8-88b5-f5bea7275861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130527778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.130527778
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.2720482666
Short name T825
Test name
Test status
Simulation time 2117618437 ps
CPU time 4.99 seconds
Started Apr 18 03:46:40 PM PDT 24
Finished Apr 18 03:46:45 PM PDT 24
Peak memory 242176 kb
Host smart-a5df1daf-e484-4ce8-8ee4-afa99cede139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720482666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.2720482666
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.2925761774
Short name T1133
Test name
Test status
Simulation time 131673839 ps
CPU time 3.94 seconds
Started Apr 18 03:46:45 PM PDT 24
Finished Apr 18 03:46:49 PM PDT 24
Peak memory 241936 kb
Host smart-b5608656-7fc1-49c3-b4e9-f0675c56aa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925761774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.2925761774
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.1691703347
Short name T224
Test name
Test status
Simulation time 1422211585 ps
CPU time 4.48 seconds
Started Apr 18 03:46:45 PM PDT 24
Finished Apr 18 03:46:50 PM PDT 24
Peak memory 241820 kb
Host smart-4fa84ff2-16d6-43dd-bf52-13ce684df540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691703347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.1691703347
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.2282060245
Short name T1129
Test name
Test status
Simulation time 139368636 ps
CPU time 5.05 seconds
Started Apr 18 03:46:44 PM PDT 24
Finished Apr 18 03:46:49 PM PDT 24
Peak memory 241764 kb
Host smart-d9c0d71c-d7a5-4356-bade-ac463871bd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282060245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.2282060245
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.2307021829
Short name T1017
Test name
Test status
Simulation time 131333119 ps
CPU time 3.48 seconds
Started Apr 18 03:46:44 PM PDT 24
Finished Apr 18 03:46:48 PM PDT 24
Peak memory 242184 kb
Host smart-c2247489-39ff-4d99-86a9-d3f048ff44ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307021829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.2307021829
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.3104243228
Short name T1003
Test name
Test status
Simulation time 152235803 ps
CPU time 4.14 seconds
Started Apr 18 03:46:49 PM PDT 24
Finished Apr 18 03:46:54 PM PDT 24
Peak memory 241824 kb
Host smart-145570fb-b1c8-4e19-9757-24b5b1e3d99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104243228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.3104243228
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.2981084408
Short name T468
Test name
Test status
Simulation time 182677471 ps
CPU time 4.43 seconds
Started Apr 18 03:46:48 PM PDT 24
Finished Apr 18 03:46:53 PM PDT 24
Peak memory 241880 kb
Host smart-6360ccd2-c814-4dc5-b89b-5e3905646256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981084408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.2981084408
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.2546370531
Short name T12
Test name
Test status
Simulation time 469606971 ps
CPU time 3.59 seconds
Started Apr 18 03:46:50 PM PDT 24
Finished Apr 18 03:46:54 PM PDT 24
Peak memory 241840 kb
Host smart-64ef001c-16d9-4cc2-813d-312da514dec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546370531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.2546370531
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.1155803953
Short name T976
Test name
Test status
Simulation time 53270719 ps
CPU time 1.61 seconds
Started Apr 18 03:40:59 PM PDT 24
Finished Apr 18 03:41:01 PM PDT 24
Peak memory 240144 kb
Host smart-c9bc7888-2203-4d2f-80da-01441d77515a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155803953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.1155803953
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.1752385673
Short name T539
Test name
Test status
Simulation time 546541095 ps
CPU time 15.86 seconds
Started Apr 18 03:40:55 PM PDT 24
Finished Apr 18 03:41:11 PM PDT 24
Peak memory 242972 kb
Host smart-a6c8c460-36a4-4388-9f09-c17566ee7ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752385673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.1752385673
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.2536106584
Short name T678
Test name
Test status
Simulation time 482760501 ps
CPU time 13.45 seconds
Started Apr 18 03:40:56 PM PDT 24
Finished Apr 18 03:41:10 PM PDT 24
Peak memory 242356 kb
Host smart-6dea3452-433c-4e7f-9c9f-465141713ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536106584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.2536106584
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.541245587
Short name T617
Test name
Test status
Simulation time 649261851 ps
CPU time 8.37 seconds
Started Apr 18 03:40:55 PM PDT 24
Finished Apr 18 03:41:04 PM PDT 24
Peak memory 242128 kb
Host smart-109cd03a-181c-421a-b69b-66523ea8ab29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541245587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.541245587
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.515951706
Short name T33
Test name
Test status
Simulation time 138006185 ps
CPU time 4.2 seconds
Started Apr 18 03:40:55 PM PDT 24
Finished Apr 18 03:41:00 PM PDT 24
Peak memory 241848 kb
Host smart-5c20d9f2-eda1-4742-b784-5c1aa7aeef57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515951706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.515951706
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.1079961209
Short name T223
Test name
Test status
Simulation time 2863192276 ps
CPU time 17.95 seconds
Started Apr 18 03:40:55 PM PDT 24
Finished Apr 18 03:41:13 PM PDT 24
Peak memory 242068 kb
Host smart-0475eb1a-9772-4669-b0cf-ef1c91b67ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079961209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.1079961209
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.1326394968
Short name T1186
Test name
Test status
Simulation time 685628905 ps
CPU time 9.26 seconds
Started Apr 18 03:40:56 PM PDT 24
Finished Apr 18 03:41:06 PM PDT 24
Peak memory 241720 kb
Host smart-c7842fcd-162e-4830-a14b-04793e06350c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326394968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.1326394968
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.3575369079
Short name T1166
Test name
Test status
Simulation time 490433637 ps
CPU time 11.8 seconds
Started Apr 18 03:40:54 PM PDT 24
Finished Apr 18 03:41:07 PM PDT 24
Peak memory 242128 kb
Host smart-1ae1092e-96d0-44f9-b37f-fc6db8410e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575369079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.3575369079
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.317990527
Short name T1148
Test name
Test status
Simulation time 178296497 ps
CPU time 5.04 seconds
Started Apr 18 03:40:54 PM PDT 24
Finished Apr 18 03:41:00 PM PDT 24
Peak memory 247224 kb
Host smart-c65f86d0-d209-451b-8fdd-0687eccdcf3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317990527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.317990527
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.3525710421
Short name T354
Test name
Test status
Simulation time 784966396 ps
CPU time 11.49 seconds
Started Apr 18 03:40:56 PM PDT 24
Finished Apr 18 03:41:07 PM PDT 24
Peak memory 241948 kb
Host smart-948eb48b-703a-4900-9908-805fe09dc778
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525710421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.3525710421
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.2917463563
Short name T597
Test name
Test status
Simulation time 2137297498 ps
CPU time 6.07 seconds
Started Apr 18 03:40:54 PM PDT 24
Finished Apr 18 03:41:00 PM PDT 24
Peak memory 241920 kb
Host smart-e6151be9-6844-4e65-9222-09050cd28c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917463563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.2917463563
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.1999240708
Short name T102
Test name
Test status
Simulation time 13731357249 ps
CPU time 100.59 seconds
Started Apr 18 03:40:59 PM PDT 24
Finished Apr 18 03:42:40 PM PDT 24
Peak memory 245336 kb
Host smart-44105c00-cc87-48fc-bd4d-fe980e0bc218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999240708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all
.1999240708
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.3505870179
Short name T141
Test name
Test status
Simulation time 167030136998 ps
CPU time 1155.45 seconds
Started Apr 18 03:41:01 PM PDT 24
Finished Apr 18 04:00:17 PM PDT 24
Peak memory 279148 kb
Host smart-9b0fbf27-17be-4a5d-8c35-c917679a8357
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505870179 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.3505870179
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.698745671
Short name T374
Test name
Test status
Simulation time 4690559674 ps
CPU time 39.12 seconds
Started Apr 18 03:40:59 PM PDT 24
Finished Apr 18 03:41:39 PM PDT 24
Peak memory 242176 kb
Host smart-0d78ad81-7e7b-4a7d-b3b7-6f522a1a6976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698745671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.698745671
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.4251444799
Short name T1031
Test name
Test status
Simulation time 507938912 ps
CPU time 6.12 seconds
Started Apr 18 03:46:50 PM PDT 24
Finished Apr 18 03:46:57 PM PDT 24
Peak memory 241836 kb
Host smart-348ab4de-3906-46ca-8368-aa852b934f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251444799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.4251444799
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.1429422918
Short name T659
Test name
Test status
Simulation time 163753639 ps
CPU time 5.12 seconds
Started Apr 18 03:46:53 PM PDT 24
Finished Apr 18 03:46:59 PM PDT 24
Peak memory 241832 kb
Host smart-b267f823-158a-444d-a3ea-cc1ef7bad9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429422918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.1429422918
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.3931845463
Short name T1058
Test name
Test status
Simulation time 453710213 ps
CPU time 5.37 seconds
Started Apr 18 03:46:49 PM PDT 24
Finished Apr 18 03:46:55 PM PDT 24
Peak memory 242168 kb
Host smart-0b6cfa23-a5ec-4eda-bdfd-15e885b243cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931845463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.3931845463
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.1063541254
Short name T683
Test name
Test status
Simulation time 1965774210 ps
CPU time 7.13 seconds
Started Apr 18 03:46:52 PM PDT 24
Finished Apr 18 03:47:00 PM PDT 24
Peak memory 241800 kb
Host smart-5cd99642-9c78-4cfc-b28b-5e0b73bbf4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063541254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.1063541254
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.3227173958
Short name T1008
Test name
Test status
Simulation time 2283478373 ps
CPU time 6.24 seconds
Started Apr 18 03:46:51 PM PDT 24
Finished Apr 18 03:46:58 PM PDT 24
Peak memory 242220 kb
Host smart-e94793a4-8392-4d2a-a841-c0701f389ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227173958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.3227173958
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.3809798778
Short name T41
Test name
Test status
Simulation time 133223557 ps
CPU time 4.24 seconds
Started Apr 18 03:46:50 PM PDT 24
Finished Apr 18 03:46:55 PM PDT 24
Peak memory 241928 kb
Host smart-ba69ca1c-a28e-427e-a5e5-dddeb42e6fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809798778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.3809798778
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.30744482
Short name T983
Test name
Test status
Simulation time 115122767 ps
CPU time 4.13 seconds
Started Apr 18 03:46:53 PM PDT 24
Finished Apr 18 03:46:58 PM PDT 24
Peak memory 242228 kb
Host smart-024815b3-7294-4cf3-a239-fc6784b5ff19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30744482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.30744482
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.1998231870
Short name T1001
Test name
Test status
Simulation time 279148851 ps
CPU time 4.62 seconds
Started Apr 18 03:46:52 PM PDT 24
Finished Apr 18 03:46:57 PM PDT 24
Peak memory 241940 kb
Host smart-5d33423f-7df7-4d0c-b18f-e7653dd76d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998231870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.1998231870
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.1062315331
Short name T487
Test name
Test status
Simulation time 3087561022 ps
CPU time 9.04 seconds
Started Apr 18 03:46:51 PM PDT 24
Finished Apr 18 03:47:01 PM PDT 24
Peak memory 241912 kb
Host smart-b894735f-1369-467e-b88d-6f02dc85ca8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062315331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.1062315331
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.3332158309
Short name T785
Test name
Test status
Simulation time 48918154 ps
CPU time 1.68 seconds
Started Apr 18 03:41:04 PM PDT 24
Finished Apr 18 03:41:06 PM PDT 24
Peak memory 240316 kb
Host smart-909856b6-90a8-4355-ac00-8e4019a5aa82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332158309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.3332158309
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.417763131
Short name T937
Test name
Test status
Simulation time 6176506266 ps
CPU time 15.27 seconds
Started Apr 18 03:41:05 PM PDT 24
Finished Apr 18 03:41:21 PM PDT 24
Peak memory 243836 kb
Host smart-984a97b4-872a-4c0e-b779-44700bf74553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417763131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.417763131
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.1859443723
Short name T328
Test name
Test status
Simulation time 668493376 ps
CPU time 21.64 seconds
Started Apr 18 03:41:04 PM PDT 24
Finished Apr 18 03:41:27 PM PDT 24
Peak memory 241880 kb
Host smart-684687f2-b770-4f72-8824-ee8de5e22f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859443723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1859443723
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.196788037
Short name T412
Test name
Test status
Simulation time 2762913601 ps
CPU time 19.4 seconds
Started Apr 18 03:41:05 PM PDT 24
Finished Apr 18 03:41:26 PM PDT 24
Peak memory 242228 kb
Host smart-1ee6a9e4-9b8b-4478-af81-980213468a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196788037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.196788037
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.3493780366
Short name T116
Test name
Test status
Simulation time 206023042 ps
CPU time 4.88 seconds
Started Apr 18 03:41:06 PM PDT 24
Finished Apr 18 03:41:12 PM PDT 24
Peak memory 242100 kb
Host smart-e23475c3-5ea2-42bb-8aa7-0cd2eeb0b110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493780366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3493780366
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.3666194039
Short name T740
Test name
Test status
Simulation time 2718410158 ps
CPU time 43.01 seconds
Started Apr 18 03:41:06 PM PDT 24
Finished Apr 18 03:41:49 PM PDT 24
Peak memory 257016 kb
Host smart-b3687f6a-4d1d-4bcf-b1b8-d3669068e25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666194039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.3666194039
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.2688246763
Short name T610
Test name
Test status
Simulation time 3561700088 ps
CPU time 15.03 seconds
Started Apr 18 03:41:05 PM PDT 24
Finished Apr 18 03:41:20 PM PDT 24
Peak memory 242432 kb
Host smart-79e70d2b-632f-4c45-96dd-4d8280d41076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688246763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.2688246763
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.1770353857
Short name T1191
Test name
Test status
Simulation time 543379435 ps
CPU time 7.56 seconds
Started Apr 18 03:40:59 PM PDT 24
Finished Apr 18 03:41:07 PM PDT 24
Peak memory 241836 kb
Host smart-267df916-a746-4ad1-89c5-bde4248943d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770353857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.1770353857
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.2428133115
Short name T812
Test name
Test status
Simulation time 2067929849 ps
CPU time 22.53 seconds
Started Apr 18 03:41:06 PM PDT 24
Finished Apr 18 03:41:29 PM PDT 24
Peak memory 241632 kb
Host smart-1f15a8dd-6e08-4e4d-8f51-35d585941ff8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428133115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2428133115
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.3874023067
Short name T1151
Test name
Test status
Simulation time 450130969 ps
CPU time 10.99 seconds
Started Apr 18 03:41:05 PM PDT 24
Finished Apr 18 03:41:16 PM PDT 24
Peak memory 241900 kb
Host smart-8f20bf96-9ebc-465e-8eaa-4fc4d151f9b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874023067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.3874023067
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.2197763189
Short name T1009
Test name
Test status
Simulation time 248617447 ps
CPU time 5.44 seconds
Started Apr 18 03:40:59 PM PDT 24
Finished Apr 18 03:41:05 PM PDT 24
Peak memory 241772 kb
Host smart-b8157190-5e22-404c-a944-43ba612089f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197763189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.2197763189
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.3667817138
Short name T238
Test name
Test status
Simulation time 14773878383 ps
CPU time 44.7 seconds
Started Apr 18 03:41:07 PM PDT 24
Finished Apr 18 03:41:53 PM PDT 24
Peak memory 242608 kb
Host smart-6a2173ec-6bef-481c-8c1e-b0f5e77c195d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667817138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.3667817138
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.2869925969
Short name T1077
Test name
Test status
Simulation time 80453480435 ps
CPU time 2547.56 seconds
Started Apr 18 03:41:05 PM PDT 24
Finished Apr 18 04:23:33 PM PDT 24
Peak memory 609320 kb
Host smart-bfe8ae45-ba39-409f-aa9a-dc6ea0ee8cae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869925969 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.2869925969
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.2080581282
Short name T818
Test name
Test status
Simulation time 4006119968 ps
CPU time 7.25 seconds
Started Apr 18 03:41:05 PM PDT 24
Finished Apr 18 03:41:13 PM PDT 24
Peak memory 242520 kb
Host smart-304b8ca7-abf2-488a-a246-fccae17dfcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080581282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.2080581282
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.3964029412
Short name T963
Test name
Test status
Simulation time 104261518 ps
CPU time 4.53 seconds
Started Apr 18 03:46:51 PM PDT 24
Finished Apr 18 03:46:56 PM PDT 24
Peak memory 241764 kb
Host smart-3093ea89-d7a7-4712-9394-452b76dc489b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964029412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.3964029412
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.1750408058
Short name T1111
Test name
Test status
Simulation time 328407520 ps
CPU time 4.39 seconds
Started Apr 18 03:46:52 PM PDT 24
Finished Apr 18 03:46:57 PM PDT 24
Peak memory 242156 kb
Host smart-cab34308-470f-4873-a23a-1fa3ec198a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750408058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.1750408058
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.2423748325
Short name T968
Test name
Test status
Simulation time 243531859 ps
CPU time 3.87 seconds
Started Apr 18 03:46:51 PM PDT 24
Finished Apr 18 03:46:56 PM PDT 24
Peak memory 241800 kb
Host smart-dd189c67-10d0-45d9-88bb-c9e1ba712881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423748325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.2423748325
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.1774871642
Short name T194
Test name
Test status
Simulation time 155366801 ps
CPU time 3.85 seconds
Started Apr 18 03:46:54 PM PDT 24
Finished Apr 18 03:46:59 PM PDT 24
Peak memory 241824 kb
Host smart-51c22ea6-3089-4a9b-a75c-70f71d20061f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774871642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.1774871642
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.3654502243
Short name T418
Test name
Test status
Simulation time 143059495 ps
CPU time 5.14 seconds
Started Apr 18 03:46:56 PM PDT 24
Finished Apr 18 03:47:01 PM PDT 24
Peak memory 241888 kb
Host smart-e11118b8-3445-402c-abc1-8248225bce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654502243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.3654502243
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.455466674
Short name T225
Test name
Test status
Simulation time 492149044 ps
CPU time 3.39 seconds
Started Apr 18 03:46:53 PM PDT 24
Finished Apr 18 03:46:57 PM PDT 24
Peak memory 241808 kb
Host smart-fbe0791d-f85f-400e-be7a-fc0b3a482001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455466674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.455466674
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.1052606907
Short name T1028
Test name
Test status
Simulation time 2235074101 ps
CPU time 6.53 seconds
Started Apr 18 03:46:52 PM PDT 24
Finished Apr 18 03:46:59 PM PDT 24
Peak memory 241956 kb
Host smart-d68b674a-fbc4-4a9c-ac04-580e23a64298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052606907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.1052606907
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.310505951
Short name T1030
Test name
Test status
Simulation time 2019463336 ps
CPU time 8.13 seconds
Started Apr 18 03:46:58 PM PDT 24
Finished Apr 18 03:47:07 PM PDT 24
Peak memory 242244 kb
Host smart-f025b01c-2e06-45b0-892e-8689612ae847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310505951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.310505951
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.2452369846
Short name T1035
Test name
Test status
Simulation time 2089301426 ps
CPU time 6.31 seconds
Started Apr 18 03:46:52 PM PDT 24
Finished Apr 18 03:46:59 PM PDT 24
Peak memory 241780 kb
Host smart-e351c6d7-bea3-4034-af2a-cec48b3f06b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452369846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.2452369846
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.978200869
Short name T579
Test name
Test status
Simulation time 123035339 ps
CPU time 1.95 seconds
Started Apr 18 03:41:16 PM PDT 24
Finished Apr 18 03:41:18 PM PDT 24
Peak memory 240184 kb
Host smart-c98b8151-ae45-47ba-9c9f-4af2f144ee65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978200869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.978200869
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.3795982852
Short name T1045
Test name
Test status
Simulation time 3701465469 ps
CPU time 25.81 seconds
Started Apr 18 03:41:11 PM PDT 24
Finished Apr 18 03:41:37 PM PDT 24
Peak memory 241808 kb
Host smart-2b5e668d-7b4c-4754-81e3-c6c97c3d0047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795982852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.3795982852
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.2251066464
Short name T543
Test name
Test status
Simulation time 3404548516 ps
CPU time 9.35 seconds
Started Apr 18 03:41:11 PM PDT 24
Finished Apr 18 03:41:20 PM PDT 24
Peak memory 242412 kb
Host smart-d1ae919a-514e-4ee0-a09c-a76631f821eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251066464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.2251066464
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.3494911776
Short name T545
Test name
Test status
Simulation time 506046089 ps
CPU time 4.3 seconds
Started Apr 18 03:41:05 PM PDT 24
Finished Apr 18 03:41:09 PM PDT 24
Peak memory 241776 kb
Host smart-0f52f3a4-567e-46bb-81b4-cc4e3411c595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494911776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.3494911776
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.911179164
Short name T1057
Test name
Test status
Simulation time 313512929 ps
CPU time 6.16 seconds
Started Apr 18 03:41:10 PM PDT 24
Finished Apr 18 03:41:17 PM PDT 24
Peak memory 242204 kb
Host smart-7978f274-d781-4621-95be-e0ed2dc1991e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911179164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.911179164
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.3862807969
Short name T801
Test name
Test status
Simulation time 1328453603 ps
CPU time 32.92 seconds
Started Apr 18 03:41:13 PM PDT 24
Finished Apr 18 03:41:46 PM PDT 24
Peak memory 241952 kb
Host smart-efad4572-f1d4-47d0-9e4c-c9fddb067795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862807969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.3862807969
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.1871986516
Short name T754
Test name
Test status
Simulation time 149051899 ps
CPU time 6.63 seconds
Started Apr 18 03:41:04 PM PDT 24
Finished Apr 18 03:41:11 PM PDT 24
Peak memory 242036 kb
Host smart-000e0b9c-8e5b-40f4-af1b-3e75b3e735f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871986516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.1871986516
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.810323084
Short name T422
Test name
Test status
Simulation time 292059626 ps
CPU time 7.2 seconds
Started Apr 18 03:41:06 PM PDT 24
Finished Apr 18 03:41:14 PM PDT 24
Peak memory 241804 kb
Host smart-dfd41fb8-529c-4243-a826-ccebba8ce509
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=810323084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.810323084
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.2525620430
Short name T616
Test name
Test status
Simulation time 704669295 ps
CPU time 12.14 seconds
Started Apr 18 03:41:10 PM PDT 24
Finished Apr 18 03:41:23 PM PDT 24
Peak memory 242092 kb
Host smart-7ccb3521-4519-42c3-9d9a-9e925596c8e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2525620430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.2525620430
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.312650217
Short name T925
Test name
Test status
Simulation time 209408350 ps
CPU time 7.49 seconds
Started Apr 18 03:41:08 PM PDT 24
Finished Apr 18 03:41:16 PM PDT 24
Peak memory 241844 kb
Host smart-348b0ff7-8d90-4ea7-8b86-e2091f0436f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312650217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.312650217
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.432240856
Short name T327
Test name
Test status
Simulation time 7202192230 ps
CPU time 71.58 seconds
Started Apr 18 03:41:15 PM PDT 24
Finished Apr 18 03:42:27 PM PDT 24
Peak memory 245884 kb
Host smart-f992d8a0-0fcf-4a74-a035-d82f5e73da62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432240856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.
432240856
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.319798661
Short name T721
Test name
Test status
Simulation time 289536631 ps
CPU time 4.55 seconds
Started Apr 18 03:41:11 PM PDT 24
Finished Apr 18 03:41:16 PM PDT 24
Peak memory 241844 kb
Host smart-381478c6-040e-4b38-9f09-89a337cf99b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319798661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.319798661
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.706367988
Short name T940
Test name
Test status
Simulation time 406846370 ps
CPU time 3.83 seconds
Started Apr 18 03:46:52 PM PDT 24
Finished Apr 18 03:46:57 PM PDT 24
Peak memory 241800 kb
Host smart-82de4afa-9ad4-4b6a-8784-f53da3188790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706367988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.706367988
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.1681056893
Short name T978
Test name
Test status
Simulation time 209496206 ps
CPU time 4.95 seconds
Started Apr 18 03:46:53 PM PDT 24
Finished Apr 18 03:46:59 PM PDT 24
Peak memory 241756 kb
Host smart-2da7d4a3-a7fb-4fcb-a927-5bf08510f4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681056893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.1681056893
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.3829368441
Short name T387
Test name
Test status
Simulation time 362111678 ps
CPU time 5.48 seconds
Started Apr 18 03:46:59 PM PDT 24
Finished Apr 18 03:47:05 PM PDT 24
Peak memory 241892 kb
Host smart-632824a8-a8cc-4c46-a0cc-c0f711cbcdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829368441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.3829368441
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.3934790563
Short name T424
Test name
Test status
Simulation time 121778039 ps
CPU time 3.32 seconds
Started Apr 18 03:46:55 PM PDT 24
Finished Apr 18 03:46:59 PM PDT 24
Peak memory 241880 kb
Host smart-eaeb8f61-e9c2-4067-8420-c283e34cd282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934790563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.3934790563
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.1380128387
Short name T653
Test name
Test status
Simulation time 424232420 ps
CPU time 4.59 seconds
Started Apr 18 03:46:58 PM PDT 24
Finished Apr 18 03:47:03 PM PDT 24
Peak memory 242120 kb
Host smart-4a312986-cbdb-49d0-9e90-d47ce75c2114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380128387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.1380128387
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.2964151285
Short name T1159
Test name
Test status
Simulation time 617610371 ps
CPU time 4.71 seconds
Started Apr 18 03:46:52 PM PDT 24
Finished Apr 18 03:46:58 PM PDT 24
Peak memory 242140 kb
Host smart-45a84daf-1ace-44dd-9981-df7946ac87db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964151285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.2964151285
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.2943856743
Short name T1029
Test name
Test status
Simulation time 156007885 ps
CPU time 3.31 seconds
Started Apr 18 03:46:56 PM PDT 24
Finished Apr 18 03:47:00 PM PDT 24
Peak memory 242044 kb
Host smart-4f8c5ed9-a496-4111-a40e-c218b0212e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943856743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.2943856743
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.2838957990
Short name T169
Test name
Test status
Simulation time 163574062 ps
CPU time 4.08 seconds
Started Apr 18 03:47:00 PM PDT 24
Finished Apr 18 03:47:04 PM PDT 24
Peak memory 242184 kb
Host smart-776d16c7-7829-4653-a85e-262d2955c0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838957990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.2838957990
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.1417750169
Short name T52
Test name
Test status
Simulation time 499683923 ps
CPU time 5.36 seconds
Started Apr 18 03:46:58 PM PDT 24
Finished Apr 18 03:47:05 PM PDT 24
Peak memory 241872 kb
Host smart-190266cb-d902-4750-b655-f4b485acf022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417750169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.1417750169
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.827803162
Short name T743
Test name
Test status
Simulation time 170882893 ps
CPU time 1.66 seconds
Started Apr 18 03:41:19 PM PDT 24
Finished Apr 18 03:41:21 PM PDT 24
Peak memory 240164 kb
Host smart-45fe6b90-af7c-46fd-bd74-f7e34ea13d2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827803162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.827803162
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.1797121352
Short name T1101
Test name
Test status
Simulation time 6744825218 ps
CPU time 20.46 seconds
Started Apr 18 03:41:22 PM PDT 24
Finished Apr 18 03:41:43 PM PDT 24
Peak memory 243664 kb
Host smart-51e9695b-fc49-47a3-895a-ca10aa4da557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797121352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.1797121352
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.3855001754
Short name T7
Test name
Test status
Simulation time 25796326678 ps
CPU time 52.42 seconds
Started Apr 18 03:41:19 PM PDT 24
Finished Apr 18 03:42:12 PM PDT 24
Peak memory 256788 kb
Host smart-3a617d92-3d83-4671-8e4e-a185619bfdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855001754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.3855001754
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.2504047726
Short name T608
Test name
Test status
Simulation time 958379158 ps
CPU time 35.17 seconds
Started Apr 18 03:41:22 PM PDT 24
Finished Apr 18 03:41:58 PM PDT 24
Peak memory 242120 kb
Host smart-39727db5-651b-492e-8561-6f0b3fbdd53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504047726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.2504047726
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.1404650314
Short name T529
Test name
Test status
Simulation time 292295909 ps
CPU time 4.33 seconds
Started Apr 18 03:41:17 PM PDT 24
Finished Apr 18 03:41:22 PM PDT 24
Peak memory 242140 kb
Host smart-9f8b4d0a-9987-4b6e-a0c1-ddfe9d76f3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404650314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.1404650314
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.4117447054
Short name T500
Test name
Test status
Simulation time 1222005181 ps
CPU time 29.01 seconds
Started Apr 18 03:41:20 PM PDT 24
Finished Apr 18 03:41:50 PM PDT 24
Peak memory 249888 kb
Host smart-d284295e-040f-47b7-8d85-8ac1537bcb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117447054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.4117447054
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.1697247802
Short name T908
Test name
Test status
Simulation time 801554066 ps
CPU time 32.43 seconds
Started Apr 18 03:41:20 PM PDT 24
Finished Apr 18 03:41:53 PM PDT 24
Peak memory 242136 kb
Host smart-39dbe69c-8e07-4f2e-9868-bb7cbdde50dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697247802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.1697247802
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.534223171
Short name T868
Test name
Test status
Simulation time 277132505 ps
CPU time 4.02 seconds
Started Apr 18 03:41:20 PM PDT 24
Finished Apr 18 03:41:25 PM PDT 24
Peak memory 242104 kb
Host smart-18f92456-b86f-406a-b9f1-57bcd09f4438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534223171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.534223171
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.2275836211
Short name T547
Test name
Test status
Simulation time 652685108 ps
CPU time 9.67 seconds
Started Apr 18 03:41:21 PM PDT 24
Finished Apr 18 03:41:31 PM PDT 24
Peak memory 241676 kb
Host smart-ac8a0382-9fe8-4cac-bb5a-3259a92b7044
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2275836211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.2275836211
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.703042529
Short name T639
Test name
Test status
Simulation time 2171144127 ps
CPU time 7.3 seconds
Started Apr 18 03:41:21 PM PDT 24
Finished Apr 18 03:41:29 PM PDT 24
Peak memory 241848 kb
Host smart-2aa80ef0-6389-4a0c-87ec-3c404339d944
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=703042529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.703042529
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.1185211542
Short name T670
Test name
Test status
Simulation time 268360335 ps
CPU time 3.41 seconds
Started Apr 18 03:41:17 PM PDT 24
Finished Apr 18 03:41:21 PM PDT 24
Peak memory 242192 kb
Host smart-11b6337f-aa93-4873-a795-ca8b9600f044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185211542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1185211542
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.2237058856
Short name T1156
Test name
Test status
Simulation time 225760953914 ps
CPU time 1159.19 seconds
Started Apr 18 03:41:21 PM PDT 24
Finished Apr 18 04:00:41 PM PDT 24
Peak memory 312828 kb
Host smart-d87e465d-5f62-47f3-b163-22836101d195
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237058856 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.2237058856
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.1050293824
Short name T414
Test name
Test status
Simulation time 467615917 ps
CPU time 9.09 seconds
Started Apr 18 03:41:20 PM PDT 24
Finished Apr 18 03:41:29 PM PDT 24
Peak memory 241784 kb
Host smart-560fa509-f30e-4810-ba82-259195779415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050293824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.1050293824
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.392171717
Short name T1012
Test name
Test status
Simulation time 142195387 ps
CPU time 5.28 seconds
Started Apr 18 03:46:59 PM PDT 24
Finished Apr 18 03:47:05 PM PDT 24
Peak memory 241708 kb
Host smart-4d2ede84-e6b6-442f-bc54-4718a9e975b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392171717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.392171717
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.1840109481
Short name T1020
Test name
Test status
Simulation time 176026366 ps
CPU time 4.88 seconds
Started Apr 18 03:47:01 PM PDT 24
Finished Apr 18 03:47:06 PM PDT 24
Peak memory 241880 kb
Host smart-02b2f480-18d0-4889-be4d-a6718089ee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840109481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.1840109481
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.2425930336
Short name T839
Test name
Test status
Simulation time 173152536 ps
CPU time 4.11 seconds
Started Apr 18 03:46:58 PM PDT 24
Finished Apr 18 03:47:03 PM PDT 24
Peak memory 242008 kb
Host smart-d7308f56-d17a-49e0-a82e-47598a1fb16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425930336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.2425930336
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.1276212932
Short name T1043
Test name
Test status
Simulation time 268890347 ps
CPU time 5.23 seconds
Started Apr 18 03:46:58 PM PDT 24
Finished Apr 18 03:47:03 PM PDT 24
Peak memory 241928 kb
Host smart-f1ce7065-18c6-4a4f-b2ba-c26d2bb9f303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276212932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.1276212932
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.669278780
Short name T1143
Test name
Test status
Simulation time 251005234 ps
CPU time 3.7 seconds
Started Apr 18 03:46:59 PM PDT 24
Finished Apr 18 03:47:04 PM PDT 24
Peak memory 242168 kb
Host smart-5cbf2b71-b18e-46de-ac18-b64ab7ab1419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669278780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.669278780
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.1595560721
Short name T705
Test name
Test status
Simulation time 217672001 ps
CPU time 3.34 seconds
Started Apr 18 03:47:06 PM PDT 24
Finished Apr 18 03:47:10 PM PDT 24
Peak memory 242092 kb
Host smart-70218366-d1c8-4107-b97f-0725ed407f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595560721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.1595560721
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.3875551191
Short name T943
Test name
Test status
Simulation time 233586629 ps
CPU time 4.44 seconds
Started Apr 18 03:47:02 PM PDT 24
Finished Apr 18 03:47:07 PM PDT 24
Peak memory 241856 kb
Host smart-1999ca8d-31ff-4fbd-972d-461779ab8f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875551191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.3875551191
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.2237178990
Short name T1054
Test name
Test status
Simulation time 258371699 ps
CPU time 5.05 seconds
Started Apr 18 03:46:58 PM PDT 24
Finished Apr 18 03:47:04 PM PDT 24
Peak memory 242060 kb
Host smart-3eaecb4b-ae86-40c1-8f80-427bcb532ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237178990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.2237178990
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.1563106816
Short name T871
Test name
Test status
Simulation time 101688599 ps
CPU time 4.35 seconds
Started Apr 18 03:46:58 PM PDT 24
Finished Apr 18 03:47:03 PM PDT 24
Peak memory 241784 kb
Host smart-18983a9b-97b5-4ea8-9676-db2777cf9b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563106816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.1563106816
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.14227615
Short name T61
Test name
Test status
Simulation time 164154136 ps
CPU time 5.36 seconds
Started Apr 18 03:47:00 PM PDT 24
Finished Apr 18 03:47:06 PM PDT 24
Peak memory 242248 kb
Host smart-a18bff1a-93e9-4e28-a0f3-a30f44d60623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14227615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.14227615
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.2725695600
Short name T880
Test name
Test status
Simulation time 166763636 ps
CPU time 1.65 seconds
Started Apr 18 03:37:12 PM PDT 24
Finished Apr 18 03:37:14 PM PDT 24
Peak memory 240352 kb
Host smart-09860503-9967-4246-994b-beda7076214d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725695600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.2725695600
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.3760611580
Short name T1084
Test name
Test status
Simulation time 25736341492 ps
CPU time 54.24 seconds
Started Apr 18 03:37:00 PM PDT 24
Finished Apr 18 03:37:55 PM PDT 24
Peak memory 243684 kb
Host smart-2c5b8292-cba9-4180-818a-ded5d688748e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760611580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.3760611580
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.1677177563
Short name T987
Test name
Test status
Simulation time 3327254044 ps
CPU time 21.84 seconds
Started Apr 18 03:37:36 PM PDT 24
Finished Apr 18 03:37:58 PM PDT 24
Peak memory 242996 kb
Host smart-840f2ceb-10c6-4a04-8ee9-357bb7370598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677177563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1677177563
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.1132524672
Short name T945
Test name
Test status
Simulation time 2154968738 ps
CPU time 51.6 seconds
Started Apr 18 03:37:11 PM PDT 24
Finished Apr 18 03:38:03 PM PDT 24
Peak memory 255536 kb
Host smart-59404e1d-17c1-4055-a311-7ad74c942a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132524672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.1132524672
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.3847986843
Short name T815
Test name
Test status
Simulation time 3693117026 ps
CPU time 32.38 seconds
Started Apr 18 03:37:10 PM PDT 24
Finished Apr 18 03:37:42 PM PDT 24
Peak memory 242160 kb
Host smart-6d9ac7c3-58b6-4a85-8772-cd543c79d462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847986843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.3847986843
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.2005027299
Short name T81
Test name
Test status
Simulation time 2162950324 ps
CPU time 6.51 seconds
Started Apr 18 03:37:02 PM PDT 24
Finished Apr 18 03:37:09 PM PDT 24
Peak memory 241916 kb
Host smart-889a4393-d58d-4ca7-b012-e8fdf5624bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005027299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.2005027299
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.1660971399
Short name T769
Test name
Test status
Simulation time 3672748218 ps
CPU time 17.44 seconds
Started Apr 18 03:37:06 PM PDT 24
Finished Apr 18 03:37:24 PM PDT 24
Peak memory 243044 kb
Host smart-f006daec-4237-4661-9363-769b2703705c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660971399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.1660971399
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.447259336
Short name T377
Test name
Test status
Simulation time 10673819987 ps
CPU time 39.52 seconds
Started Apr 18 03:37:06 PM PDT 24
Finished Apr 18 03:37:46 PM PDT 24
Peak memory 243112 kb
Host smart-9c9fabc9-97ee-4d03-af45-94be595f62f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447259336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.447259336
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.1862125037
Short name T1044
Test name
Test status
Simulation time 490165784 ps
CPU time 4.75 seconds
Started Apr 18 03:37:09 PM PDT 24
Finished Apr 18 03:37:15 PM PDT 24
Peak memory 241880 kb
Host smart-647e6203-d949-4284-b2c4-63519ec85a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862125037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.1862125037
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.2747212048
Short name T1066
Test name
Test status
Simulation time 9428766944 ps
CPU time 31.58 seconds
Started Apr 18 03:37:01 PM PDT 24
Finished Apr 18 03:37:33 PM PDT 24
Peak memory 241852 kb
Host smart-4c80350a-d46f-4d99-a3c8-7591bf9b696e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747212048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.2747212048
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.436103353
Short name T353
Test name
Test status
Simulation time 555336627 ps
CPU time 9.67 seconds
Started Apr 18 03:37:06 PM PDT 24
Finished Apr 18 03:37:16 PM PDT 24
Peak memory 241888 kb
Host smart-3a19cf71-bbf3-4fde-82ae-76042b4c462c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=436103353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.436103353
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.165011965
Short name T675
Test name
Test status
Simulation time 411244292 ps
CPU time 5.31 seconds
Started Apr 18 03:37:00 PM PDT 24
Finished Apr 18 03:37:06 PM PDT 24
Peak memory 241840 kb
Host smart-532fabef-3099-4d62-82cf-8ae1dde616e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165011965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.165011965
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.2353007415
Short name T878
Test name
Test status
Simulation time 2843185030 ps
CPU time 66.66 seconds
Started Apr 18 03:37:11 PM PDT 24
Finished Apr 18 03:38:19 PM PDT 24
Peak memory 249208 kb
Host smart-3604c0a2-29e7-485f-a632-f2e72e2e4ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353007415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
2353007415
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.1092515278
Short name T475
Test name
Test status
Simulation time 31646917857 ps
CPU time 839.62 seconds
Started Apr 18 03:37:10 PM PDT 24
Finished Apr 18 03:51:11 PM PDT 24
Peak memory 248796 kb
Host smart-d408988e-3924-446e-9dbe-dc383b49073f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092515278 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.1092515278
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.215122174
Short name T870
Test name
Test status
Simulation time 1163591735 ps
CPU time 22.82 seconds
Started Apr 18 03:37:10 PM PDT 24
Finished Apr 18 03:37:34 PM PDT 24
Peak memory 241764 kb
Host smart-3ccea019-cc51-494c-889b-a3c1462cf46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215122174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.215122174
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.1145659549
Short name T230
Test name
Test status
Simulation time 47932660 ps
CPU time 1.67 seconds
Started Apr 18 03:41:25 PM PDT 24
Finished Apr 18 03:41:27 PM PDT 24
Peak memory 240148 kb
Host smart-5cf4c2a9-2f6b-49e7-9e29-b770fe4e563e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145659549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.1145659549
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.1050134236
Short name T132
Test name
Test status
Simulation time 1293263116 ps
CPU time 8.82 seconds
Started Apr 18 03:41:27 PM PDT 24
Finished Apr 18 03:41:36 PM PDT 24
Peak memory 248716 kb
Host smart-33677a35-4c88-4f95-bd86-9e0fc1d0ebef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050134236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1050134236
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.88462866
Short name T663
Test name
Test status
Simulation time 1378073028 ps
CPU time 11.5 seconds
Started Apr 18 03:41:26 PM PDT 24
Finished Apr 18 03:41:38 PM PDT 24
Peak memory 241656 kb
Host smart-b5c05c11-3133-418d-bdcf-7f450b152087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88462866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.88462866
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.786017634
Short name T814
Test name
Test status
Simulation time 383600463 ps
CPU time 13.56 seconds
Started Apr 18 03:41:27 PM PDT 24
Finished Apr 18 03:41:41 PM PDT 24
Peak memory 241692 kb
Host smart-f26d6d45-4887-42b4-92ad-536007df55dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786017634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.786017634
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.203897211
Short name T860
Test name
Test status
Simulation time 231104848 ps
CPU time 4.59 seconds
Started Apr 18 03:41:25 PM PDT 24
Finished Apr 18 03:41:30 PM PDT 24
Peak memory 241768 kb
Host smart-99048b9c-da5c-4559-b2fb-6658b70b1b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203897211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.203897211
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.4269991475
Short name T843
Test name
Test status
Simulation time 3493877372 ps
CPU time 47.85 seconds
Started Apr 18 03:41:25 PM PDT 24
Finished Apr 18 03:42:14 PM PDT 24
Peak memory 257852 kb
Host smart-b0cba9ec-a516-424a-bf4a-539339d92fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269991475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.4269991475
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.3631460316
Short name T438
Test name
Test status
Simulation time 2907553119 ps
CPU time 56.96 seconds
Started Apr 18 03:41:27 PM PDT 24
Finished Apr 18 03:42:25 PM PDT 24
Peak memory 242428 kb
Host smart-7f902dda-9b76-4908-8c01-cba3f3653512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631460316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.3631460316
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.2406693787
Short name T596
Test name
Test status
Simulation time 3457194321 ps
CPU time 8.45 seconds
Started Apr 18 03:41:26 PM PDT 24
Finished Apr 18 03:41:36 PM PDT 24
Peak memory 242112 kb
Host smart-ae1e8181-91be-4915-858a-caaaacf7dcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406693787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.2406693787
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.1355230260
Short name T939
Test name
Test status
Simulation time 12895567572 ps
CPU time 23.76 seconds
Started Apr 18 03:41:28 PM PDT 24
Finished Apr 18 03:41:52 PM PDT 24
Peak memory 241904 kb
Host smart-cceeddbb-b662-4ab3-b573-053faf03f40e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1355230260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.1355230260
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.1746283811
Short name T882
Test name
Test status
Simulation time 884310322 ps
CPU time 7.06 seconds
Started Apr 18 03:41:25 PM PDT 24
Finished Apr 18 03:41:32 PM PDT 24
Peak memory 242124 kb
Host smart-58adc954-9619-465a-aa8c-9d73728f7417
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1746283811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.1746283811
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.2428403978
Short name T407
Test name
Test status
Simulation time 249295517 ps
CPU time 5.55 seconds
Started Apr 18 03:41:25 PM PDT 24
Finished Apr 18 03:41:31 PM PDT 24
Peak memory 241836 kb
Host smart-bdb307a2-c02f-4664-9a5e-e2556cf2c4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428403978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.2428403978
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.2803066350
Short name T733
Test name
Test status
Simulation time 13099664300 ps
CPU time 93.13 seconds
Started Apr 18 03:41:27 PM PDT 24
Finished Apr 18 03:43:01 PM PDT 24
Peak memory 265316 kb
Host smart-bb9b5cf7-4ad1-4a59-a166-a3cb6802c2b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803066350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.2803066350
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.3177237787
Short name T478
Test name
Test status
Simulation time 675091711 ps
CPU time 22.58 seconds
Started Apr 18 03:41:26 PM PDT 24
Finished Apr 18 03:41:49 PM PDT 24
Peak memory 241828 kb
Host smart-6b2dfb3e-4d45-4215-b686-834cf79c7de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177237787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.3177237787
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.1045821832
Short name T488
Test name
Test status
Simulation time 781191585 ps
CPU time 2.28 seconds
Started Apr 18 03:41:36 PM PDT 24
Finished Apr 18 03:41:39 PM PDT 24
Peak memory 240228 kb
Host smart-6ef10d76-4149-419d-8622-9155d513758d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045821832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.1045821832
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.894836092
Short name T31
Test name
Test status
Simulation time 3089773841 ps
CPU time 33.42 seconds
Started Apr 18 03:41:33 PM PDT 24
Finished Apr 18 03:42:08 PM PDT 24
Peak memory 242104 kb
Host smart-89d73a46-756c-4b66-b26b-9303b88b46bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894836092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.894836092
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.2756142055
Short name T651
Test name
Test status
Simulation time 605751489 ps
CPU time 9.76 seconds
Started Apr 18 03:41:33 PM PDT 24
Finished Apr 18 03:41:44 PM PDT 24
Peak memory 242184 kb
Host smart-32b735e2-68fb-4515-bf8d-f5a726c191e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756142055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.2756142055
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.1869694222
Short name T637
Test name
Test status
Simulation time 1427901772 ps
CPU time 21.9 seconds
Started Apr 18 03:41:31 PM PDT 24
Finished Apr 18 03:41:53 PM PDT 24
Peak memory 242272 kb
Host smart-76b83370-e797-4edd-8a6e-4504892dbf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869694222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.1869694222
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.4242413146
Short name T247
Test name
Test status
Simulation time 1466750038 ps
CPU time 3.79 seconds
Started Apr 18 03:41:30 PM PDT 24
Finished Apr 18 03:41:34 PM PDT 24
Peak memory 242104 kb
Host smart-8883d928-6894-4991-bb1d-f21b8b3fbb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242413146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.4242413146
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.1425773025
Short name T827
Test name
Test status
Simulation time 4159514094 ps
CPU time 26.15 seconds
Started Apr 18 03:41:30 PM PDT 24
Finished Apr 18 03:41:57 PM PDT 24
Peak memory 248760 kb
Host smart-0e23afdd-a2d0-47d1-8c79-81985c8049e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425773025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.1425773025
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.3422464549
Short name T558
Test name
Test status
Simulation time 1395659512 ps
CPU time 35.77 seconds
Started Apr 18 03:41:32 PM PDT 24
Finished Apr 18 03:42:09 PM PDT 24
Peak memory 242368 kb
Host smart-a8f31bce-d66a-4c35-854f-1fb13ab7a63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422464549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.3422464549
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.235664372
Short name T1072
Test name
Test status
Simulation time 112098291 ps
CPU time 4.01 seconds
Started Apr 18 03:41:33 PM PDT 24
Finished Apr 18 03:41:38 PM PDT 24
Peak memory 241684 kb
Host smart-a65bfe51-857c-40bb-9a39-7347ea8d7cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235664372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.235664372
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.2574831261
Short name T672
Test name
Test status
Simulation time 1005391889 ps
CPU time 17.2 seconds
Started Apr 18 03:41:33 PM PDT 24
Finished Apr 18 03:41:51 PM PDT 24
Peak memory 241824 kb
Host smart-7fc63f8b-1fb0-4da7-9666-de34078c518b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2574831261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.2574831261
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.1359293665
Short name T636
Test name
Test status
Simulation time 144135050 ps
CPU time 3.57 seconds
Started Apr 18 03:41:32 PM PDT 24
Finished Apr 18 03:41:36 PM PDT 24
Peak memory 241916 kb
Host smart-3f47e220-4186-47b9-b4ac-23c404f8409f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359293665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.1359293665
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.3006301001
Short name T955
Test name
Test status
Simulation time 255172440 ps
CPU time 7.23 seconds
Started Apr 18 03:41:28 PM PDT 24
Finished Apr 18 03:41:35 PM PDT 24
Peak memory 242180 kb
Host smart-b4d371ec-9b5a-4d1d-bd06-5a27cdfb36d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006301001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.3006301001
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.366623489
Short name T872
Test name
Test status
Simulation time 52094820762 ps
CPU time 1275.74 seconds
Started Apr 18 03:41:36 PM PDT 24
Finished Apr 18 04:02:53 PM PDT 24
Peak memory 374848 kb
Host smart-e556a71f-5872-4517-965e-0319c2e009d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366623489 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.366623489
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.2794293078
Short name T373
Test name
Test status
Simulation time 15157395799 ps
CPU time 45.44 seconds
Started Apr 18 03:41:37 PM PDT 24
Finished Apr 18 03:42:23 PM PDT 24
Peak memory 242208 kb
Host smart-468c665b-cccc-4f5b-abf8-ffc8e2a83e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794293078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.2794293078
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.926567505
Short name T885
Test name
Test status
Simulation time 49415267 ps
CPU time 1.77 seconds
Started Apr 18 03:41:43 PM PDT 24
Finished Apr 18 03:41:45 PM PDT 24
Peak memory 240072 kb
Host smart-0d0557ff-7d70-4317-8dc4-8e78b7f77499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926567505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.926567505
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.148005464
Short name T668
Test name
Test status
Simulation time 283120261 ps
CPU time 8.56 seconds
Started Apr 18 03:41:41 PM PDT 24
Finished Apr 18 03:41:50 PM PDT 24
Peak memory 242484 kb
Host smart-ad5d45e9-571f-415d-8ef5-3865df8b4a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148005464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.148005464
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.2922687907
Short name T641
Test name
Test status
Simulation time 306232971 ps
CPU time 16.44 seconds
Started Apr 18 03:41:43 PM PDT 24
Finished Apr 18 03:42:00 PM PDT 24
Peak memory 242196 kb
Host smart-6bcc11a0-d0a2-49e2-9ad9-cb3910495bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922687907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.2922687907
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.2002454519
Short name T234
Test name
Test status
Simulation time 4870997445 ps
CPU time 30.05 seconds
Started Apr 18 03:41:37 PM PDT 24
Finished Apr 18 03:42:08 PM PDT 24
Peak memory 248708 kb
Host smart-65d7a5a6-f60f-4f03-a94d-892bc784813f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002454519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.2002454519
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.4280710579
Short name T803
Test name
Test status
Simulation time 122396830 ps
CPU time 3.75 seconds
Started Apr 18 03:41:37 PM PDT 24
Finished Apr 18 03:41:42 PM PDT 24
Peak memory 241840 kb
Host smart-469de0c6-b825-440a-9f63-c076479fa889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280710579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.4280710579
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.3185938993
Short name T160
Test name
Test status
Simulation time 4437844169 ps
CPU time 64.34 seconds
Started Apr 18 03:41:44 PM PDT 24
Finished Apr 18 03:42:49 PM PDT 24
Peak memory 257016 kb
Host smart-e52e8cf8-a287-422c-aa95-d18398e9f01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185938993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.3185938993
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.1462910422
Short name T884
Test name
Test status
Simulation time 4569187630 ps
CPU time 28.26 seconds
Started Apr 18 03:41:43 PM PDT 24
Finished Apr 18 03:42:11 PM PDT 24
Peak memory 243096 kb
Host smart-5ede8a60-532f-4851-8f29-bd87af5cbe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462910422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.1462910422
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.4166025251
Short name T804
Test name
Test status
Simulation time 12486371860 ps
CPU time 39.69 seconds
Started Apr 18 03:41:36 PM PDT 24
Finished Apr 18 03:42:17 PM PDT 24
Peak memory 241816 kb
Host smart-2b6df7a1-88d2-4ab8-a84c-81532c98c657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166025251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.4166025251
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.2300992957
Short name T735
Test name
Test status
Simulation time 2839773885 ps
CPU time 24.29 seconds
Started Apr 18 03:41:36 PM PDT 24
Finished Apr 18 03:42:01 PM PDT 24
Peak memory 248584 kb
Host smart-1ac16916-6c40-46d2-8c3c-e8ebd948b234
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2300992957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.2300992957
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.684093081
Short name T241
Test name
Test status
Simulation time 3386497296 ps
CPU time 6.89 seconds
Started Apr 18 03:41:43 PM PDT 24
Finished Apr 18 03:41:50 PM PDT 24
Peak memory 242012 kb
Host smart-cc40be0b-39d4-4768-8d4d-e82dd5c40477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684093081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.684093081
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.1890491934
Short name T694
Test name
Test status
Simulation time 157452866 ps
CPU time 5.81 seconds
Started Apr 18 03:41:37 PM PDT 24
Finished Apr 18 03:41:44 PM PDT 24
Peak memory 241980 kb
Host smart-bdb024f7-ac76-4b5e-b778-25ea7a6d9ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890491934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.1890491934
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.1285393706
Short name T540
Test name
Test status
Simulation time 31099737507 ps
CPU time 150.99 seconds
Started Apr 18 03:41:40 PM PDT 24
Finished Apr 18 03:44:12 PM PDT 24
Peak memory 250376 kb
Host smart-b901ba16-f4b3-418b-a2e1-ae2b7178be43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285393706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.1285393706
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.903670287
Short name T1016
Test name
Test status
Simulation time 443977913040 ps
CPU time 714.62 seconds
Started Apr 18 03:41:42 PM PDT 24
Finished Apr 18 03:53:38 PM PDT 24
Peak memory 300136 kb
Host smart-50ec85bd-205f-4f25-9962-a5fcdf41dd8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903670287 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.903670287
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.467308225
Short name T278
Test name
Test status
Simulation time 5993254936 ps
CPU time 16.13 seconds
Started Apr 18 03:41:42 PM PDT 24
Finished Apr 18 03:41:59 PM PDT 24
Peak memory 242820 kb
Host smart-c67fb236-e8cf-4c1f-afbb-393d7584503b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467308225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.467308225
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.2975451879
Short name T851
Test name
Test status
Simulation time 82490386 ps
CPU time 1.83 seconds
Started Apr 18 03:41:47 PM PDT 24
Finished Apr 18 03:41:50 PM PDT 24
Peak memory 240068 kb
Host smart-5c66c81f-9ada-4299-bb37-20d5a626ac9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975451879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.2975451879
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.478191285
Short name T603
Test name
Test status
Simulation time 5446596421 ps
CPU time 12.36 seconds
Started Apr 18 03:41:47 PM PDT 24
Finished Apr 18 03:42:00 PM PDT 24
Peak memory 248676 kb
Host smart-492898db-bc36-4d25-9025-c9c69ad0f296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478191285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.478191285
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.4023788899
Short name T748
Test name
Test status
Simulation time 203783674 ps
CPU time 9.11 seconds
Started Apr 18 03:41:46 PM PDT 24
Finished Apr 18 03:41:56 PM PDT 24
Peak memory 242168 kb
Host smart-12806cbb-b32b-486c-b947-b425853cd2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023788899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.4023788899
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.313158876
Short name T1078
Test name
Test status
Simulation time 1850256055 ps
CPU time 21.54 seconds
Started Apr 18 03:41:46 PM PDT 24
Finished Apr 18 03:42:08 PM PDT 24
Peak memory 242320 kb
Host smart-f07fa82c-11f0-407d-8360-8aa75f63a6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313158876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.313158876
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.2986070497
Short name T1112
Test name
Test status
Simulation time 145820109 ps
CPU time 4.05 seconds
Started Apr 18 03:41:42 PM PDT 24
Finished Apr 18 03:41:46 PM PDT 24
Peak memory 241908 kb
Host smart-8afbbc15-b6f3-49a7-bf65-4dfd32b1e638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986070497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.2986070497
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.3874344669
Short name T700
Test name
Test status
Simulation time 821245397 ps
CPU time 22.11 seconds
Started Apr 18 03:41:46 PM PDT 24
Finished Apr 18 03:42:09 PM PDT 24
Peak memory 243012 kb
Host smart-b201da1e-9e73-4958-9a04-c65f5303d038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874344669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.3874344669
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.3640789275
Short name T1088
Test name
Test status
Simulation time 793097587 ps
CPU time 14.34 seconds
Started Apr 18 03:41:49 PM PDT 24
Finished Apr 18 03:42:04 PM PDT 24
Peak memory 242136 kb
Host smart-627b261b-7988-4ef8-89f5-6d0764a4ce02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640789275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.3640789275
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.2915852999
Short name T810
Test name
Test status
Simulation time 138994681 ps
CPU time 5.84 seconds
Started Apr 18 03:41:46 PM PDT 24
Finished Apr 18 03:41:52 PM PDT 24
Peak memory 241740 kb
Host smart-dd27e006-18a0-4e92-b0a8-35d0813f6fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915852999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.2915852999
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.711242996
Short name T1157
Test name
Test status
Simulation time 2503448316 ps
CPU time 5.7 seconds
Started Apr 18 03:41:41 PM PDT 24
Finished Apr 18 03:41:48 PM PDT 24
Peak memory 241752 kb
Host smart-d032fba3-dc50-4a47-a0e3-df90f5a71eb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=711242996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.711242996
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.2998361162
Short name T572
Test name
Test status
Simulation time 374332537 ps
CPU time 6.45 seconds
Started Apr 18 03:41:46 PM PDT 24
Finished Apr 18 03:41:52 PM PDT 24
Peak memory 242224 kb
Host smart-2a3afb64-4640-411f-9d1f-f80895ce93d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2998361162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.2998361162
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.3071049580
Short name T984
Test name
Test status
Simulation time 126817999 ps
CPU time 3.69 seconds
Started Apr 18 03:41:42 PM PDT 24
Finished Apr 18 03:41:47 PM PDT 24
Peak memory 241892 kb
Host smart-bccfa19b-d985-4400-b637-6da146cce620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071049580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.3071049580
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.3546641464
Short name T469
Test name
Test status
Simulation time 3134447450 ps
CPU time 15.75 seconds
Started Apr 18 03:41:48 PM PDT 24
Finished Apr 18 03:42:05 PM PDT 24
Peak memory 241548 kb
Host smart-ed7ce272-34b1-46d6-b221-3a0d92c61b7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546641464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.3546641464
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.3261492817
Short name T1107
Test name
Test status
Simulation time 332038610 ps
CPU time 4.39 seconds
Started Apr 18 03:41:48 PM PDT 24
Finished Apr 18 03:41:53 PM PDT 24
Peak memory 241736 kb
Host smart-02c84049-35d7-4b3e-bf23-35dfbc6e8c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261492817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.3261492817
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.3833737703
Short name T451
Test name
Test status
Simulation time 194465955 ps
CPU time 2.36 seconds
Started Apr 18 03:42:00 PM PDT 24
Finished Apr 18 03:42:03 PM PDT 24
Peak memory 240364 kb
Host smart-2c8ec9d1-b7af-4c56-836b-0346f5147bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833737703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.3833737703
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.3898673843
Short name T44
Test name
Test status
Simulation time 21715421174 ps
CPU time 57.13 seconds
Started Apr 18 03:41:53 PM PDT 24
Finished Apr 18 03:42:51 PM PDT 24
Peak memory 248868 kb
Host smart-4e2a85cb-f64d-42f2-b666-7c49e217f99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898673843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.3898673843
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.3628370214
Short name T442
Test name
Test status
Simulation time 148431903 ps
CPU time 7.03 seconds
Started Apr 18 03:42:02 PM PDT 24
Finished Apr 18 03:42:10 PM PDT 24
Peak memory 241568 kb
Host smart-7055b6d8-ed1c-4140-855c-c6779d9d6564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628370214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.3628370214
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.549475867
Short name T1026
Test name
Test status
Simulation time 4462141860 ps
CPU time 30.89 seconds
Started Apr 18 03:41:54 PM PDT 24
Finished Apr 18 03:42:26 PM PDT 24
Peak memory 242264 kb
Host smart-a761d484-9975-47a2-bbe9-2bb9b24525f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549475867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.549475867
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.2313140306
Short name T507
Test name
Test status
Simulation time 148113687 ps
CPU time 4.56 seconds
Started Apr 18 03:41:48 PM PDT 24
Finished Apr 18 03:41:53 PM PDT 24
Peak memory 241792 kb
Host smart-7a581849-92c1-4245-b19a-f836c6223892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313140306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.2313140306
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.1744960623
Short name T598
Test name
Test status
Simulation time 1007142457 ps
CPU time 9.61 seconds
Started Apr 18 03:41:51 PM PDT 24
Finished Apr 18 03:42:01 PM PDT 24
Peak memory 241940 kb
Host smart-39189f37-1a4e-4e7a-b4bd-ff9cf9efca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744960623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.1744960623
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.3462113004
Short name T584
Test name
Test status
Simulation time 202127956 ps
CPU time 7.75 seconds
Started Apr 18 03:41:52 PM PDT 24
Finished Apr 18 03:42:00 PM PDT 24
Peak memory 241752 kb
Host smart-ab357a8b-3c66-46da-ad3d-a743d19f38ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462113004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3462113004
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.3604012
Short name T711
Test name
Test status
Simulation time 456439439 ps
CPU time 5.39 seconds
Started Apr 18 03:41:49 PM PDT 24
Finished Apr 18 03:41:55 PM PDT 24
Peak memory 241812 kb
Host smart-82bd332b-19e6-44de-8cc3-bf72fdd91c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.3604012
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.4152662686
Short name T462
Test name
Test status
Simulation time 2455106095 ps
CPU time 19.15 seconds
Started Apr 18 03:41:45 PM PDT 24
Finished Apr 18 03:42:05 PM PDT 24
Peak memory 241792 kb
Host smart-16568b49-e743-4676-a6c4-8779c58c03a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4152662686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.4152662686
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.662104926
Short name T463
Test name
Test status
Simulation time 173226219 ps
CPU time 6.61 seconds
Started Apr 18 03:41:54 PM PDT 24
Finished Apr 18 03:42:02 PM PDT 24
Peak memory 241840 kb
Host smart-3345e23a-3d12-4327-a0ba-f100617647e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662104926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.662104926
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.3317270686
Short name T395
Test name
Test status
Simulation time 1710050778 ps
CPU time 5.29 seconds
Started Apr 18 03:41:47 PM PDT 24
Finished Apr 18 03:41:53 PM PDT 24
Peak memory 241784 kb
Host smart-0d9f503d-3e3e-4457-bc4b-5da644e40604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317270686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.3317270686
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.410693708
Short name T838
Test name
Test status
Simulation time 36215903850 ps
CPU time 286.21 seconds
Started Apr 18 03:41:58 PM PDT 24
Finished Apr 18 03:46:45 PM PDT 24
Peak memory 273356 kb
Host smart-b5713518-6fbb-4a07-bf68-269775f74a5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410693708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.
410693708
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.3767737066
Short name T792
Test name
Test status
Simulation time 262519444 ps
CPU time 7.29 seconds
Started Apr 18 03:41:53 PM PDT 24
Finished Apr 18 03:42:01 PM PDT 24
Peak memory 241676 kb
Host smart-fc1655d9-2dc7-4707-b033-c19269bc064b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767737066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.3767737066
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.151119956
Short name T638
Test name
Test status
Simulation time 136399518 ps
CPU time 1.65 seconds
Started Apr 18 03:42:02 PM PDT 24
Finished Apr 18 03:42:04 PM PDT 24
Peak memory 240176 kb
Host smart-7c7c7f07-bd9b-4111-9070-3f2d6c8136e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151119956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.151119956
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.62807028
Short name T117
Test name
Test status
Simulation time 6271590142 ps
CPU time 43.95 seconds
Started Apr 18 03:42:01 PM PDT 24
Finished Apr 18 03:42:46 PM PDT 24
Peak memory 242344 kb
Host smart-0299a754-5eeb-474a-8f05-a26de82c2f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62807028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.62807028
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.2230500105
Short name T727
Test name
Test status
Simulation time 992423914 ps
CPU time 13.7 seconds
Started Apr 18 03:42:00 PM PDT 24
Finished Apr 18 03:42:14 PM PDT 24
Peak memory 242236 kb
Host smart-33876473-7389-4b7e-8813-4a8abebdfe56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230500105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.2230500105
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.3079098241
Short name T393
Test name
Test status
Simulation time 324101617 ps
CPU time 7.62 seconds
Started Apr 18 03:41:56 PM PDT 24
Finished Apr 18 03:42:05 PM PDT 24
Peak memory 242072 kb
Host smart-394f7162-7e8c-48f8-b41c-ba5ce9eb6f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079098241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.3079098241
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.2511829654
Short name T479
Test name
Test status
Simulation time 3021705082 ps
CPU time 7.92 seconds
Started Apr 18 03:41:57 PM PDT 24
Finished Apr 18 03:42:05 PM PDT 24
Peak memory 241804 kb
Host smart-70fa63ee-910c-48eb-b177-b7237eb8f508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511829654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.2511829654
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.3184579913
Short name T161
Test name
Test status
Simulation time 1379080602 ps
CPU time 16.52 seconds
Started Apr 18 03:42:04 PM PDT 24
Finished Apr 18 03:42:21 PM PDT 24
Peak memory 243352 kb
Host smart-d5b42c9f-34c3-4873-977e-a829a2e212a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184579913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.3184579913
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.3160254319
Short name T577
Test name
Test status
Simulation time 721386711 ps
CPU time 8.38 seconds
Started Apr 18 03:42:05 PM PDT 24
Finished Apr 18 03:42:14 PM PDT 24
Peak memory 242236 kb
Host smart-937fe860-7178-429a-9b84-fb1196a0da2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160254319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.3160254319
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.3431175739
Short name T575
Test name
Test status
Simulation time 2659322997 ps
CPU time 9.46 seconds
Started Apr 18 03:41:58 PM PDT 24
Finished Apr 18 03:42:08 PM PDT 24
Peak memory 241620 kb
Host smart-f59536a1-c6c3-47fe-bc22-3fe8ebd8fa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431175739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.3431175739
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.4188444357
Short name T1053
Test name
Test status
Simulation time 3310817770 ps
CPU time 27.62 seconds
Started Apr 18 03:41:59 PM PDT 24
Finished Apr 18 03:42:27 PM PDT 24
Peak memory 242196 kb
Host smart-f12d3cf5-b4b4-4dcb-912f-bb1b2059b6b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188444357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.4188444357
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.2177296853
Short name T357
Test name
Test status
Simulation time 178249756 ps
CPU time 7.14 seconds
Started Apr 18 03:42:02 PM PDT 24
Finished Apr 18 03:42:09 PM PDT 24
Peak memory 241908 kb
Host smart-e479483f-facb-47cf-939c-e22b0b5da916
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177296853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.2177296853
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.1513428288
Short name T408
Test name
Test status
Simulation time 957706025 ps
CPU time 7.2 seconds
Started Apr 18 03:41:57 PM PDT 24
Finished Apr 18 03:42:05 PM PDT 24
Peak memory 241892 kb
Host smart-c1f2167d-7a3f-46d2-a3a6-1a0b827c3dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513428288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1513428288
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.773212734
Short name T755
Test name
Test status
Simulation time 1153837624 ps
CPU time 16.71 seconds
Started Apr 18 03:42:03 PM PDT 24
Finished Apr 18 03:42:20 PM PDT 24
Peak memory 242136 kb
Host smart-76089b69-7368-4ece-b84a-5843aad7c7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773212734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.773212734
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.2185317035
Short name T701
Test name
Test status
Simulation time 126586222 ps
CPU time 2.12 seconds
Started Apr 18 03:42:12 PM PDT 24
Finished Apr 18 03:42:14 PM PDT 24
Peak memory 240112 kb
Host smart-9c93f346-df91-4284-bdbd-9e67b7f3c257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185317035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.2185317035
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.514950303
Short name T162
Test name
Test status
Simulation time 926951252 ps
CPU time 11.76 seconds
Started Apr 18 03:42:06 PM PDT 24
Finished Apr 18 03:42:18 PM PDT 24
Peak memory 241616 kb
Host smart-7c97ccda-f375-4151-9c21-ed39994b796f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514950303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.514950303
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.710847788
Short name T1110
Test name
Test status
Simulation time 957441075 ps
CPU time 18.64 seconds
Started Apr 18 03:42:08 PM PDT 24
Finished Apr 18 03:42:27 PM PDT 24
Peak memory 241748 kb
Host smart-91f77f8b-e23f-463f-a352-5cd16ae511b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710847788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.710847788
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.3459769866
Short name T993
Test name
Test status
Simulation time 124818794 ps
CPU time 3.17 seconds
Started Apr 18 03:42:03 PM PDT 24
Finished Apr 18 03:42:07 PM PDT 24
Peak memory 241716 kb
Host smart-42b3e5ba-ec65-40f1-a942-71c15db05c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459769866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3459769866
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.688440094
Short name T660
Test name
Test status
Simulation time 153781104 ps
CPU time 4.1 seconds
Started Apr 18 03:42:09 PM PDT 24
Finished Apr 18 03:42:14 PM PDT 24
Peak memory 241788 kb
Host smart-0637b22c-d965-4dad-83f0-3207f268c610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688440094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.688440094
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.1742442619
Short name T1196
Test name
Test status
Simulation time 2069203670 ps
CPU time 22.14 seconds
Started Apr 18 03:42:08 PM PDT 24
Finished Apr 18 03:42:31 PM PDT 24
Peak memory 242196 kb
Host smart-989ff260-fa90-4c28-8207-f5b2eafc5c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742442619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1742442619
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.1617551402
Short name T321
Test name
Test status
Simulation time 114434587 ps
CPU time 3.67 seconds
Started Apr 18 03:42:09 PM PDT 24
Finished Apr 18 03:42:13 PM PDT 24
Peak memory 241680 kb
Host smart-1fed2a19-acd0-403b-a8df-3c80d4bc6407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617551402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.1617551402
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.2304140792
Short name T108
Test name
Test status
Simulation time 1193534469 ps
CPU time 18.89 seconds
Started Apr 18 03:42:10 PM PDT 24
Finished Apr 18 03:42:29 PM PDT 24
Peak memory 242032 kb
Host smart-ecd6e0c5-c0f7-4dfa-812f-8c7b1d302c1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2304140792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.2304140792
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.555521797
Short name T847
Test name
Test status
Simulation time 987566432 ps
CPU time 8.28 seconds
Started Apr 18 03:42:14 PM PDT 24
Finished Apr 18 03:42:23 PM PDT 24
Peak memory 241964 kb
Host smart-c2c62309-0bfd-448f-88e5-9855c8384251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=555521797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.555521797
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.2159724788
Short name T1131
Test name
Test status
Simulation time 223188699 ps
CPU time 3.91 seconds
Started Apr 18 03:42:06 PM PDT 24
Finished Apr 18 03:42:10 PM PDT 24
Peak memory 241772 kb
Host smart-26a1b6ee-114e-47b7-9970-21040997efc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159724788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.2159724788
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.2263462401
Short name T920
Test name
Test status
Simulation time 37408617403 ps
CPU time 666.1 seconds
Started Apr 18 03:42:11 PM PDT 24
Finished Apr 18 03:53:18 PM PDT 24
Peak memory 307300 kb
Host smart-68d3ece4-05a5-4ac0-916c-86a2b9b5069c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263462401 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.2263462401
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.1367521946
Short name T389
Test name
Test status
Simulation time 249436928 ps
CPU time 3.11 seconds
Started Apr 18 03:42:12 PM PDT 24
Finished Apr 18 03:42:15 PM PDT 24
Peak memory 241728 kb
Host smart-fcd59be6-8910-4757-9500-e8c9c3d7ee6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367521946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.1367521946
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.2714520852
Short name T960
Test name
Test status
Simulation time 67447808 ps
CPU time 2 seconds
Started Apr 18 03:42:23 PM PDT 24
Finished Apr 18 03:42:25 PM PDT 24
Peak memory 240088 kb
Host smart-0b041c36-9ead-4090-882c-64c5f0460fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714520852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2714520852
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.3602077026
Short name T956
Test name
Test status
Simulation time 362116566 ps
CPU time 13.3 seconds
Started Apr 18 03:42:17 PM PDT 24
Finished Apr 18 03:42:31 PM PDT 24
Peak memory 248700 kb
Host smart-e0cf5214-d1ea-4c5b-a937-26e07d5965b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602077026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.3602077026
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.2925762875
Short name T822
Test name
Test status
Simulation time 1489977644 ps
CPU time 23.28 seconds
Started Apr 18 03:42:18 PM PDT 24
Finished Apr 18 03:42:42 PM PDT 24
Peak memory 242376 kb
Host smart-b0a39931-3170-4b24-af15-3e09e63fc8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925762875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.2925762875
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.1236381096
Short name T802
Test name
Test status
Simulation time 1117447239 ps
CPU time 19.9 seconds
Started Apr 18 03:42:13 PM PDT 24
Finished Apr 18 03:42:33 PM PDT 24
Peak memory 241772 kb
Host smart-f330967d-fc0c-4bb4-b828-79aacde7dfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236381096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.1236381096
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.1050967692
Short name T138
Test name
Test status
Simulation time 530617947 ps
CPU time 5.09 seconds
Started Apr 18 03:42:12 PM PDT 24
Finished Apr 18 03:42:18 PM PDT 24
Peak memory 241956 kb
Host smart-f177eccc-eadd-48de-a7b1-d36854e0cbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050967692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.1050967692
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.2322126844
Short name T1092
Test name
Test status
Simulation time 2029466965 ps
CPU time 30.68 seconds
Started Apr 18 03:42:20 PM PDT 24
Finished Apr 18 03:42:51 PM PDT 24
Peak memory 242288 kb
Host smart-bf696054-f157-4db9-a66e-0a97ce2ba064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322126844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.2322126844
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.4042099883
Short name T553
Test name
Test status
Simulation time 8506754530 ps
CPU time 31.33 seconds
Started Apr 18 03:42:16 PM PDT 24
Finished Apr 18 03:42:48 PM PDT 24
Peak memory 241812 kb
Host smart-036bf522-0814-4b84-9620-6c03f454d5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042099883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.4042099883
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.2583344578
Short name T410
Test name
Test status
Simulation time 1997967455 ps
CPU time 8.75 seconds
Started Apr 18 03:42:12 PM PDT 24
Finished Apr 18 03:42:21 PM PDT 24
Peak memory 241668 kb
Host smart-010b3021-0a91-4a8c-b6c7-562346d464da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583344578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.2583344578
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.3221919942
Short name T1140
Test name
Test status
Simulation time 3020849204 ps
CPU time 29.13 seconds
Started Apr 18 03:42:11 PM PDT 24
Finished Apr 18 03:42:41 PM PDT 24
Peak memory 242228 kb
Host smart-3f3e75cc-0b48-4ef4-abf0-02ed8687ab9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3221919942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.3221919942
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.3704996880
Short name T360
Test name
Test status
Simulation time 1164181891 ps
CPU time 10.01 seconds
Started Apr 18 03:42:20 PM PDT 24
Finished Apr 18 03:42:30 PM PDT 24
Peak memory 241816 kb
Host smart-1743ab4d-b650-43d9-bbf7-f1e7ac9cc8e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3704996880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.3704996880
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.2417696631
Short name T589
Test name
Test status
Simulation time 232817694 ps
CPU time 3.14 seconds
Started Apr 18 03:42:12 PM PDT 24
Finished Apr 18 03:42:16 PM PDT 24
Peak memory 241836 kb
Host smart-e4874d6b-b839-4812-98b9-1bb79da141fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417696631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.2417696631
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.2678060830
Short name T1185
Test name
Test status
Simulation time 53397267824 ps
CPU time 83.26 seconds
Started Apr 18 03:42:22 PM PDT 24
Finished Apr 18 03:43:45 PM PDT 24
Peak memory 255808 kb
Host smart-b6205179-f080-42cf-8a7a-ff5f84d34593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678060830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.2678060830
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.821790911
Short name T270
Test name
Test status
Simulation time 148586810327 ps
CPU time 1471.27 seconds
Started Apr 18 03:42:22 PM PDT 24
Finished Apr 18 04:06:53 PM PDT 24
Peak memory 268760 kb
Host smart-d0033705-d15a-4848-a967-f60b44826b10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821790911 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.821790911
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.1020957336
Short name T1113
Test name
Test status
Simulation time 1603888002 ps
CPU time 25.88 seconds
Started Apr 18 03:42:22 PM PDT 24
Finished Apr 18 03:42:48 PM PDT 24
Peak memory 242024 kb
Host smart-a800fa68-ee11-4c60-8fde-a814466379e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020957336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.1020957336
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.3025599928
Short name T1059
Test name
Test status
Simulation time 588490082 ps
CPU time 1.93 seconds
Started Apr 18 03:42:27 PM PDT 24
Finished Apr 18 03:42:30 PM PDT 24
Peak memory 240316 kb
Host smart-e66bd54a-d573-4546-ab06-d5ea10886e19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025599928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.3025599928
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.3631641448
Short name T114
Test name
Test status
Simulation time 12656069969 ps
CPU time 24.39 seconds
Started Apr 18 03:42:25 PM PDT 24
Finished Apr 18 03:42:50 PM PDT 24
Peak memory 243844 kb
Host smart-96392bca-eb41-4a7f-9eba-b27936edf60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631641448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3631641448
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.1876808402
Short name T707
Test name
Test status
Simulation time 4566529748 ps
CPU time 23.94 seconds
Started Apr 18 03:42:23 PM PDT 24
Finished Apr 18 03:42:47 PM PDT 24
Peak memory 241880 kb
Host smart-668d4f64-559b-4a5c-aa2b-74326c57f846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876808402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.1876808402
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.3930391385
Short name T559
Test name
Test status
Simulation time 1794051419 ps
CPU time 25.25 seconds
Started Apr 18 03:42:24 PM PDT 24
Finished Apr 18 03:42:49 PM PDT 24
Peak memory 242188 kb
Host smart-c300b82c-bd98-4502-be71-6a87483ce670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930391385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.3930391385
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.2384671392
Short name T892
Test name
Test status
Simulation time 812403161 ps
CPU time 5.55 seconds
Started Apr 18 03:42:24 PM PDT 24
Finished Apr 18 03:42:30 PM PDT 24
Peak memory 242140 kb
Host smart-990884a0-6fc2-4441-847b-a0cbe2e724dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384671392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.2384671392
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.2608952793
Short name T952
Test name
Test status
Simulation time 562133069 ps
CPU time 13.25 seconds
Started Apr 18 03:42:28 PM PDT 24
Finished Apr 18 03:42:41 PM PDT 24
Peak memory 242036 kb
Host smart-567fb223-48cb-4671-b5d6-fd5b8bf8b6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608952793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.2608952793
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.3805662149
Short name T1105
Test name
Test status
Simulation time 108217152 ps
CPU time 5.28 seconds
Started Apr 18 03:42:24 PM PDT 24
Finished Apr 18 03:42:30 PM PDT 24
Peak memory 242036 kb
Host smart-add0af60-9899-4c23-849d-d183710ef512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805662149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.3805662149
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.3440237116
Short name T472
Test name
Test status
Simulation time 2361699747 ps
CPU time 19.37 seconds
Started Apr 18 03:42:23 PM PDT 24
Finished Apr 18 03:42:43 PM PDT 24
Peak memory 242072 kb
Host smart-7baffcd3-b719-44fd-b66a-e52f063ed751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440237116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.3440237116
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.2918630841
Short name T355
Test name
Test status
Simulation time 173978236 ps
CPU time 6.68 seconds
Started Apr 18 03:42:27 PM PDT 24
Finished Apr 18 03:42:34 PM PDT 24
Peak memory 241968 kb
Host smart-5f5559a7-9f01-439b-8dfb-bdc72ee39da9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2918630841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.2918630841
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.3880504407
Short name T1192
Test name
Test status
Simulation time 165332347 ps
CPU time 6.16 seconds
Started Apr 18 03:42:23 PM PDT 24
Finished Apr 18 03:42:29 PM PDT 24
Peak memory 241820 kb
Host smart-ac754c2f-77c1-4de7-a7a3-2ef004d3eb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880504407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.3880504407
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.1282316142
Short name T642
Test name
Test status
Simulation time 2614031654 ps
CPU time 59.38 seconds
Started Apr 18 03:42:26 PM PDT 24
Finished Apr 18 03:43:26 PM PDT 24
Peak memory 246208 kb
Host smart-5844e9f8-e9d7-4fba-b5d1-62319d86a8bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282316142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.1282316142
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.982795783
Short name T277
Test name
Test status
Simulation time 239000164673 ps
CPU time 976.34 seconds
Started Apr 18 03:42:28 PM PDT 24
Finished Apr 18 03:58:44 PM PDT 24
Peak memory 312216 kb
Host smart-18411122-1f15-45cb-93b8-af8bf0d87fa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982795783 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.982795783
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.1058295333
Short name T798
Test name
Test status
Simulation time 5500951018 ps
CPU time 43.01 seconds
Started Apr 18 03:42:30 PM PDT 24
Finished Apr 18 03:43:13 PM PDT 24
Peak memory 242320 kb
Host smart-085a8b6d-0222-4b06-a536-7dec0a5c292e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058295333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.1058295333
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.4119710036
Short name T632
Test name
Test status
Simulation time 78630612 ps
CPU time 1.64 seconds
Started Apr 18 03:42:32 PM PDT 24
Finished Apr 18 03:42:34 PM PDT 24
Peak memory 240440 kb
Host smart-9d4b5a5c-69d3-434f-8cfd-fa1e9b012452
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119710036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.4119710036
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.4074819513
Short name T113
Test name
Test status
Simulation time 690101287 ps
CPU time 28.12 seconds
Started Apr 18 03:42:33 PM PDT 24
Finished Apr 18 03:43:02 PM PDT 24
Peak memory 241888 kb
Host smart-db6e77b8-f166-4b3c-b7be-6116e8248e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074819513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.4074819513
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.2479767013
Short name T332
Test name
Test status
Simulation time 2085594227 ps
CPU time 25.04 seconds
Started Apr 18 03:42:32 PM PDT 24
Finished Apr 18 03:42:57 PM PDT 24
Peak memory 241784 kb
Host smart-ca70edc1-d73b-4141-a6e1-ae1a081351e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479767013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.2479767013
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.46224233
Short name T1014
Test name
Test status
Simulation time 1121799916 ps
CPU time 10.48 seconds
Started Apr 18 03:42:27 PM PDT 24
Finished Apr 18 03:42:38 PM PDT 24
Peak memory 241760 kb
Host smart-1e3fafab-b69a-4849-86cc-d27729ed459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46224233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.46224233
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.522349443
Short name T788
Test name
Test status
Simulation time 107242534 ps
CPU time 4.36 seconds
Started Apr 18 03:42:30 PM PDT 24
Finished Apr 18 03:42:35 PM PDT 24
Peak memory 241800 kb
Host smart-5e9568eb-9bf4-4a45-a078-c93a62791b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522349443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.522349443
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.3663958256
Short name T902
Test name
Test status
Simulation time 9590973864 ps
CPU time 25.43 seconds
Started Apr 18 03:42:32 PM PDT 24
Finished Apr 18 03:42:58 PM PDT 24
Peak memory 243200 kb
Host smart-15a215c0-b8e3-43d5-b48e-dcd1abdea588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663958256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.3663958256
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.855557204
Short name T1087
Test name
Test status
Simulation time 476058532 ps
CPU time 10.98 seconds
Started Apr 18 03:42:29 PM PDT 24
Finished Apr 18 03:42:40 PM PDT 24
Peak memory 241816 kb
Host smart-b32a78ee-207a-4f26-8bf8-ec730d4adeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855557204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.855557204
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.4201813128
Short name T109
Test name
Test status
Simulation time 7530114322 ps
CPU time 18.52 seconds
Started Apr 18 03:42:29 PM PDT 24
Finished Apr 18 03:42:47 PM PDT 24
Peak memory 241820 kb
Host smart-55643411-a30a-4bb5-99e8-955b32936a85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4201813128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.4201813128
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.2162927729
Short name T415
Test name
Test status
Simulation time 127025789 ps
CPU time 4.02 seconds
Started Apr 18 03:42:33 PM PDT 24
Finished Apr 18 03:42:37 PM PDT 24
Peak memory 241924 kb
Host smart-c9099c00-9f02-4a98-96e8-696af9343a35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2162927729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.2162927729
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.1544417300
Short name T867
Test name
Test status
Simulation time 495194714 ps
CPU time 4.26 seconds
Started Apr 18 03:42:29 PM PDT 24
Finished Apr 18 03:42:34 PM PDT 24
Peak memory 242184 kb
Host smart-742e3224-4d7f-4448-9964-0e9d054f078e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544417300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.1544417300
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.643176528
Short name T336
Test name
Test status
Simulation time 40818150693 ps
CPU time 189.72 seconds
Started Apr 18 03:42:34 PM PDT 24
Finished Apr 18 03:45:44 PM PDT 24
Peak memory 257076 kb
Host smart-c2e2eac2-e57c-4553-939d-2878c486c9bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643176528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.
643176528
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.1277621044
Short name T136
Test name
Test status
Simulation time 87588158246 ps
CPU time 1153.36 seconds
Started Apr 18 03:42:32 PM PDT 24
Finished Apr 18 04:01:46 PM PDT 24
Peak memory 352764 kb
Host smart-840fb669-f4c1-4507-895f-214ddf3ca051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277621044 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.1277621044
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.510366234
Short name T896
Test name
Test status
Simulation time 2401909711 ps
CPU time 6.46 seconds
Started Apr 18 03:42:34 PM PDT 24
Finished Apr 18 03:42:41 PM PDT 24
Peak memory 241900 kb
Host smart-b897141c-a736-4345-9d1d-33565fe277d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510366234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.510366234
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.3237013521
Short name T586
Test name
Test status
Simulation time 756730265 ps
CPU time 2.25 seconds
Started Apr 18 03:37:36 PM PDT 24
Finished Apr 18 03:37:38 PM PDT 24
Peak memory 240100 kb
Host smart-c8bef99a-ddaa-4039-b431-a89a6e1f8c78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237013521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.3237013521
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.777688765
Short name T630
Test name
Test status
Simulation time 461018607 ps
CPU time 7.87 seconds
Started Apr 18 03:37:15 PM PDT 24
Finished Apr 18 03:37:23 PM PDT 24
Peak memory 241900 kb
Host smart-549f4cd0-925f-4070-8eb4-7f15b1286081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777688765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.777688765
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.1090448664
Short name T1080
Test name
Test status
Simulation time 483141898 ps
CPU time 3.91 seconds
Started Apr 18 03:37:21 PM PDT 24
Finished Apr 18 03:37:25 PM PDT 24
Peak memory 242128 kb
Host smart-68527640-a15a-415e-8346-4079b1142faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090448664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.1090448664
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.3878060599
Short name T946
Test name
Test status
Simulation time 1167946630 ps
CPU time 29.75 seconds
Started Apr 18 03:37:21 PM PDT 24
Finished Apr 18 03:37:52 PM PDT 24
Peak memory 242956 kb
Host smart-9af20902-e650-40a9-9a7a-e5b4ade80d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878060599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.3878060599
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.894596765
Short name T562
Test name
Test status
Simulation time 4177074591 ps
CPU time 25.04 seconds
Started Apr 18 03:37:22 PM PDT 24
Finished Apr 18 03:37:48 PM PDT 24
Peak memory 242148 kb
Host smart-b534173f-51c3-4b91-9bb6-fa3638b92651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894596765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.894596765
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.97072283
Short name T168
Test name
Test status
Simulation time 192522879 ps
CPU time 2.94 seconds
Started Apr 18 03:37:20 PM PDT 24
Finished Apr 18 03:37:24 PM PDT 24
Peak memory 242260 kb
Host smart-795e65dc-340a-4b25-89a6-44d5a871a732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97072283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.97072283
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.3407148076
Short name T899
Test name
Test status
Simulation time 1735631930 ps
CPU time 23.35 seconds
Started Apr 18 03:37:22 PM PDT 24
Finished Apr 18 03:37:46 PM PDT 24
Peak memory 242188 kb
Host smart-a53c2a77-c9ba-4266-8a39-fafe1d8b9a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407148076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.3407148076
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.1179149510
Short name T605
Test name
Test status
Simulation time 20798127460 ps
CPU time 35.6 seconds
Started Apr 18 03:37:30 PM PDT 24
Finished Apr 18 03:38:06 PM PDT 24
Peak memory 243264 kb
Host smart-020fd31d-75b6-4fc0-af16-672b87190853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179149510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.1179149510
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.608684282
Short name T128
Test name
Test status
Simulation time 976798267 ps
CPU time 6.19 seconds
Started Apr 18 03:37:16 PM PDT 24
Finished Apr 18 03:37:23 PM PDT 24
Peak memory 241752 kb
Host smart-137c5e0b-350b-4725-b39e-e1115ef80639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608684282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.608684282
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.2696066887
Short name T1116
Test name
Test status
Simulation time 849869719 ps
CPU time 14.66 seconds
Started Apr 18 03:37:17 PM PDT 24
Finished Apr 18 03:37:32 PM PDT 24
Peak memory 242012 kb
Host smart-4fae755f-8ecb-4435-a4a6-55a809b8ecb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2696066887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2696066887
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.1142463723
Short name T359
Test name
Test status
Simulation time 116674097 ps
CPU time 3.12 seconds
Started Apr 18 03:37:29 PM PDT 24
Finished Apr 18 03:37:33 PM PDT 24
Peak memory 241880 kb
Host smart-dbafc43e-f218-4976-a554-1b1b9125b85b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1142463723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1142463723
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.3835045852
Short name T25
Test name
Test status
Simulation time 9637208426 ps
CPU time 178.04 seconds
Started Apr 18 03:37:31 PM PDT 24
Finished Apr 18 03:40:30 PM PDT 24
Peak memory 265748 kb
Host smart-dfa0f045-8498-48aa-84da-0cb1bce20807
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835045852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3835045852
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.817329819
Short name T739
Test name
Test status
Simulation time 2027251966 ps
CPU time 5.69 seconds
Started Apr 18 03:37:12 PM PDT 24
Finished Apr 18 03:37:18 PM PDT 24
Peak memory 241768 kb
Host smart-db814569-e733-408b-b539-4c4d6be62acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817329819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.817329819
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.3599110639
Short name T254
Test name
Test status
Simulation time 20834471578 ps
CPU time 228.42 seconds
Started Apr 18 03:37:26 PM PDT 24
Finished Apr 18 03:41:14 PM PDT 24
Peak memory 257044 kb
Host smart-6f39341c-ff0a-4544-ab28-b69b668d192f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599110639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
3599110639
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.3393486177
Short name T129
Test name
Test status
Simulation time 84954315745 ps
CPU time 1312.99 seconds
Started Apr 18 03:37:29 PM PDT 24
Finished Apr 18 03:59:23 PM PDT 24
Peak memory 396400 kb
Host smart-c941d0e4-9a8c-44ef-98b7-6e8c3d71b600
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393486177 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.3393486177
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.638400946
Short name T910
Test name
Test status
Simulation time 2149493134 ps
CPU time 17.25 seconds
Started Apr 18 03:37:29 PM PDT 24
Finished Apr 18 03:37:47 PM PDT 24
Peak memory 241972 kb
Host smart-0dd218a0-0936-4a1d-8c8e-952f61ca6250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638400946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.638400946
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.145139959
Short name T995
Test name
Test status
Simulation time 214680914 ps
CPU time 2.35 seconds
Started Apr 18 03:42:38 PM PDT 24
Finished Apr 18 03:42:41 PM PDT 24
Peak memory 240080 kb
Host smart-1bff4d90-37f2-4470-a9b0-30c631bae624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145139959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.145139959
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.1272300843
Short name T1183
Test name
Test status
Simulation time 1375375949 ps
CPU time 16.46 seconds
Started Apr 18 03:42:36 PM PDT 24
Finished Apr 18 03:42:53 PM PDT 24
Peak memory 242564 kb
Host smart-67a35d60-2df0-4d84-b8a1-9123dffbeb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272300843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1272300843
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.2822881438
Short name T6
Test name
Test status
Simulation time 1668547590 ps
CPU time 42 seconds
Started Apr 18 03:42:41 PM PDT 24
Finished Apr 18 03:43:23 PM PDT 24
Peak memory 246152 kb
Host smart-2c678231-12cc-4422-9d9e-419a73e68b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822881438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.2822881438
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.3595343965
Short name T915
Test name
Test status
Simulation time 10225297512 ps
CPU time 28.42 seconds
Started Apr 18 03:42:38 PM PDT 24
Finished Apr 18 03:43:07 PM PDT 24
Peak memory 243380 kb
Host smart-d058507f-253d-4e4d-9216-7f766a55d29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595343965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.3595343965
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.103563813
Short name T681
Test name
Test status
Simulation time 144874064 ps
CPU time 4.96 seconds
Started Apr 18 03:42:37 PM PDT 24
Finished Apr 18 03:42:43 PM PDT 24
Peak memory 241660 kb
Host smart-10f8eff8-e230-4ea3-acd9-877916d6de92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103563813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.103563813
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.751575075
Short name T574
Test name
Test status
Simulation time 885778113 ps
CPU time 19.88 seconds
Started Apr 18 03:42:36 PM PDT 24
Finished Apr 18 03:42:56 PM PDT 24
Peak memory 242072 kb
Host smart-98f7172a-b96c-47ca-af3f-5c0e65138482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751575075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.751575075
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.4006562345
Short name T181
Test name
Test status
Simulation time 231552921 ps
CPU time 6.47 seconds
Started Apr 18 03:42:38 PM PDT 24
Finished Apr 18 03:42:44 PM PDT 24
Peak memory 242020 kb
Host smart-095391b2-080a-4227-a2c4-5add1176ec9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006562345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.4006562345
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.1746673186
Short name T585
Test name
Test status
Simulation time 2327854353 ps
CPU time 23.95 seconds
Started Apr 18 03:42:39 PM PDT 24
Finished Apr 18 03:43:03 PM PDT 24
Peak memory 241836 kb
Host smart-7af1a472-455f-4e4c-a2b0-923ccdaf33f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1746673186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.1746673186
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.548667912
Short name T416
Test name
Test status
Simulation time 2139443683 ps
CPU time 7.32 seconds
Started Apr 18 03:42:39 PM PDT 24
Finished Apr 18 03:42:46 PM PDT 24
Peak memory 241740 kb
Host smart-54ed88d2-cbf7-4af3-93a6-dc0561f025af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=548667912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.548667912
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.3671871071
Short name T98
Test name
Test status
Simulation time 262827200 ps
CPU time 3.67 seconds
Started Apr 18 03:42:33 PM PDT 24
Finished Apr 18 03:42:37 PM PDT 24
Peak memory 241936 kb
Host smart-870f570e-bae9-4e1e-a3c9-50f927101f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671871071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.3671871071
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.2153975090
Short name T467
Test name
Test status
Simulation time 4639173054 ps
CPU time 74.12 seconds
Started Apr 18 03:42:38 PM PDT 24
Finished Apr 18 03:43:53 PM PDT 24
Peak memory 245812 kb
Host smart-121f9286-ddfb-42ff-b32d-8400edfaae1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153975090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.2153975090
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.2310909709
Short name T280
Test name
Test status
Simulation time 123040627679 ps
CPU time 3372.6 seconds
Started Apr 18 03:42:41 PM PDT 24
Finished Apr 18 04:38:55 PM PDT 24
Peak memory 306700 kb
Host smart-4ae4d7c7-2209-4d96-8926-d72c65262ce0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310909709 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.2310909709
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.3001775952
Short name T1115
Test name
Test status
Simulation time 517367488 ps
CPU time 19.1 seconds
Started Apr 18 03:42:39 PM PDT 24
Finished Apr 18 03:42:58 PM PDT 24
Peak memory 241968 kb
Host smart-e9869369-c1dc-4bbc-9e4d-4ebc26329652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001775952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.3001775952
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.3008629767
Short name T564
Test name
Test status
Simulation time 785121443 ps
CPU time 14.35 seconds
Started Apr 18 03:42:42 PM PDT 24
Finished Apr 18 03:42:57 PM PDT 24
Peak memory 243876 kb
Host smart-63b87f6f-fb3b-4910-978c-c8780699bffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008629767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.3008629767
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.2403070610
Short name T492
Test name
Test status
Simulation time 1487476607 ps
CPU time 11.83 seconds
Started Apr 18 03:42:43 PM PDT 24
Finished Apr 18 03:42:55 PM PDT 24
Peak memory 241776 kb
Host smart-56e1119c-c6d0-4807-9f44-dacb7aa12175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403070610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.2403070610
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.2273191978
Short name T807
Test name
Test status
Simulation time 5177683916 ps
CPU time 31.94 seconds
Started Apr 18 03:42:42 PM PDT 24
Finished Apr 18 03:43:14 PM PDT 24
Peak memory 243532 kb
Host smart-7b970377-364f-48b2-ba72-f81ddf8bc00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273191978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.2273191978
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.625146393
Short name T772
Test name
Test status
Simulation time 121777848 ps
CPU time 3.62 seconds
Started Apr 18 03:42:44 PM PDT 24
Finished Apr 18 03:42:48 PM PDT 24
Peak memory 242132 kb
Host smart-340ac8cd-f314-4cf1-b693-c3c2922995a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625146393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.625146393
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.2042305278
Short name T163
Test name
Test status
Simulation time 873223132 ps
CPU time 6.69 seconds
Started Apr 18 03:42:42 PM PDT 24
Finished Apr 18 03:42:49 PM PDT 24
Peak memory 242188 kb
Host smart-85be05bf-7280-4c23-9ba6-44409a129fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042305278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.2042305278
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.1376818952
Short name T465
Test name
Test status
Simulation time 933927928 ps
CPU time 24.64 seconds
Started Apr 18 03:42:42 PM PDT 24
Finished Apr 18 03:43:07 PM PDT 24
Peak memory 248636 kb
Host smart-8703178b-5b22-4318-8740-c122fb1a9010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376818952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1376818952
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.3774156287
Short name T396
Test name
Test status
Simulation time 2896169659 ps
CPU time 8.09 seconds
Started Apr 18 03:42:41 PM PDT 24
Finished Apr 18 03:42:50 PM PDT 24
Peak memory 248564 kb
Host smart-982b8cc4-306f-4d87-892d-97046914fae9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3774156287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.3774156287
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.119631824
Short name T777
Test name
Test status
Simulation time 879582497 ps
CPU time 7.89 seconds
Started Apr 18 03:42:42 PM PDT 24
Finished Apr 18 03:42:51 PM PDT 24
Peak memory 241920 kb
Host smart-d60f54b2-4d5a-460f-a4ea-fa903585d2d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119631824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.119631824
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.3337690585
Short name T1184
Test name
Test status
Simulation time 321812053 ps
CPU time 10.78 seconds
Started Apr 18 03:42:45 PM PDT 24
Finished Apr 18 03:42:56 PM PDT 24
Peak memory 241872 kb
Host smart-96d75979-268f-4a66-bcd9-5af37f9bc764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337690585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.3337690585
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.3885414067
Short name T890
Test name
Test status
Simulation time 13704452333 ps
CPU time 173.74 seconds
Started Apr 18 03:42:47 PM PDT 24
Finished Apr 18 03:45:42 PM PDT 24
Peak memory 248668 kb
Host smart-f4b67702-4f05-469e-a708-898f40fc5dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885414067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.3885414067
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.2648767162
Short name T271
Test name
Test status
Simulation time 42064859793 ps
CPU time 1227.65 seconds
Started Apr 18 03:42:43 PM PDT 24
Finished Apr 18 04:03:12 PM PDT 24
Peak memory 308396 kb
Host smart-1245c31d-db89-4150-9b8e-52a3bee986ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648767162 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.2648767162
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.1061657498
Short name T811
Test name
Test status
Simulation time 2928148789 ps
CPU time 38.02 seconds
Started Apr 18 03:42:44 PM PDT 24
Finished Apr 18 03:43:23 PM PDT 24
Peak memory 242392 kb
Host smart-6dae2a28-800f-4037-b9f3-eab48c2cf0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061657498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.1061657498
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.3389470569
Short name T423
Test name
Test status
Simulation time 51080102 ps
CPU time 1.9 seconds
Started Apr 18 03:43:00 PM PDT 24
Finished Apr 18 03:43:02 PM PDT 24
Peak memory 240088 kb
Host smart-ea535d9f-aa7d-4b39-948d-7dc0ff857bf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389470569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.3389470569
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.767859918
Short name T50
Test name
Test status
Simulation time 2087065699 ps
CPU time 33.02 seconds
Started Apr 18 03:42:48 PM PDT 24
Finished Apr 18 03:43:22 PM PDT 24
Peak memory 242152 kb
Host smart-64715dd4-de0f-4149-a01a-fb0866b74d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767859918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.767859918
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.795610637
Short name T568
Test name
Test status
Simulation time 735465503 ps
CPU time 12.79 seconds
Started Apr 18 03:42:47 PM PDT 24
Finished Apr 18 03:43:01 PM PDT 24
Peak memory 241888 kb
Host smart-88b84adc-d32e-45df-b07b-b13f8a181d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795610637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.795610637
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.3910862171
Short name T379
Test name
Test status
Simulation time 12175283568 ps
CPU time 31.17 seconds
Started Apr 18 03:42:48 PM PDT 24
Finished Apr 18 03:43:19 PM PDT 24
Peak memory 242868 kb
Host smart-a1e31d14-5cb4-44fe-821f-981e0bdb6be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910862171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3910862171
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.396464903
Short name T504
Test name
Test status
Simulation time 541942376 ps
CPU time 4.44 seconds
Started Apr 18 03:42:47 PM PDT 24
Finished Apr 18 03:42:52 PM PDT 24
Peak memory 242200 kb
Host smart-3426008f-67ed-46cf-8053-2e5a4929dd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396464903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.396464903
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.4185667205
Short name T697
Test name
Test status
Simulation time 2667835132 ps
CPU time 27.02 seconds
Started Apr 18 03:42:55 PM PDT 24
Finished Apr 18 03:43:22 PM PDT 24
Peak memory 242240 kb
Host smart-ee410d9e-3275-47f4-bb1d-a123d3cda7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185667205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.4185667205
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.259945695
Short name T213
Test name
Test status
Simulation time 856401011 ps
CPU time 12.87 seconds
Started Apr 18 03:42:53 PM PDT 24
Finished Apr 18 03:43:06 PM PDT 24
Peak memory 241764 kb
Host smart-615a076f-73b8-4f5e-b903-8336c3b4726a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259945695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.259945695
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.182134758
Short name T942
Test name
Test status
Simulation time 4571511757 ps
CPU time 9.71 seconds
Started Apr 18 03:42:47 PM PDT 24
Finished Apr 18 03:42:57 PM PDT 24
Peak memory 241880 kb
Host smart-ed9bd6a6-8e03-49c1-89f3-2e8633b3f786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182134758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.182134758
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.1181642043
Short name T1130
Test name
Test status
Simulation time 4670070183 ps
CPU time 15.19 seconds
Started Apr 18 03:42:47 PM PDT 24
Finished Apr 18 03:43:03 PM PDT 24
Peak memory 241956 kb
Host smart-9172a49b-1dee-422b-906a-277383a8614e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1181642043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1181642043
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.3172329989
Short name T362
Test name
Test status
Simulation time 615051027 ps
CPU time 10.64 seconds
Started Apr 18 03:42:54 PM PDT 24
Finished Apr 18 03:43:05 PM PDT 24
Peak memory 241832 kb
Host smart-dae0e29e-aae6-4528-9aee-da3e4b363e16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3172329989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.3172329989
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.3212977967
Short name T1063
Test name
Test status
Simulation time 1342112889 ps
CPU time 7.34 seconds
Started Apr 18 03:42:47 PM PDT 24
Finished Apr 18 03:42:55 PM PDT 24
Peak memory 241644 kb
Host smart-2def89e5-0ebe-4e13-9455-dcd1685f3277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212977967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.3212977967
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.1642755007
Short name T124
Test name
Test status
Simulation time 36473476219 ps
CPU time 189.55 seconds
Started Apr 18 03:42:59 PM PDT 24
Finished Apr 18 03:46:09 PM PDT 24
Peak memory 257292 kb
Host smart-0cec1718-833c-451c-a4e0-c345c9da0c66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642755007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.1642755007
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.2121039796
Short name T687
Test name
Test status
Simulation time 1208732822199 ps
CPU time 2444.89 seconds
Started Apr 18 03:42:53 PM PDT 24
Finished Apr 18 04:23:39 PM PDT 24
Peak memory 511028 kb
Host smart-18d88149-3fa7-4391-8e9a-0d55ea547d0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121039796 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.2121039796
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.1152066504
Short name T281
Test name
Test status
Simulation time 2875587862 ps
CPU time 30.12 seconds
Started Apr 18 03:42:53 PM PDT 24
Finished Apr 18 03:43:23 PM PDT 24
Peak memory 241804 kb
Host smart-f4a6b2e3-5d82-41a5-bb96-e7bd3608c909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152066504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.1152066504
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.2485941759
Short name T706
Test name
Test status
Simulation time 985521854 ps
CPU time 2.63 seconds
Started Apr 18 03:43:03 PM PDT 24
Finished Apr 18 03:43:07 PM PDT 24
Peak memory 240436 kb
Host smart-24f2ec96-a38b-4a9f-8c99-e4b3dac2e82b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485941759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.2485941759
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.3771109712
Short name T759
Test name
Test status
Simulation time 4342632937 ps
CPU time 36.05 seconds
Started Apr 18 03:42:58 PM PDT 24
Finished Apr 18 03:43:34 PM PDT 24
Peak memory 242060 kb
Host smart-f66b969b-6cad-4bfc-9f9b-45990cc6e88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771109712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.3771109712
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.448140665
Short name T87
Test name
Test status
Simulation time 367504140 ps
CPU time 5.07 seconds
Started Apr 18 03:42:59 PM PDT 24
Finished Apr 18 03:43:04 PM PDT 24
Peak memory 242096 kb
Host smart-90abe9ef-bfa4-4202-a6ef-3c77ad6bca3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448140665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.448140665
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.3146729536
Short name T695
Test name
Test status
Simulation time 1558559513 ps
CPU time 14.77 seconds
Started Apr 18 03:42:57 PM PDT 24
Finished Apr 18 03:43:13 PM PDT 24
Peak memory 242000 kb
Host smart-1cd6d150-39c3-44aa-8b60-b03cb09b0654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146729536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.3146729536
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.2412136428
Short name T205
Test name
Test status
Simulation time 1523928170 ps
CPU time 23.44 seconds
Started Apr 18 03:43:02 PM PDT 24
Finished Apr 18 03:43:25 PM PDT 24
Peak memory 242416 kb
Host smart-20e56d01-7fcd-47aa-8238-c32bc161f2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412136428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.2412136428
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.1682882500
Short name T483
Test name
Test status
Simulation time 1610690898 ps
CPU time 6.69 seconds
Started Apr 18 03:42:59 PM PDT 24
Finished Apr 18 03:43:06 PM PDT 24
Peak memory 241624 kb
Host smart-0cf72857-2d28-48f1-8d9d-3810c8714c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682882500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.1682882500
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.974119738
Short name T1180
Test name
Test status
Simulation time 2883232066 ps
CPU time 21.23 seconds
Started Apr 18 03:42:58 PM PDT 24
Finished Apr 18 03:43:20 PM PDT 24
Peak memory 241708 kb
Host smart-2ce0053c-e08c-4c0b-8bf7-662a408883c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=974119738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.974119738
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.1274915732
Short name T111
Test name
Test status
Simulation time 118222391 ps
CPU time 3.6 seconds
Started Apr 18 03:43:02 PM PDT 24
Finished Apr 18 03:43:06 PM PDT 24
Peak memory 241936 kb
Host smart-ebd98e14-d7ff-4828-b533-17eba282e3b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1274915732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.1274915732
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.3294657025
Short name T747
Test name
Test status
Simulation time 724657610 ps
CPU time 6.34 seconds
Started Apr 18 03:42:58 PM PDT 24
Finished Apr 18 03:43:05 PM PDT 24
Peak memory 241912 kb
Host smart-66b435ba-cea3-41b6-8668-02ed2498b47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294657025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.3294657025
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.1354057043
Short name T662
Test name
Test status
Simulation time 69387269 ps
CPU time 1.91 seconds
Started Apr 18 03:43:15 PM PDT 24
Finished Apr 18 03:43:18 PM PDT 24
Peak memory 240340 kb
Host smart-16d5c502-bd45-41a4-ab7d-1e9f0b8acbaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354057043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.1354057043
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.1415126919
Short name T751
Test name
Test status
Simulation time 1938376480 ps
CPU time 11.77 seconds
Started Apr 18 03:43:09 PM PDT 24
Finished Apr 18 03:43:21 PM PDT 24
Peak memory 242568 kb
Host smart-d51fb1ec-70a6-4e9c-a60e-2785a3ecf3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415126919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.1415126919
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.3313235005
Short name T484
Test name
Test status
Simulation time 379262727 ps
CPU time 10.73 seconds
Started Apr 18 03:43:08 PM PDT 24
Finished Apr 18 03:43:19 PM PDT 24
Peak memory 241780 kb
Host smart-3b472d33-639e-4f4a-abe2-21b2a565394d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313235005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.3313235005
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.2141208296
Short name T1040
Test name
Test status
Simulation time 10538113552 ps
CPU time 34.39 seconds
Started Apr 18 03:43:09 PM PDT 24
Finished Apr 18 03:43:43 PM PDT 24
Peak memory 243324 kb
Host smart-b6787183-e3c3-4531-b08a-95cc6f199fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141208296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.2141208296
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.802045436
Short name T1106
Test name
Test status
Simulation time 119608275 ps
CPU time 4.06 seconds
Started Apr 18 03:43:03 PM PDT 24
Finished Apr 18 03:43:07 PM PDT 24
Peak memory 241924 kb
Host smart-c80045eb-43e7-4dd7-8334-8b2b6694efb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802045436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.802045436
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.3452122253
Short name T770
Test name
Test status
Simulation time 1339905335 ps
CPU time 28.78 seconds
Started Apr 18 03:43:07 PM PDT 24
Finished Apr 18 03:43:36 PM PDT 24
Peak memory 242744 kb
Host smart-7b630f13-acca-40db-805d-8e574eedc875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452122253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.3452122253
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.4088604150
Short name T591
Test name
Test status
Simulation time 772552603 ps
CPU time 16.64 seconds
Started Apr 18 03:43:09 PM PDT 24
Finished Apr 18 03:43:26 PM PDT 24
Peak memory 242212 kb
Host smart-de83a624-f8ac-48aa-8b16-8f33f6114a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088604150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.4088604150
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.2599912069
Short name T820
Test name
Test status
Simulation time 185606957 ps
CPU time 5.87 seconds
Started Apr 18 03:43:08 PM PDT 24
Finished Apr 18 03:43:14 PM PDT 24
Peak memory 241732 kb
Host smart-032db07d-4ada-49e9-a41c-9e82e85f3e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599912069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.2599912069
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.645274047
Short name T819
Test name
Test status
Simulation time 2485887511 ps
CPU time 22.12 seconds
Started Apr 18 03:43:03 PM PDT 24
Finished Apr 18 03:43:25 PM PDT 24
Peak memory 242104 kb
Host smart-ce158e2a-9322-4c6c-b1d5-e946fe331f8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645274047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.645274047
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.3500855953
Short name T1171
Test name
Test status
Simulation time 309314580 ps
CPU time 5.9 seconds
Started Apr 18 03:43:09 PM PDT 24
Finished Apr 18 03:43:16 PM PDT 24
Peak memory 241860 kb
Host smart-aad7be5b-4603-4afd-892f-10c009ffe513
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3500855953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3500855953
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.3693291070
Short name T590
Test name
Test status
Simulation time 247653348 ps
CPU time 3.25 seconds
Started Apr 18 03:43:04 PM PDT 24
Finished Apr 18 03:43:07 PM PDT 24
Peak memory 242112 kb
Host smart-b14ffe38-e97a-483b-9d5b-ce790e06e7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693291070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.3693291070
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.1482244208
Short name T656
Test name
Test status
Simulation time 31139229698 ps
CPU time 191.76 seconds
Started Apr 18 03:43:14 PM PDT 24
Finished Apr 18 03:46:26 PM PDT 24
Peak memory 281472 kb
Host smart-20cbfb48-8845-4cec-b0bd-6ce42db4d83a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482244208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.1482244208
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.1675197107
Short name T986
Test name
Test status
Simulation time 31845869223 ps
CPU time 433.07 seconds
Started Apr 18 03:43:08 PM PDT 24
Finished Apr 18 03:50:22 PM PDT 24
Peak memory 273480 kb
Host smart-e73b0b76-ce76-42bd-ac92-342b7d39fa9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675197107 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.1675197107
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.2829370744
Short name T970
Test name
Test status
Simulation time 2586434552 ps
CPU time 29.49 seconds
Started Apr 18 03:43:08 PM PDT 24
Finished Apr 18 03:43:38 PM PDT 24
Peak memory 241896 kb
Host smart-17d80a86-9ea9-4871-8e3d-2fd70000dfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829370744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.2829370744
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.3754777261
Short name T959
Test name
Test status
Simulation time 200273684 ps
CPU time 2.15 seconds
Started Apr 18 03:43:21 PM PDT 24
Finished Apr 18 03:43:24 PM PDT 24
Peak memory 240088 kb
Host smart-79416877-21f9-446d-a908-7df5674ffd86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754777261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3754777261
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.3297576620
Short name T409
Test name
Test status
Simulation time 1040508454 ps
CPU time 17.03 seconds
Started Apr 18 03:43:19 PM PDT 24
Finished Apr 18 03:43:37 PM PDT 24
Peak memory 241800 kb
Host smart-dd04ee82-de6f-4bb1-95cb-f57afadd8a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297576620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.3297576620
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.3734928164
Short name T909
Test name
Test status
Simulation time 1513516864 ps
CPU time 18.65 seconds
Started Apr 18 03:43:15 PM PDT 24
Finished Apr 18 03:43:34 PM PDT 24
Peak memory 242004 kb
Host smart-a13f69b9-a808-41a8-b072-66f7c44759da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734928164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.3734928164
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.591855789
Short name T684
Test name
Test status
Simulation time 93694288 ps
CPU time 3.07 seconds
Started Apr 18 03:43:16 PM PDT 24
Finished Apr 18 03:43:19 PM PDT 24
Peak memory 242068 kb
Host smart-c1fc972d-3b6b-4955-bdb7-1b9a85c4811c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591855789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.591855789
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.1199137839
Short name T432
Test name
Test status
Simulation time 1333795242 ps
CPU time 9.48 seconds
Started Apr 18 03:43:21 PM PDT 24
Finished Apr 18 03:43:31 PM PDT 24
Peak memory 243004 kb
Host smart-6bd9ea07-8457-468c-bc81-d8db5c45379e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199137839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.1199137839
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.148919702
Short name T979
Test name
Test status
Simulation time 829958767 ps
CPU time 10.03 seconds
Started Apr 18 03:43:20 PM PDT 24
Finished Apr 18 03:43:31 PM PDT 24
Peak memory 242132 kb
Host smart-d4c82849-c7c6-4d43-a4f4-942f9d3a193a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148919702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.148919702
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.2803500365
Short name T1071
Test name
Test status
Simulation time 238644931 ps
CPU time 5.82 seconds
Started Apr 18 03:43:16 PM PDT 24
Finished Apr 18 03:43:22 PM PDT 24
Peak memory 241672 kb
Host smart-edcb4b5d-b329-47e6-8c7a-bd4f4c972508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803500365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.2803500365
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.1993955964
Short name T107
Test name
Test status
Simulation time 1054265083 ps
CPU time 12.82 seconds
Started Apr 18 03:43:15 PM PDT 24
Finished Apr 18 03:43:29 PM PDT 24
Peak memory 241664 kb
Host smart-82f0cb35-f223-42fb-9fe3-a58fdcf64261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1993955964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.1993955964
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.3436505221
Short name T365
Test name
Test status
Simulation time 592536676 ps
CPU time 10.52 seconds
Started Apr 18 03:43:19 PM PDT 24
Finished Apr 18 03:43:30 PM PDT 24
Peak memory 242200 kb
Host smart-fb418ec3-9aca-4e65-ab20-0bfb382a9efa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436505221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.3436505221
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.217538816
Short name T879
Test name
Test status
Simulation time 355157403 ps
CPU time 7.68 seconds
Started Apr 18 03:43:15 PM PDT 24
Finished Apr 18 03:43:23 PM PDT 24
Peak memory 241840 kb
Host smart-0540145c-9105-4460-a322-ccdaabab87e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217538816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.217538816
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.3494079907
Short name T149
Test name
Test status
Simulation time 22492961658 ps
CPU time 129.17 seconds
Started Apr 18 03:43:20 PM PDT 24
Finished Apr 18 03:45:29 PM PDT 24
Peak memory 265332 kb
Host smart-f7ec6b02-f015-497e-995e-32f08c362138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494079907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.3494079907
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.277481433
Short name T813
Test name
Test status
Simulation time 714499618 ps
CPU time 13.1 seconds
Started Apr 18 03:43:22 PM PDT 24
Finished Apr 18 03:43:36 PM PDT 24
Peak memory 241760 kb
Host smart-bd9f72d5-2e1e-4b32-beba-e964bedb01fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277481433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.277481433
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.2809428641
Short name T390
Test name
Test status
Simulation time 762790041 ps
CPU time 1.87 seconds
Started Apr 18 03:43:29 PM PDT 24
Finished Apr 18 03:43:31 PM PDT 24
Peak memory 240152 kb
Host smart-f10917ff-5ea8-4e63-833d-7b3e43a5baa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809428641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.2809428641
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.2234222299
Short name T58
Test name
Test status
Simulation time 3404708221 ps
CPU time 25.1 seconds
Started Apr 18 03:43:26 PM PDT 24
Finished Apr 18 03:43:52 PM PDT 24
Peak memory 244632 kb
Host smart-d50025ad-7ea6-4c38-beeb-bbb6fc8001e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234222299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2234222299
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.2237418120
Short name T392
Test name
Test status
Simulation time 419921487 ps
CPU time 19.69 seconds
Started Apr 18 03:43:25 PM PDT 24
Finished Apr 18 03:43:45 PM PDT 24
Peak memory 241864 kb
Host smart-5d0fcfe9-822c-4389-bc0f-4159b55d4772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237418120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2237418120
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.1990911783
Short name T436
Test name
Test status
Simulation time 779815924 ps
CPU time 16.77 seconds
Started Apr 18 03:43:23 PM PDT 24
Finished Apr 18 03:43:41 PM PDT 24
Peak memory 242224 kb
Host smart-8aec3c7a-e0e3-4f27-94fa-f3dc37f51ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990911783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.1990911783
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.510077256
Short name T1104
Test name
Test status
Simulation time 118297809 ps
CPU time 3.28 seconds
Started Apr 18 03:43:19 PM PDT 24
Finished Apr 18 03:43:22 PM PDT 24
Peak memory 241716 kb
Host smart-6229a16f-b2b1-4fe1-b61c-eceba2eeeae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510077256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.510077256
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.3058592126
Short name T544
Test name
Test status
Simulation time 4084383625 ps
CPU time 66.98 seconds
Started Apr 18 03:43:23 PM PDT 24
Finished Apr 18 03:44:31 PM PDT 24
Peak memory 256928 kb
Host smart-1a561400-8604-4c66-b339-963e21de820e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058592126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.3058592126
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.3011676437
Short name T966
Test name
Test status
Simulation time 1938397713 ps
CPU time 52.86 seconds
Started Apr 18 03:43:25 PM PDT 24
Finished Apr 18 03:44:19 PM PDT 24
Peak memory 242028 kb
Host smart-b99da178-fd5d-4b2e-92cc-3103f7390fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011676437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.3011676437
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.4186745526
Short name T876
Test name
Test status
Simulation time 1161674135 ps
CPU time 17.09 seconds
Started Apr 18 03:43:19 PM PDT 24
Finished Apr 18 03:43:37 PM PDT 24
Peak memory 241668 kb
Host smart-68f6a053-a4b7-4141-869f-28684064b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186745526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.4186745526
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.355162003
Short name T1069
Test name
Test status
Simulation time 909346019 ps
CPU time 21.7 seconds
Started Apr 18 03:43:19 PM PDT 24
Finished Apr 18 03:43:41 PM PDT 24
Peak memory 241584 kb
Host smart-27ce7129-8a11-402b-9ef6-29f0ad63c16b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355162003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.355162003
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.1218332805
Short name T923
Test name
Test status
Simulation time 4072446855 ps
CPU time 12.87 seconds
Started Apr 18 03:43:25 PM PDT 24
Finished Apr 18 03:43:38 PM PDT 24
Peak memory 242800 kb
Host smart-09bef319-dce6-4bda-9703-bae24dbe9862
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1218332805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.1218332805
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.3678797041
Short name T1046
Test name
Test status
Simulation time 364233509 ps
CPU time 11.7 seconds
Started Apr 18 03:43:19 PM PDT 24
Finished Apr 18 03:43:32 PM PDT 24
Peak memory 242152 kb
Host smart-f9dd30f1-9715-4701-b78d-09ae474ab3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678797041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3678797041
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.348556701
Short name T382
Test name
Test status
Simulation time 4968748793 ps
CPU time 81.75 seconds
Started Apr 18 03:43:28 PM PDT 24
Finished Apr 18 03:44:50 PM PDT 24
Peak memory 247792 kb
Host smart-933b43f9-47fa-4f81-8bcc-91ba28920485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348556701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.
348556701
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.436017841
Short name T779
Test name
Test status
Simulation time 280769363105 ps
CPU time 761.71 seconds
Started Apr 18 03:43:25 PM PDT 24
Finished Apr 18 03:56:07 PM PDT 24
Peak memory 323328 kb
Host smart-2851dbb1-ef49-4aa5-90b9-70dfd0117048
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436017841 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.436017841
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.2762015911
Short name T369
Test name
Test status
Simulation time 11937368543 ps
CPU time 48.87 seconds
Started Apr 18 03:43:25 PM PDT 24
Finished Apr 18 03:44:15 PM PDT 24
Peak memory 241880 kb
Host smart-8dc97aff-eda8-4538-b537-4014d3862ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762015911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.2762015911
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.3047834760
Short name T93
Test name
Test status
Simulation time 162056244 ps
CPU time 1.64 seconds
Started Apr 18 03:43:30 PM PDT 24
Finished Apr 18 03:43:32 PM PDT 24
Peak memory 240276 kb
Host smart-25964dd6-4cf6-4810-a21c-ce441f0e9521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047834760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.3047834760
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.4289096871
Short name T59
Test name
Test status
Simulation time 629377435 ps
CPU time 21.31 seconds
Started Apr 18 03:43:32 PM PDT 24
Finished Apr 18 03:43:54 PM PDT 24
Peak memory 242120 kb
Host smart-37622665-68f1-411a-bd54-1cd215475c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289096871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.4289096871
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.3138040915
Short name T515
Test name
Test status
Simulation time 370093427 ps
CPU time 16.71 seconds
Started Apr 18 03:43:31 PM PDT 24
Finished Apr 18 03:43:48 PM PDT 24
Peak memory 241932 kb
Host smart-5fb61eeb-e781-40dd-b828-4b75f24bd50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138040915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.3138040915
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.3719464021
Short name T947
Test name
Test status
Simulation time 1688308096 ps
CPU time 31.14 seconds
Started Apr 18 03:43:30 PM PDT 24
Finished Apr 18 03:44:02 PM PDT 24
Peak memory 242284 kb
Host smart-bd30cd6d-4df7-4da0-8799-1c8c4e4658ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719464021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.3719464021
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.3451037296
Short name T69
Test name
Test status
Simulation time 265996277 ps
CPU time 3.93 seconds
Started Apr 18 03:43:30 PM PDT 24
Finished Apr 18 03:43:34 PM PDT 24
Peak memory 241884 kb
Host smart-c069d389-665a-45af-a448-6e23b2c4cc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451037296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.3451037296
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.3413947749
Short name T1055
Test name
Test status
Simulation time 409560396 ps
CPU time 5.54 seconds
Started Apr 18 03:43:30 PM PDT 24
Finished Apr 18 03:43:36 PM PDT 24
Peak memory 242364 kb
Host smart-82658228-ed01-49d0-a442-3682d8303a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413947749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.3413947749
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.2970371214
Short name T931
Test name
Test status
Simulation time 4553409622 ps
CPU time 29.42 seconds
Started Apr 18 03:43:30 PM PDT 24
Finished Apr 18 03:44:00 PM PDT 24
Peak memory 242416 kb
Host smart-6d098545-a2e0-4ef8-928b-2f113789bb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970371214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.2970371214
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.1823071576
Short name T150
Test name
Test status
Simulation time 11158159139 ps
CPU time 21.28 seconds
Started Apr 18 03:43:29 PM PDT 24
Finished Apr 18 03:43:51 PM PDT 24
Peak memory 241980 kb
Host smart-b0026c42-69ba-478a-98dc-b78c87852fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823071576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.1823071576
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.3097548564
Short name T1168
Test name
Test status
Simulation time 509723956 ps
CPU time 19.37 seconds
Started Apr 18 03:43:24 PM PDT 24
Finished Apr 18 03:43:44 PM PDT 24
Peak memory 241644 kb
Host smart-5f72ce5f-6a0b-450e-a87e-4af42c1f8c7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097548564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.3097548564
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.1192313101
Short name T364
Test name
Test status
Simulation time 4890392798 ps
CPU time 12.01 seconds
Started Apr 18 03:43:30 PM PDT 24
Finished Apr 18 03:43:42 PM PDT 24
Peak memory 242680 kb
Host smart-fcddd702-beed-4e5c-b5fc-169d15eff477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192313101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.1192313101
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.183387529
Short name T502
Test name
Test status
Simulation time 686272508 ps
CPU time 5.03 seconds
Started Apr 18 03:43:26 PM PDT 24
Finished Apr 18 03:43:31 PM PDT 24
Peak memory 242172 kb
Host smart-b34173c6-b122-4e08-92a4-f04aee7c46c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183387529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.183387529
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.4207813930
Short name T1145
Test name
Test status
Simulation time 72414901712 ps
CPU time 201.89 seconds
Started Apr 18 03:43:29 PM PDT 24
Finished Apr 18 03:46:52 PM PDT 24
Peak memory 257220 kb
Host smart-2c3c2410-33ff-427f-9a86-d9af1eb9543c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207813930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.4207813930
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.1422675149
Short name T658
Test name
Test status
Simulation time 355134255717 ps
CPU time 844.68 seconds
Started Apr 18 03:43:32 PM PDT 24
Finished Apr 18 03:57:37 PM PDT 24
Peak memory 271712 kb
Host smart-20cef993-09a6-42fa-806f-a838d4851245
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422675149 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.1422675149
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.2471893591
Short name T833
Test name
Test status
Simulation time 2548326838 ps
CPU time 25.43 seconds
Started Apr 18 03:43:29 PM PDT 24
Finished Apr 18 03:43:54 PM PDT 24
Peak memory 241776 kb
Host smart-03334bd9-2985-498b-b352-794b3821fba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471893591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.2471893591
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.4024412741
Short name T864
Test name
Test status
Simulation time 78355194 ps
CPU time 1.55 seconds
Started Apr 18 03:43:43 PM PDT 24
Finished Apr 18 03:43:46 PM PDT 24
Peak memory 240564 kb
Host smart-df68b293-3af0-4b65-b167-a2377abe8941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024412741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.4024412741
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.3631576634
Short name T431
Test name
Test status
Simulation time 557987422 ps
CPU time 11.47 seconds
Started Apr 18 03:43:35 PM PDT 24
Finished Apr 18 03:43:47 PM PDT 24
Peak memory 242232 kb
Host smart-93749188-0837-4d4e-9377-180d1ca85538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631576634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.3631576634
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.143208123
Short name T941
Test name
Test status
Simulation time 1048234773 ps
CPU time 31.19 seconds
Started Apr 18 03:43:36 PM PDT 24
Finished Apr 18 03:44:08 PM PDT 24
Peak memory 243180 kb
Host smart-430ada24-5d18-451f-a15f-b8e7d8736a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143208123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.143208123
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.3805807643
Short name T105
Test name
Test status
Simulation time 1594023454 ps
CPU time 28.34 seconds
Started Apr 18 03:43:36 PM PDT 24
Finished Apr 18 03:44:05 PM PDT 24
Peak memory 242232 kb
Host smart-778d8ea2-a9d5-489c-80f1-e27f8065f65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805807643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.3805807643
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.2327683740
Short name T648
Test name
Test status
Simulation time 2092068950 ps
CPU time 34.53 seconds
Started Apr 18 03:43:36 PM PDT 24
Finished Apr 18 03:44:11 PM PDT 24
Peak memory 248688 kb
Host smart-1e9067d4-944f-4704-aee1-c80a77e5da82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327683740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2327683740
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.2662654654
Short name T676
Test name
Test status
Simulation time 1035900078 ps
CPU time 12.51 seconds
Started Apr 18 03:43:34 PM PDT 24
Finished Apr 18 03:43:47 PM PDT 24
Peak memory 241760 kb
Host smart-1a355322-49f1-4917-b51f-b847f378b27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662654654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.2662654654
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.737321818
Short name T781
Test name
Test status
Simulation time 469631125 ps
CPU time 15.17 seconds
Started Apr 18 03:43:35 PM PDT 24
Finished Apr 18 03:43:51 PM PDT 24
Peak memory 241804 kb
Host smart-d0ce108f-9062-4ff7-886e-eb9c13ab04ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737321818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.737321818
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.1591284087
Short name T1082
Test name
Test status
Simulation time 790646940 ps
CPU time 26.33 seconds
Started Apr 18 03:43:36 PM PDT 24
Finished Apr 18 03:44:03 PM PDT 24
Peak memory 242012 kb
Host smart-78b09104-5a3b-484a-8841-920924d2def9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591284087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.1591284087
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.1750678873
Short name T445
Test name
Test status
Simulation time 2525265548 ps
CPU time 6.32 seconds
Started Apr 18 03:43:36 PM PDT 24
Finished Apr 18 03:43:43 PM PDT 24
Peak memory 242296 kb
Host smart-b0744e9b-c243-4f6e-ab65-0967f6c5c334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750678873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.1750678873
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.166985169
Short name T1187
Test name
Test status
Simulation time 828947834 ps
CPU time 6.6 seconds
Started Apr 18 03:43:29 PM PDT 24
Finished Apr 18 03:43:37 PM PDT 24
Peak memory 241844 kb
Host smart-d88c5fcf-2d70-46ae-861a-885d1f73bbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166985169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.166985169
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.1690072631
Short name T643
Test name
Test status
Simulation time 139192206678 ps
CPU time 1604.21 seconds
Started Apr 18 03:43:42 PM PDT 24
Finished Apr 18 04:10:27 PM PDT 24
Peak memory 285820 kb
Host smart-0306639c-a295-4cb4-8167-aa956100e1a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690072631 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.1690072631
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.1673050753
Short name T441
Test name
Test status
Simulation time 4929969827 ps
CPU time 28.84 seconds
Started Apr 18 03:43:36 PM PDT 24
Finished Apr 18 03:44:05 PM PDT 24
Peak memory 242224 kb
Host smart-84548886-94f0-4986-99f0-e2751f341533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673050753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1673050753
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.1355134682
Short name T894
Test name
Test status
Simulation time 221272102 ps
CPU time 2.04 seconds
Started Apr 18 03:43:47 PM PDT 24
Finished Apr 18 03:43:50 PM PDT 24
Peak memory 240436 kb
Host smart-04cfda38-1c4b-4a48-aaf8-b76a2d47f6af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355134682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.1355134682
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.3216413242
Short name T1122
Test name
Test status
Simulation time 230529744 ps
CPU time 6.69 seconds
Started Apr 18 03:43:47 PM PDT 24
Finished Apr 18 03:43:55 PM PDT 24
Peak memory 242356 kb
Host smart-7f2dea33-3be9-41f5-b583-422f401dd616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216413242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.3216413242
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.4279957071
Short name T1037
Test name
Test status
Simulation time 2230008706 ps
CPU time 16.83 seconds
Started Apr 18 03:43:42 PM PDT 24
Finished Apr 18 03:44:00 PM PDT 24
Peak memory 241904 kb
Host smart-aab3dbc2-b499-419e-b6f2-7e17f72b694e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279957071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.4279957071
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.624698086
Short name T1041
Test name
Test status
Simulation time 5354259371 ps
CPU time 30.3 seconds
Started Apr 18 03:43:43 PM PDT 24
Finished Apr 18 03:44:14 PM PDT 24
Peak memory 242632 kb
Host smart-3db671aa-29f3-43bf-84de-39ce208dad47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624698086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.624698086
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.2341821665
Short name T635
Test name
Test status
Simulation time 2267740833 ps
CPU time 4.81 seconds
Started Apr 18 03:43:41 PM PDT 24
Finished Apr 18 03:43:46 PM PDT 24
Peak memory 242248 kb
Host smart-1ba879b4-785b-4a7f-908c-34ba6fc34426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341821665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.2341821665
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.3986618390
Short name T1033
Test name
Test status
Simulation time 1010168639 ps
CPU time 8.55 seconds
Started Apr 18 03:43:41 PM PDT 24
Finished Apr 18 03:43:51 PM PDT 24
Peak memory 242012 kb
Host smart-6066b9bb-4ddb-4f67-bae6-b71e792c49af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986618390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.3986618390
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.450398615
Short name T1147
Test name
Test status
Simulation time 1494013246 ps
CPU time 25.13 seconds
Started Apr 18 03:43:44 PM PDT 24
Finished Apr 18 03:44:10 PM PDT 24
Peak memory 248696 kb
Host smart-5b0dbca1-9960-4089-8c94-6ca99c7f83e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450398615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.450398615
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.1617146262
Short name T806
Test name
Test status
Simulation time 875782567 ps
CPU time 7.2 seconds
Started Apr 18 03:43:41 PM PDT 24
Finished Apr 18 03:43:49 PM PDT 24
Peak memory 241908 kb
Host smart-b04c5011-fd0d-46a7-acf9-b7634b7dda1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617146262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.1617146262
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.4027786987
Short name T183
Test name
Test status
Simulation time 579413055 ps
CPU time 6.49 seconds
Started Apr 18 03:43:42 PM PDT 24
Finished Apr 18 03:43:49 PM PDT 24
Peak memory 241784 kb
Host smart-4e362b24-d246-4e30-af0b-9896e68ffedb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027786987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.4027786987
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.1103496716
Short name T887
Test name
Test status
Simulation time 998351161 ps
CPU time 9.58 seconds
Started Apr 18 03:43:43 PM PDT 24
Finished Apr 18 03:43:53 PM PDT 24
Peak memory 241992 kb
Host smart-8ad29aca-dc0e-41bb-9908-4d842a735cfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103496716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.1103496716
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.3569543277
Short name T1188
Test name
Test status
Simulation time 1160762126 ps
CPU time 10.23 seconds
Started Apr 18 03:43:40 PM PDT 24
Finished Apr 18 03:43:51 PM PDT 24
Peak memory 241856 kb
Host smart-d8943f1d-6c24-427b-a2b3-47b427de3395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569543277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.3569543277
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.2364463018
Short name T1167
Test name
Test status
Simulation time 22162980456 ps
CPU time 239.96 seconds
Started Apr 18 03:43:47 PM PDT 24
Finished Apr 18 03:47:48 PM PDT 24
Peak memory 273560 kb
Host smart-240eab34-8362-4914-81ab-18ee5cfda312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364463018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.2364463018
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.2171432072
Short name T1073
Test name
Test status
Simulation time 98954898396 ps
CPU time 1057.99 seconds
Started Apr 18 03:43:46 PM PDT 24
Finished Apr 18 04:01:25 PM PDT 24
Peak memory 250188 kb
Host smart-89515d76-4afe-47b7-9401-fcb470c3ea2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171432072 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.2171432072
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.4168821061
Short name T924
Test name
Test status
Simulation time 333443530 ps
CPU time 6.15 seconds
Started Apr 18 03:43:44 PM PDT 24
Finished Apr 18 03:43:51 PM PDT 24
Peak memory 241724 kb
Host smart-de70e274-acb4-472c-976f-39ad8fe7d55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168821061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.4168821061
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.3089075979
Short name T386
Test name
Test status
Simulation time 286927643 ps
CPU time 2.3 seconds
Started Apr 18 03:37:52 PM PDT 24
Finished Apr 18 03:37:54 PM PDT 24
Peak memory 240500 kb
Host smart-a170135b-f4b4-48ee-8c51-7cd2ddd2b626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089075979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.3089075979
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.1612858377
Short name T376
Test name
Test status
Simulation time 1323003193 ps
CPU time 27.04 seconds
Started Apr 18 03:37:36 PM PDT 24
Finished Apr 18 03:38:04 PM PDT 24
Peak memory 242216 kb
Host smart-935c8e66-5667-45f2-a78c-fac3ab9b44f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612858377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.1612858377
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.1444188091
Short name T512
Test name
Test status
Simulation time 571182309 ps
CPU time 11.04 seconds
Started Apr 18 03:37:42 PM PDT 24
Finished Apr 18 03:37:54 PM PDT 24
Peak memory 242276 kb
Host smart-5378cbc6-5101-4dc2-8d0c-a567b198a860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444188091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.1444188091
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.1510098464
Short name T965
Test name
Test status
Simulation time 2725272059 ps
CPU time 11.77 seconds
Started Apr 18 03:37:41 PM PDT 24
Finished Apr 18 03:37:54 PM PDT 24
Peak memory 241884 kb
Host smart-0a227549-a200-45d2-aac2-82124665b92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510098464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.1510098464
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.138128461
Short name T1126
Test name
Test status
Simulation time 1172387541 ps
CPU time 14.65 seconds
Started Apr 18 03:37:42 PM PDT 24
Finished Apr 18 03:37:57 PM PDT 24
Peak memory 242164 kb
Host smart-5bc9db65-bbf5-4323-9529-24a6a2c56548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138128461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.138128461
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.2348218414
Short name T34
Test name
Test status
Simulation time 352578911 ps
CPU time 4.39 seconds
Started Apr 18 03:37:37 PM PDT 24
Finished Apr 18 03:37:42 PM PDT 24
Peak memory 241780 kb
Host smart-2fa9fb5d-6e4c-4621-a4d3-67a5c3e525d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348218414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.2348218414
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.936612416
Short name T850
Test name
Test status
Simulation time 1772125973 ps
CPU time 40.85 seconds
Started Apr 18 03:37:48 PM PDT 24
Finished Apr 18 03:38:29 PM PDT 24
Peak memory 246360 kb
Host smart-03210219-a5bd-4319-ad35-2f830f5d31d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936612416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.936612416
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.3119932507
Short name T756
Test name
Test status
Simulation time 210615570 ps
CPU time 7.7 seconds
Started Apr 18 03:37:48 PM PDT 24
Finished Apr 18 03:37:56 PM PDT 24
Peak memory 241872 kb
Host smart-35d1fde6-31e3-409c-b59f-a4cbb2fe0756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119932507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.3119932507
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.2322492978
Short name T402
Test name
Test status
Simulation time 373261044 ps
CPU time 10.15 seconds
Started Apr 18 03:37:43 PM PDT 24
Finished Apr 18 03:37:53 PM PDT 24
Peak memory 242008 kb
Host smart-4db324e1-59ab-41f1-ae8c-a81210d8cb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322492978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.2322492978
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.2416536138
Short name T982
Test name
Test status
Simulation time 2285249578 ps
CPU time 30.93 seconds
Started Apr 18 03:37:42 PM PDT 24
Finished Apr 18 03:38:13 PM PDT 24
Peak memory 241720 kb
Host smart-44e0ef13-2e7d-4b44-ac77-eed9f46758d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2416536138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.2416536138
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.2427243764
Short name T1022
Test name
Test status
Simulation time 344787530 ps
CPU time 10.78 seconds
Started Apr 18 03:37:47 PM PDT 24
Finished Apr 18 03:37:58 PM PDT 24
Peak memory 242236 kb
Host smart-5cfff85d-4960-4956-a84f-79ed49d4e8da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2427243764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.2427243764
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.1867089513
Short name T400
Test name
Test status
Simulation time 516006235 ps
CPU time 8.43 seconds
Started Apr 18 03:37:36 PM PDT 24
Finished Apr 18 03:37:45 PM PDT 24
Peak memory 241980 kb
Host smart-8c2347c8-3f9f-4a6b-acf5-b661d4de97cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867089513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.1867089513
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.741666144
Short name T775
Test name
Test status
Simulation time 12730435518 ps
CPU time 81.34 seconds
Started Apr 18 03:37:52 PM PDT 24
Finished Apr 18 03:39:14 PM PDT 24
Peak memory 244560 kb
Host smart-dd88cb93-598c-4bfa-9f76-2ec0e1a754cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741666144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.741666144
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.2609899255
Short name T671
Test name
Test status
Simulation time 33941952899 ps
CPU time 644.27 seconds
Started Apr 18 03:37:46 PM PDT 24
Finished Apr 18 03:48:31 PM PDT 24
Peak memory 274440 kb
Host smart-9da3d476-f396-471e-a887-b9b3a176dc76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609899255 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.2609899255
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.3517112455
Short name T1085
Test name
Test status
Simulation time 690369407 ps
CPU time 24.1 seconds
Started Apr 18 03:37:46 PM PDT 24
Finished Apr 18 03:38:11 PM PDT 24
Peak memory 241768 kb
Host smart-466f1719-4719-4123-bd4b-6d388b7d41bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517112455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.3517112455
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.1360768601
Short name T858
Test name
Test status
Simulation time 286830857 ps
CPU time 3.84 seconds
Started Apr 18 03:43:46 PM PDT 24
Finished Apr 18 03:43:51 PM PDT 24
Peak memory 242168 kb
Host smart-5e1c1de9-b7ac-4b5f-bd70-d722901e4341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360768601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.1360768601
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.574282858
Short name T258
Test name
Test status
Simulation time 870401134 ps
CPU time 8.88 seconds
Started Apr 18 03:43:46 PM PDT 24
Finished Apr 18 03:43:56 PM PDT 24
Peak memory 241816 kb
Host smart-a5fab81b-994d-43a1-9552-dae37307ae1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574282858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.574282858
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.3085154080
Short name T20
Test name
Test status
Simulation time 28486660980 ps
CPU time 370.08 seconds
Started Apr 18 03:43:48 PM PDT 24
Finished Apr 18 03:49:58 PM PDT 24
Peak memory 248904 kb
Host smart-746d371c-99e7-43bd-bd6e-49030058f5f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085154080 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.3085154080
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.4369002
Short name T787
Test name
Test status
Simulation time 184351346 ps
CPU time 4.54 seconds
Started Apr 18 03:43:51 PM PDT 24
Finished Apr 18 03:43:56 PM PDT 24
Peak memory 242160 kb
Host smart-c747e3ef-52ec-489e-98dc-0545332415a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4369002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.4369002
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.2254499494
Short name T738
Test name
Test status
Simulation time 13184980303 ps
CPU time 34.61 seconds
Started Apr 18 03:43:53 PM PDT 24
Finished Apr 18 03:44:28 PM PDT 24
Peak memory 241916 kb
Host smart-8045ae82-e5cd-4ab1-b2f6-73367f47df54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254499494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.2254499494
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.2821765150
Short name T283
Test name
Test status
Simulation time 525671700515 ps
CPU time 1926.55 seconds
Started Apr 18 03:43:51 PM PDT 24
Finished Apr 18 04:15:58 PM PDT 24
Peak memory 445220 kb
Host smart-f6dff01d-b3f1-449f-98e4-4a16ec8f4317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821765150 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.2821765150
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.2183672020
Short name T170
Test name
Test status
Simulation time 1385371412 ps
CPU time 4.19 seconds
Started Apr 18 03:43:51 PM PDT 24
Finished Apr 18 03:43:56 PM PDT 24
Peak memory 241800 kb
Host smart-69d666cc-2520-4227-a03b-1b745e1019f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183672020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.2183672020
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.308752734
Short name T461
Test name
Test status
Simulation time 295992438 ps
CPU time 7.95 seconds
Started Apr 18 03:43:50 PM PDT 24
Finished Apr 18 03:43:59 PM PDT 24
Peak memory 241764 kb
Host smart-65da76a2-cee5-4fcf-a571-d5f2145d93f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308752734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.308752734
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.243776362
Short name T269
Test name
Test status
Simulation time 735295979780 ps
CPU time 1359.65 seconds
Started Apr 18 03:43:50 PM PDT 24
Finished Apr 18 04:06:31 PM PDT 24
Peak memory 313348 kb
Host smart-0e5a1936-7c7e-4277-aae2-1a72a7ebc3fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243776362 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.243776362
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.1158104931
Short name T427
Test name
Test status
Simulation time 450742903 ps
CPU time 5.25 seconds
Started Apr 18 03:43:50 PM PDT 24
Finished Apr 18 03:43:55 PM PDT 24
Peak memory 242080 kb
Host smart-4146e56f-a8f1-46c7-9362-c85201fc37c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158104931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.1158104931
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.464685791
Short name T626
Test name
Test status
Simulation time 3222040981 ps
CPU time 14.52 seconds
Started Apr 18 03:43:55 PM PDT 24
Finished Apr 18 03:44:10 PM PDT 24
Peak memory 241884 kb
Host smart-23648b2e-97d5-4c20-83d3-1ceda71fe2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464685791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.464685791
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.3839913792
Short name T1155
Test name
Test status
Simulation time 25375372255 ps
CPU time 117.69 seconds
Started Apr 18 03:43:57 PM PDT 24
Finished Apr 18 03:45:55 PM PDT 24
Peak memory 250512 kb
Host smart-37d1144b-adcf-49b7-9f6a-d26484e79137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839913792 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.3839913792
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.2435928385
Short name T926
Test name
Test status
Simulation time 406036886 ps
CPU time 4.38 seconds
Started Apr 18 03:43:56 PM PDT 24
Finished Apr 18 03:44:01 PM PDT 24
Peak memory 241776 kb
Host smart-5a20bcd9-e76d-4506-a3d3-28a13e452163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435928385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.2435928385
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.592487751
Short name T644
Test name
Test status
Simulation time 9551823863 ps
CPU time 22.39 seconds
Started Apr 18 03:43:55 PM PDT 24
Finished Apr 18 03:44:18 PM PDT 24
Peak memory 241980 kb
Host smart-df9d107b-24fb-4979-ba77-20df9853948f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592487751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.592487751
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.3176679174
Short name T14
Test name
Test status
Simulation time 190659638696 ps
CPU time 272 seconds
Started Apr 18 03:43:56 PM PDT 24
Finished Apr 18 03:48:29 PM PDT 24
Peak memory 276144 kb
Host smart-52133892-eab7-4ba9-bf89-6a53d513694c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176679174 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.3176679174
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.1574013810
Short name T650
Test name
Test status
Simulation time 462489618 ps
CPU time 4.96 seconds
Started Apr 18 03:43:58 PM PDT 24
Finished Apr 18 03:44:03 PM PDT 24
Peak memory 241852 kb
Host smart-320d2095-38a5-448e-9d2c-2fd804973b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574013810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.1574013810
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.1542249355
Short name T873
Test name
Test status
Simulation time 2355409122 ps
CPU time 18.78 seconds
Started Apr 18 03:43:57 PM PDT 24
Finished Apr 18 03:44:17 PM PDT 24
Peak memory 241768 kb
Host smart-1e8f73c3-a7ac-4ce5-a455-ec9eed60562e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542249355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.1542249355
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.1947887642
Short name T835
Test name
Test status
Simulation time 103331672 ps
CPU time 4.11 seconds
Started Apr 18 03:43:56 PM PDT 24
Finished Apr 18 03:44:00 PM PDT 24
Peak memory 241696 kb
Host smart-99c06a6a-4854-4f5a-abed-762d49f62e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947887642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.1947887642
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.654928742
Short name T1164
Test name
Test status
Simulation time 11431627057 ps
CPU time 41.68 seconds
Started Apr 18 03:43:57 PM PDT 24
Finished Apr 18 03:44:39 PM PDT 24
Peak memory 242304 kb
Host smart-1446d106-79dd-4085-88cb-6722407e0de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654928742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.654928742
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.2774576443
Short name T384
Test name
Test status
Simulation time 71196698680 ps
CPU time 893.69 seconds
Started Apr 18 03:43:59 PM PDT 24
Finished Apr 18 03:58:54 PM PDT 24
Peak memory 262728 kb
Host smart-9eb366b0-71ea-467c-8ad2-be534ce546cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774576443 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.2774576443
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.512597734
Short name T216
Test name
Test status
Simulation time 322438768 ps
CPU time 4.19 seconds
Started Apr 18 03:44:02 PM PDT 24
Finished Apr 18 03:44:06 PM PDT 24
Peak memory 241828 kb
Host smart-149c0426-3c3e-4f02-b43f-61d6c26ace72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512597734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.512597734
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.3328042104
Short name T508
Test name
Test status
Simulation time 4700287120 ps
CPU time 15.37 seconds
Started Apr 18 03:44:01 PM PDT 24
Finished Apr 18 03:44:16 PM PDT 24
Peak memory 241824 kb
Host smart-51954cc1-793b-404e-96c1-22cd831d5c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328042104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.3328042104
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.437129189
Short name T713
Test name
Test status
Simulation time 640378876329 ps
CPU time 1720.42 seconds
Started Apr 18 03:44:02 PM PDT 24
Finished Apr 18 04:12:43 PM PDT 24
Peak memory 399944 kb
Host smart-ca32f7d4-0fc0-475a-bf4e-ee3354b00f07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437129189 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.437129189
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.1347983557
Short name T875
Test name
Test status
Simulation time 419720372 ps
CPU time 4.95 seconds
Started Apr 18 03:43:59 PM PDT 24
Finished Apr 18 03:44:04 PM PDT 24
Peak memory 242016 kb
Host smart-80551c35-d4da-4635-a828-1d66d43b6692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347983557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.1347983557
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.46621605
Short name T935
Test name
Test status
Simulation time 184923769 ps
CPU time 5.07 seconds
Started Apr 18 03:44:00 PM PDT 24
Finished Apr 18 03:44:06 PM PDT 24
Peak memory 242084 kb
Host smart-799aa4b8-8b45-4041-99a8-8c7f94d33452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46621605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.46621605
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.2843625923
Short name T239
Test name
Test status
Simulation time 961674938076 ps
CPU time 2539.02 seconds
Started Apr 18 03:44:00 PM PDT 24
Finished Apr 18 04:26:20 PM PDT 24
Peak memory 334944 kb
Host smart-27882402-eb93-4161-b936-55fde3389675
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843625923 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.2843625923
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.683324185
Short name T975
Test name
Test status
Simulation time 653946066 ps
CPU time 3.94 seconds
Started Apr 18 03:43:58 PM PDT 24
Finished Apr 18 03:44:03 PM PDT 24
Peak memory 241992 kb
Host smart-0f5905fb-6751-4325-9f99-bda45d8ae63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683324185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.683324185
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.3375891655
Short name T447
Test name
Test status
Simulation time 241173266 ps
CPU time 4.43 seconds
Started Apr 18 03:44:01 PM PDT 24
Finished Apr 18 03:44:06 PM PDT 24
Peak memory 241572 kb
Host smart-2e72af7d-d8d8-4a43-acde-aebc82f880e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375891655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.3375891655
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.871856069
Short name T1158
Test name
Test status
Simulation time 156133407 ps
CPU time 2.48 seconds
Started Apr 18 03:38:03 PM PDT 24
Finished Apr 18 03:38:06 PM PDT 24
Peak memory 240100 kb
Host smart-df0070c9-3a27-4e66-94b7-c66e57fcd244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871856069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.871856069
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.1891487647
Short name T654
Test name
Test status
Simulation time 2365926302 ps
CPU time 30.11 seconds
Started Apr 18 03:37:53 PM PDT 24
Finished Apr 18 03:38:23 PM PDT 24
Peak memory 242340 kb
Host smart-3bd2442f-fa0b-459f-a0a2-b989a7762a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891487647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.1891487647
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.2884671036
Short name T64
Test name
Test status
Simulation time 1936714780 ps
CPU time 13.43 seconds
Started Apr 18 03:38:01 PM PDT 24
Finished Apr 18 03:38:15 PM PDT 24
Peak memory 241888 kb
Host smart-c7d42894-b8fd-4dff-b5c3-79e7e8be749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884671036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.2884671036
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.2104843150
Short name T333
Test name
Test status
Simulation time 387639326 ps
CPU time 10.87 seconds
Started Apr 18 03:38:00 PM PDT 24
Finished Apr 18 03:38:12 PM PDT 24
Peak memory 241712 kb
Host smart-3db73483-1970-4a1e-8ad4-4a3fadb24f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104843150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.2104843150
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.3775764304
Short name T530
Test name
Test status
Simulation time 6749526291 ps
CPU time 38.75 seconds
Started Apr 18 03:37:57 PM PDT 24
Finished Apr 18 03:38:36 PM PDT 24
Peak memory 242916 kb
Host smart-f2c2bd7e-121d-4c91-ae29-4a49f6169901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775764304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.3775764304
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.1644235321
Short name T645
Test name
Test status
Simulation time 96877640 ps
CPU time 3.21 seconds
Started Apr 18 03:37:54 PM PDT 24
Finished Apr 18 03:37:57 PM PDT 24
Peak memory 241924 kb
Host smart-a4227705-d2a5-4ace-bfbe-868b8afe79ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644235321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1644235321
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.1584300812
Short name T840
Test name
Test status
Simulation time 6846660108 ps
CPU time 63.68 seconds
Started Apr 18 03:37:56 PM PDT 24
Finished Apr 18 03:39:01 PM PDT 24
Peak memory 257836 kb
Host smart-c47bc1a1-1619-43af-924f-4563e217e686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584300812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.1584300812
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.434059996
Short name T891
Test name
Test status
Simulation time 1015005820 ps
CPU time 26.33 seconds
Started Apr 18 03:37:56 PM PDT 24
Finished Apr 18 03:38:23 PM PDT 24
Peak memory 242280 kb
Host smart-8208cbc6-a57d-4840-9566-841bbe629393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434059996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.434059996
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.180958344
Short name T967
Test name
Test status
Simulation time 212782547 ps
CPU time 8.55 seconds
Started Apr 18 03:38:01 PM PDT 24
Finished Apr 18 03:38:10 PM PDT 24
Peak memory 241660 kb
Host smart-488ccc35-4b2d-4730-9155-69e74de20c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180958344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.180958344
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.2759550931
Short name T576
Test name
Test status
Simulation time 1667806737 ps
CPU time 11.66 seconds
Started Apr 18 03:38:01 PM PDT 24
Finished Apr 18 03:38:13 PM PDT 24
Peak memory 242008 kb
Host smart-bf322f33-83d0-47f1-96a4-4c82d83eb88f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2759550931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.2759550931
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.1772613862
Short name T174
Test name
Test status
Simulation time 374129081 ps
CPU time 7.15 seconds
Started Apr 18 03:37:57 PM PDT 24
Finished Apr 18 03:38:05 PM PDT 24
Peak memory 241820 kb
Host smart-9b7c9edd-a726-4dc4-90bb-ecbb8d3ee1f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772613862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.1772613862
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.971680468
Short name T728
Test name
Test status
Simulation time 469391509 ps
CPU time 3.32 seconds
Started Apr 18 03:37:52 PM PDT 24
Finished Apr 18 03:37:56 PM PDT 24
Peak memory 242152 kb
Host smart-76f172aa-564e-4d43-b9f2-99abd51cef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971680468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.971680468
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.473736665
Short name T784
Test name
Test status
Simulation time 943087809 ps
CPU time 28.9 seconds
Started Apr 18 03:38:04 PM PDT 24
Finished Apr 18 03:38:33 PM PDT 24
Peak memory 241536 kb
Host smart-d2f2596b-b68d-4d3f-b731-f344e35d2b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473736665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.473736665
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.2930301639
Short name T664
Test name
Test status
Simulation time 139029073620 ps
CPU time 2898.16 seconds
Started Apr 18 03:38:02 PM PDT 24
Finished Apr 18 04:26:21 PM PDT 24
Peak memory 356556 kb
Host smart-cd0913f3-bc20-4136-b4d6-5bb7119dd3a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930301639 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.2930301639
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.1065673840
Short name T494
Test name
Test status
Simulation time 2544708722 ps
CPU time 24.71 seconds
Started Apr 18 03:38:04 PM PDT 24
Finished Apr 18 03:38:30 PM PDT 24
Peak memory 241968 kb
Host smart-d44650b2-8af7-4762-8690-aeab3cc4f1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065673840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.1065673840
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.966432749
Short name T486
Test name
Test status
Simulation time 2504681830 ps
CPU time 6.48 seconds
Started Apr 18 03:44:05 PM PDT 24
Finished Apr 18 03:44:12 PM PDT 24
Peak memory 242144 kb
Host smart-ae83d6d0-eeb2-4827-8c66-d4a0018e26af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966432749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.966432749
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.1925866676
Short name T457
Test name
Test status
Simulation time 341247919 ps
CPU time 8.77 seconds
Started Apr 18 03:44:08 PM PDT 24
Finished Apr 18 03:44:17 PM PDT 24
Peak memory 242196 kb
Host smart-a10e3f0b-2384-46f9-9bf9-751aeed253e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925866676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1925866676
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.2917187482
Short name T324
Test name
Test status
Simulation time 86498863286 ps
CPU time 838.3 seconds
Started Apr 18 03:44:06 PM PDT 24
Finished Apr 18 03:58:05 PM PDT 24
Peak memory 265028 kb
Host smart-2fc7b43a-349b-4f07-9777-8731b9db430f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917187482 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.2917187482
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.941219507
Short name T905
Test name
Test status
Simulation time 509854650 ps
CPU time 4.55 seconds
Started Apr 18 03:44:06 PM PDT 24
Finished Apr 18 03:44:11 PM PDT 24
Peak memory 242120 kb
Host smart-b2a081e0-f3c6-49cf-bc3f-67fa8b8e8947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941219507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.941219507
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.2726108817
Short name T746
Test name
Test status
Simulation time 2732358201 ps
CPU time 5.59 seconds
Started Apr 18 03:44:07 PM PDT 24
Finished Apr 18 03:44:13 PM PDT 24
Peak memory 242296 kb
Host smart-0bbbb717-ef9f-4498-b273-e17cc87fa0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726108817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.2726108817
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.1911892567
Short name T1100
Test name
Test status
Simulation time 209041322136 ps
CPU time 593.64 seconds
Started Apr 18 03:44:07 PM PDT 24
Finished Apr 18 03:54:01 PM PDT 24
Peak memory 265472 kb
Host smart-2129b2f6-f038-4c0c-929e-3add03a0c470
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911892567 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.1911892567
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.3734992047
Short name T82
Test name
Test status
Simulation time 91863953 ps
CPU time 3.59 seconds
Started Apr 18 03:44:09 PM PDT 24
Finished Apr 18 03:44:13 PM PDT 24
Peak memory 241736 kb
Host smart-f4c18dfb-c472-4d53-b125-8124b77f11b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734992047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.3734992047
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.3432026175
Short name T466
Test name
Test status
Simulation time 2209925750 ps
CPU time 22.89 seconds
Started Apr 18 03:44:07 PM PDT 24
Finished Apr 18 03:44:30 PM PDT 24
Peak memory 242084 kb
Host smart-7663418f-1860-41ff-8a96-d38950c20d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432026175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.3432026175
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.3539857622
Short name T37
Test name
Test status
Simulation time 53217720407 ps
CPU time 752.56 seconds
Started Apr 18 03:44:06 PM PDT 24
Finished Apr 18 03:56:39 PM PDT 24
Peak memory 348288 kb
Host smart-6bcf6485-5b03-452b-896e-f19ef31d5cce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539857622 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.3539857622
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.2185241725
Short name T599
Test name
Test status
Simulation time 103333914 ps
CPU time 4.22 seconds
Started Apr 18 03:44:06 PM PDT 24
Finished Apr 18 03:44:10 PM PDT 24
Peak memory 242076 kb
Host smart-531ae4d8-145c-498b-960b-962011a00c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185241725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.2185241725
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.653435227
Short name T498
Test name
Test status
Simulation time 2601677464 ps
CPU time 22.59 seconds
Started Apr 18 03:44:10 PM PDT 24
Finished Apr 18 03:44:33 PM PDT 24
Peak memory 242164 kb
Host smart-a3e85163-e80e-4488-92ab-f479287b33f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653435227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.653435227
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.113867961
Short name T210
Test name
Test status
Simulation time 189527571 ps
CPU time 4.43 seconds
Started Apr 18 03:44:11 PM PDT 24
Finished Apr 18 03:44:16 PM PDT 24
Peak memory 241804 kb
Host smart-a5f9f050-a8d3-43dc-8671-013d94c4eb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113867961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.113867961
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.43396290
Short name T403
Test name
Test status
Simulation time 1086009181 ps
CPU time 9.7 seconds
Started Apr 18 03:44:10 PM PDT 24
Finished Apr 18 03:44:20 PM PDT 24
Peak memory 241736 kb
Host smart-7eaf7333-0544-4cb2-a9d5-b2a6e859ef42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43396290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.43396290
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.701882602
Short name T227
Test name
Test status
Simulation time 149383791 ps
CPU time 4.19 seconds
Started Apr 18 03:44:10 PM PDT 24
Finished Apr 18 03:44:15 PM PDT 24
Peak memory 242140 kb
Host smart-07f15cbe-9e73-4ec2-ad66-90b6385dfe22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701882602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.701882602
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.763698132
Short name T135
Test name
Test status
Simulation time 228885415 ps
CPU time 7.49 seconds
Started Apr 18 03:44:11 PM PDT 24
Finished Apr 18 03:44:19 PM PDT 24
Peak memory 241700 kb
Host smart-a085ced3-53e3-4a3a-acee-33c015a79006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763698132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.763698132
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.2596975018
Short name T550
Test name
Test status
Simulation time 591188974 ps
CPU time 4.9 seconds
Started Apr 18 03:44:10 PM PDT 24
Finished Apr 18 03:44:16 PM PDT 24
Peak memory 241924 kb
Host smart-7245555a-f55e-431d-9d7d-684b6c46989e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596975018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.2596975018
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.2266576377
Short name T1006
Test name
Test status
Simulation time 478462696 ps
CPU time 10.02 seconds
Started Apr 18 03:44:11 PM PDT 24
Finished Apr 18 03:44:21 PM PDT 24
Peak memory 241772 kb
Host smart-479f04cd-6895-4f9e-a17b-845b59bdaacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266576377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.2266576377
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.1528800228
Short name T287
Test name
Test status
Simulation time 24725451700 ps
CPU time 200.26 seconds
Started Apr 18 03:44:10 PM PDT 24
Finished Apr 18 03:47:30 PM PDT 24
Peak memory 282168 kb
Host smart-36744f73-8e7d-4e15-8d05-bec1b56fa8f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528800228 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.1528800228
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.134026265
Short name T797
Test name
Test status
Simulation time 230674542 ps
CPU time 4.34 seconds
Started Apr 18 03:44:11 PM PDT 24
Finished Apr 18 03:44:15 PM PDT 24
Peak memory 242132 kb
Host smart-e2027f85-2159-4267-9904-8aa96005d40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134026265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.134026265
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.2257707210
Short name T1108
Test name
Test status
Simulation time 219767431 ps
CPU time 5.58 seconds
Started Apr 18 03:44:16 PM PDT 24
Finished Apr 18 03:44:22 PM PDT 24
Peak memory 241688 kb
Host smart-1a4352fa-b30e-4f40-b2b1-a3a6ab0e2685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257707210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2257707210
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.219285765
Short name T282
Test name
Test status
Simulation time 902841727122 ps
CPU time 2677.24 seconds
Started Apr 18 03:44:15 PM PDT 24
Finished Apr 18 04:28:53 PM PDT 24
Peak memory 394892 kb
Host smart-8f71e6fb-9679-4df3-8bb6-fd5e2d9fa96a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219285765 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.219285765
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.1996949093
Short name T1119
Test name
Test status
Simulation time 2275613947 ps
CPU time 7.39 seconds
Started Apr 18 03:44:17 PM PDT 24
Finished Apr 18 03:44:25 PM PDT 24
Peak memory 241992 kb
Host smart-aca2d4bd-63e4-4499-ba1e-94387b605bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996949093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.1996949093
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.1626132665
Short name T155
Test name
Test status
Simulation time 412893930 ps
CPU time 10.61 seconds
Started Apr 18 03:44:15 PM PDT 24
Finished Apr 18 03:44:26 PM PDT 24
Peak memory 241824 kb
Host smart-3ba4af1f-f50c-482a-8bf9-9eb8285389c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626132665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.1626132665
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.3315123318
Short name T631
Test name
Test status
Simulation time 259450050 ps
CPU time 4.16 seconds
Started Apr 18 03:44:25 PM PDT 24
Finished Apr 18 03:44:29 PM PDT 24
Peak memory 242124 kb
Host smart-31111892-9e0d-4662-a3a7-a2dd892184d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315123318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.3315123318
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.2266308774
Short name T570
Test name
Test status
Simulation time 1117613046 ps
CPU time 21.13 seconds
Started Apr 18 03:44:20 PM PDT 24
Finished Apr 18 03:44:42 PM PDT 24
Peak memory 241628 kb
Host smart-059a937f-7a4c-45fe-b18c-e410999f4fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266308774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.2266308774
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.4254075863
Short name T623
Test name
Test status
Simulation time 89512820069 ps
CPU time 1170.52 seconds
Started Apr 18 03:44:21 PM PDT 24
Finished Apr 18 04:03:52 PM PDT 24
Peak memory 357860 kb
Host smart-3fcdd600-6b62-4114-a63e-1015adfa95f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254075863 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.4254075863
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.1808031786
Short name T429
Test name
Test status
Simulation time 156930954 ps
CPU time 1.95 seconds
Started Apr 18 03:38:19 PM PDT 24
Finished Apr 18 03:38:21 PM PDT 24
Peak memory 240192 kb
Host smart-dcb77e88-58c2-4b1d-9a28-f4c0b2abf5ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808031786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.1808031786
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.441503888
Short name T68
Test name
Test status
Simulation time 5703658179 ps
CPU time 26.43 seconds
Started Apr 18 03:38:03 PM PDT 24
Finished Apr 18 03:38:30 PM PDT 24
Peak memory 242032 kb
Host smart-41dc0a4c-2feb-46f3-9242-e9a41db3e2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441503888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.441503888
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.2681000588
Short name T845
Test name
Test status
Simulation time 15174933090 ps
CPU time 48.02 seconds
Started Apr 18 03:38:12 PM PDT 24
Finished Apr 18 03:39:01 PM PDT 24
Peak memory 246748 kb
Host smart-625cbd23-2f7b-4955-9c78-bf83b019b1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681000588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.2681000588
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.2629736614
Short name T795
Test name
Test status
Simulation time 2458628390 ps
CPU time 34.92 seconds
Started Apr 18 03:38:09 PM PDT 24
Finished Apr 18 03:38:44 PM PDT 24
Peak memory 245640 kb
Host smart-de6532da-82ed-4dc3-bab2-db8d66444603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629736614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.2629736614
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.3940987226
Short name T760
Test name
Test status
Simulation time 367311536 ps
CPU time 9.63 seconds
Started Apr 18 03:38:08 PM PDT 24
Finished Apr 18 03:38:18 PM PDT 24
Peak memory 248644 kb
Host smart-34fe09e0-7fe5-4db5-9f88-e6be407febd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940987226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.3940987226
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.1974133519
Short name T536
Test name
Test status
Simulation time 434942241 ps
CPU time 4.27 seconds
Started Apr 18 03:38:03 PM PDT 24
Finished Apr 18 03:38:07 PM PDT 24
Peak memory 242132 kb
Host smart-3a28855e-457a-4ba6-b9b9-29d9a15608f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974133519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.1974133519
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.2003965090
Short name T521
Test name
Test status
Simulation time 1122886195 ps
CPU time 23.56 seconds
Started Apr 18 03:38:13 PM PDT 24
Finished Apr 18 03:38:37 PM PDT 24
Peak memory 246084 kb
Host smart-f85cb6fe-8981-4368-86ad-dd20eee27cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003965090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.2003965090
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.674024683
Short name T928
Test name
Test status
Simulation time 1021647920 ps
CPU time 12.92 seconds
Started Apr 18 03:38:09 PM PDT 24
Finished Apr 18 03:38:22 PM PDT 24
Peak memory 241924 kb
Host smart-fae34c84-01a6-41a9-8807-8c4ea970940b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674024683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.674024683
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.872740096
Short name T201
Test name
Test status
Simulation time 9959576518 ps
CPU time 28.83 seconds
Started Apr 18 03:38:09 PM PDT 24
Finished Apr 18 03:38:38 PM PDT 24
Peak memory 241808 kb
Host smart-7be2bcf0-ab2c-4ede-a1f4-70492d9f88e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872740096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.872740096
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.848163083
Short name T972
Test name
Test status
Simulation time 3603019915 ps
CPU time 8.88 seconds
Started Apr 18 03:38:07 PM PDT 24
Finished Apr 18 03:38:16 PM PDT 24
Peak memory 241748 kb
Host smart-b1e9f16c-8c26-46ca-93ea-2b2e631ffdb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=848163083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.848163083
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.2761240509
Short name T363
Test name
Test status
Simulation time 264569131 ps
CPU time 7.53 seconds
Started Apr 18 03:38:10 PM PDT 24
Finished Apr 18 03:38:18 PM PDT 24
Peak memory 241896 kb
Host smart-c59b501c-8ce2-45c8-985a-78067ae653d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2761240509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2761240509
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.2302988295
Short name T761
Test name
Test status
Simulation time 1539288763 ps
CPU time 11.56 seconds
Started Apr 18 03:38:05 PM PDT 24
Finished Apr 18 03:38:17 PM PDT 24
Peak memory 242036 kb
Host smart-bd81fb67-74b8-4c98-b383-78834b513713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302988295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.2302988295
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.4137960038
Short name T587
Test name
Test status
Simulation time 3700482005 ps
CPU time 128.31 seconds
Started Apr 18 03:38:18 PM PDT 24
Finished Apr 18 03:40:27 PM PDT 24
Peak memory 249484 kb
Host smart-ad14a70e-41e2-4ce8-be35-428d8b19d0b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137960038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
4137960038
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.3005309233
Short name T1141
Test name
Test status
Simulation time 1491188940 ps
CPU time 24.1 seconds
Started Apr 18 03:38:15 PM PDT 24
Finished Apr 18 03:38:39 PM PDT 24
Peak memory 241880 kb
Host smart-2560a8e3-8409-4e05-9f42-db6297bdffa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005309233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.3005309233
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.1758803985
Short name T1124
Test name
Test status
Simulation time 116650796 ps
CPU time 4.06 seconds
Started Apr 18 03:44:20 PM PDT 24
Finished Apr 18 03:44:24 PM PDT 24
Peak memory 241812 kb
Host smart-101595bc-06ee-4dce-ac2e-25895d87cfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758803985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.1758803985
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.2839168281
Short name T600
Test name
Test status
Simulation time 135563256 ps
CPU time 5.88 seconds
Started Apr 18 03:44:20 PM PDT 24
Finished Apr 18 03:44:26 PM PDT 24
Peak memory 241680 kb
Host smart-b0c6b229-5236-4ee9-8a62-9cc0bfd191de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839168281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.2839168281
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.3511893719
Short name T1136
Test name
Test status
Simulation time 49059605591 ps
CPU time 1158.09 seconds
Started Apr 18 03:44:20 PM PDT 24
Finished Apr 18 04:03:39 PM PDT 24
Peak memory 331876 kb
Host smart-c54a4c12-51f6-45e5-97fb-813d5411d203
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511893719 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.3511893719
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.418602562
Short name T531
Test name
Test status
Simulation time 209671904 ps
CPU time 3.66 seconds
Started Apr 18 03:44:20 PM PDT 24
Finished Apr 18 03:44:24 PM PDT 24
Peak memory 242012 kb
Host smart-70e1d0a9-750d-4b56-b7a4-09e8f1480cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418602562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.418602562
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.172404242
Short name T1004
Test name
Test status
Simulation time 2343628110 ps
CPU time 12.01 seconds
Started Apr 18 03:44:24 PM PDT 24
Finished Apr 18 03:44:36 PM PDT 24
Peak memory 241888 kb
Host smart-eddc9f4d-55b7-46a3-867b-a08078215f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172404242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.172404242
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.3235875328
Short name T1076
Test name
Test status
Simulation time 200302646 ps
CPU time 3.69 seconds
Started Apr 18 03:44:23 PM PDT 24
Finished Apr 18 03:44:27 PM PDT 24
Peak memory 241932 kb
Host smart-5df11c12-b0c7-4430-9b78-4f57c7d7cd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235875328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.3235875328
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.988087707
Short name T80
Test name
Test status
Simulation time 1997576931 ps
CPU time 7.22 seconds
Started Apr 18 03:44:21 PM PDT 24
Finished Apr 18 03:44:28 PM PDT 24
Peak memory 242244 kb
Host smart-d110838e-91a4-4584-b356-1d95cf4b31c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988087707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.988087707
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.1674098344
Short name T279
Test name
Test status
Simulation time 93237118217 ps
CPU time 2598.37 seconds
Started Apr 18 03:44:26 PM PDT 24
Finished Apr 18 04:27:46 PM PDT 24
Peak memory 331052 kb
Host smart-8295d8e1-83f6-4f71-937e-4fd6c941c017
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674098344 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.1674098344
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.2199632002
Short name T70
Test name
Test status
Simulation time 2225272505 ps
CPU time 6.01 seconds
Started Apr 18 03:44:30 PM PDT 24
Finished Apr 18 03:44:36 PM PDT 24
Peak memory 242016 kb
Host smart-d13a3fbf-3fcc-455a-96b9-a13bb42530ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199632002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.2199632002
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.1987658824
Short name T202
Test name
Test status
Simulation time 1939865433 ps
CPU time 4.62 seconds
Started Apr 18 03:44:26 PM PDT 24
Finished Apr 18 03:44:32 PM PDT 24
Peak memory 242052 kb
Host smart-6c9077f5-a813-403f-a323-04f8f53f8fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987658824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.1987658824
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.3633061674
Short name T1061
Test name
Test status
Simulation time 285949530 ps
CPU time 4.32 seconds
Started Apr 18 03:44:26 PM PDT 24
Finished Apr 18 03:44:31 PM PDT 24
Peak memory 241940 kb
Host smart-71ac85e8-b844-487a-9b29-f4885c24d3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633061674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.3633061674
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.1440091217
Short name T391
Test name
Test status
Simulation time 217329128 ps
CPU time 3.37 seconds
Started Apr 18 03:44:27 PM PDT 24
Finished Apr 18 03:44:30 PM PDT 24
Peak memory 241612 kb
Host smart-1f3fe4ec-a69b-4009-a307-a2194c058c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440091217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1440091217
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.2775147492
Short name T511
Test name
Test status
Simulation time 122014531411 ps
CPU time 943.55 seconds
Started Apr 18 03:44:30 PM PDT 24
Finished Apr 18 04:00:14 PM PDT 24
Peak memory 251276 kb
Host smart-263cf349-e200-45c3-975c-c1569bf60741
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775147492 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.2775147492
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.3909984078
Short name T180
Test name
Test status
Simulation time 472476408 ps
CPU time 4.11 seconds
Started Apr 18 03:44:25 PM PDT 24
Finished Apr 18 03:44:30 PM PDT 24
Peak memory 242136 kb
Host smart-3852f06c-422c-422c-a3a3-cf2324b44486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909984078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3909984078
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.2656090856
Short name T1169
Test name
Test status
Simulation time 321406905 ps
CPU time 12.12 seconds
Started Apr 18 03:44:28 PM PDT 24
Finished Apr 18 03:44:40 PM PDT 24
Peak memory 241688 kb
Host smart-6d54129d-c157-4e13-9753-f19343fcd499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656090856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.2656090856
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.3531707430
Short name T142
Test name
Test status
Simulation time 127981444576 ps
CPU time 1253.68 seconds
Started Apr 18 03:44:29 PM PDT 24
Finished Apr 18 04:05:23 PM PDT 24
Peak memory 391944 kb
Host smart-a6ac4134-9948-49e7-9857-5e2f940e0955
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531707430 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.3531707430
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.1532654504
Short name T237
Test name
Test status
Simulation time 446151776 ps
CPU time 4.99 seconds
Started Apr 18 03:44:30 PM PDT 24
Finished Apr 18 03:44:36 PM PDT 24
Peak memory 242212 kb
Host smart-ce2a1b7f-b191-4657-9ebf-9356356bdd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532654504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.1532654504
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.3744900657
Short name T624
Test name
Test status
Simulation time 702410685 ps
CPU time 9.8 seconds
Started Apr 18 03:44:27 PM PDT 24
Finished Apr 18 03:44:37 PM PDT 24
Peak memory 241616 kb
Host smart-46760be5-3d16-428c-aa78-3f20572e50c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744900657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.3744900657
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.1538776942
Short name T771
Test name
Test status
Simulation time 540762767 ps
CPU time 4.43 seconds
Started Apr 18 03:44:26 PM PDT 24
Finished Apr 18 03:44:31 PM PDT 24
Peak memory 241780 kb
Host smart-664b7455-010f-4b6f-b3e7-9eccd567cf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538776942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.1538776942
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.1482932976
Short name T535
Test name
Test status
Simulation time 523431380 ps
CPU time 3.77 seconds
Started Apr 18 03:44:30 PM PDT 24
Finished Apr 18 03:44:35 PM PDT 24
Peak memory 242100 kb
Host smart-079b48e1-74b0-4fee-b8d1-4904e4bac2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482932976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.1482932976
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.4227688019
Short name T881
Test name
Test status
Simulation time 191866880190 ps
CPU time 3547.86 seconds
Started Apr 18 03:44:30 PM PDT 24
Finished Apr 18 04:43:39 PM PDT 24
Peak memory 284372 kb
Host smart-c828c726-2ed8-4881-8f8d-8e33fe5f427e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227688019 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.4227688019
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.1494224526
Short name T248
Test name
Test status
Simulation time 264115757 ps
CPU time 4.18 seconds
Started Apr 18 03:44:30 PM PDT 24
Finished Apr 18 03:44:34 PM PDT 24
Peak memory 242160 kb
Host smart-a65b49e7-b49b-4407-b25d-7160eec88049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494224526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.1494224526
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.240815186
Short name T699
Test name
Test status
Simulation time 1124637447 ps
CPU time 9.97 seconds
Started Apr 18 03:44:31 PM PDT 24
Finished Apr 18 03:44:42 PM PDT 24
Peak memory 242064 kb
Host smart-2752b5e9-691e-4cf3-af32-af651029c0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240815186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.240815186
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.3093473336
Short name T990
Test name
Test status
Simulation time 31211650442 ps
CPU time 441.38 seconds
Started Apr 18 03:44:32 PM PDT 24
Finished Apr 18 03:51:54 PM PDT 24
Peak memory 268164 kb
Host smart-ba5e14b5-de48-4505-a4f4-7f3070f39937
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093473336 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.3093473336
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.327227623
Short name T526
Test name
Test status
Simulation time 177489430 ps
CPU time 8.99 seconds
Started Apr 18 03:44:31 PM PDT 24
Finished Apr 18 03:44:40 PM PDT 24
Peak memory 241820 kb
Host smart-c82e3f13-b453-4e3f-a6e8-76a1b55b6392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327227623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.327227623
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.1043871552
Short name T649
Test name
Test status
Simulation time 179474636 ps
CPU time 2.05 seconds
Started Apr 18 03:38:28 PM PDT 24
Finished Apr 18 03:38:31 PM PDT 24
Peak memory 240472 kb
Host smart-b1b96f4e-2b2e-4bb0-b333-b6bb7df20a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043871552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.1043871552
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.3529642803
Short name T808
Test name
Test status
Simulation time 1856846634 ps
CPU time 37.88 seconds
Started Apr 18 03:38:24 PM PDT 24
Finished Apr 18 03:39:02 PM PDT 24
Peak memory 242736 kb
Host smart-7bc88dd2-d8d3-4d6b-9322-2c4ab05fbc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529642803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.3529642803
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.2792243784
Short name T63
Test name
Test status
Simulation time 2635515043 ps
CPU time 30.66 seconds
Started Apr 18 03:38:31 PM PDT 24
Finished Apr 18 03:39:02 PM PDT 24
Peak memory 242248 kb
Host smart-98fe780e-2f3a-4d8b-b94d-20e99edfada3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792243784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.2792243784
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.400421909
Short name T580
Test name
Test status
Simulation time 1490725426 ps
CPU time 29.3 seconds
Started Apr 18 03:38:24 PM PDT 24
Finished Apr 18 03:38:54 PM PDT 24
Peak memory 241620 kb
Host smart-c267dbe8-1390-4988-b5a1-a1b7ab5119c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400421909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.400421909
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.3480579279
Short name T555
Test name
Test status
Simulation time 3696750326 ps
CPU time 29.34 seconds
Started Apr 18 03:38:23 PM PDT 24
Finished Apr 18 03:38:53 PM PDT 24
Peak memory 243144 kb
Host smart-04cc4279-34bd-4044-b29f-cb9c45a44dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480579279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.3480579279
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.298089346
Short name T893
Test name
Test status
Simulation time 136003663 ps
CPU time 4.39 seconds
Started Apr 18 03:38:18 PM PDT 24
Finished Apr 18 03:38:23 PM PDT 24
Peak memory 241912 kb
Host smart-e46b3c71-d3d5-4256-a9d0-ad9f0485487f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298089346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.298089346
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.4146512563
Short name T1161
Test name
Test status
Simulation time 3819116512 ps
CPU time 32.05 seconds
Started Apr 18 03:38:30 PM PDT 24
Finished Apr 18 03:39:02 PM PDT 24
Peak memory 244632 kb
Host smart-d6be0c87-aba6-4a67-8d36-a909f978b16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146512563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.4146512563
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.2775521357
Short name T1150
Test name
Test status
Simulation time 13093231003 ps
CPU time 36.38 seconds
Started Apr 18 03:38:31 PM PDT 24
Finished Apr 18 03:39:08 PM PDT 24
Peak memory 243208 kb
Host smart-75180959-6cf5-4047-b59f-8d07f8858991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775521357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.2775521357
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.50092873
Short name T147
Test name
Test status
Simulation time 384136714 ps
CPU time 6.51 seconds
Started Apr 18 03:38:23 PM PDT 24
Finished Apr 18 03:38:30 PM PDT 24
Peak memory 241704 kb
Host smart-1aa3612a-db26-4aa1-9999-667f589cc820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50092873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.50092873
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.3469512750
Short name T757
Test name
Test status
Simulation time 2186270957 ps
CPU time 8.2 seconds
Started Apr 18 03:38:23 PM PDT 24
Finished Apr 18 03:38:32 PM PDT 24
Peak memory 247664 kb
Host smart-5fa157af-7daa-4457-8436-fbdfe693aa6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3469512750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.3469512750
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.3128179783
Short name T715
Test name
Test status
Simulation time 1912890504 ps
CPU time 5.2 seconds
Started Apr 18 03:38:31 PM PDT 24
Finished Apr 18 03:38:36 PM PDT 24
Peak memory 241832 kb
Host smart-8d722548-ede1-4779-a03c-6b6aced7269b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128179783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.3128179783
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.1717781792
Short name T1067
Test name
Test status
Simulation time 536969028 ps
CPU time 8.92 seconds
Started Apr 18 03:38:19 PM PDT 24
Finished Apr 18 03:38:28 PM PDT 24
Peak memory 241728 kb
Host smart-3b41b31e-0ab3-4d69-90c7-04d8d6f8565c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717781792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.1717781792
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.3500024434
Short name T39
Test name
Test status
Simulation time 864758856 ps
CPU time 29.67 seconds
Started Apr 18 03:38:31 PM PDT 24
Finished Apr 18 03:39:01 PM PDT 24
Peak memory 243204 kb
Host smart-8a50a93c-fbb6-4ae3-98c5-96cb3392c3d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500024434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
3500024434
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.3434716107
Short name T696
Test name
Test status
Simulation time 373497207263 ps
CPU time 811.56 seconds
Started Apr 18 03:38:30 PM PDT 24
Finished Apr 18 03:52:02 PM PDT 24
Peak memory 273548 kb
Host smart-1c082051-15e0-47c3-8071-a15cee4348c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434716107 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.3434716107
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.837296100
Short name T499
Test name
Test status
Simulation time 2772684604 ps
CPU time 27.27 seconds
Started Apr 18 03:38:28 PM PDT 24
Finished Apr 18 03:38:56 PM PDT 24
Peak memory 241828 kb
Host smart-9568118b-5a38-4615-b5e9-6bf7a34d454a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837296100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.837296100
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.3657663464
Short name T460
Test name
Test status
Simulation time 2041597818 ps
CPU time 4.86 seconds
Started Apr 18 03:44:33 PM PDT 24
Finished Apr 18 03:44:38 PM PDT 24
Peak memory 241736 kb
Host smart-20f8a875-47bd-4c55-81c4-8c632fbab732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657663464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.3657663464
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.815241036
Short name T1038
Test name
Test status
Simulation time 2561021893 ps
CPU time 25.46 seconds
Started Apr 18 03:44:31 PM PDT 24
Finished Apr 18 03:44:57 PM PDT 24
Peak memory 241780 kb
Host smart-f3903caa-2111-4bd9-bc93-7c2948f633f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815241036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.815241036
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.3764269613
Short name T1162
Test name
Test status
Simulation time 348465733076 ps
CPU time 1010.79 seconds
Started Apr 18 03:44:37 PM PDT 24
Finished Apr 18 04:01:28 PM PDT 24
Peak memory 265288 kb
Host smart-75323338-6537-4efe-b215-be018a92a053
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764269613 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.3764269613
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.443628680
Short name T674
Test name
Test status
Simulation time 120373569 ps
CPU time 3.74 seconds
Started Apr 18 03:44:36 PM PDT 24
Finished Apr 18 03:44:40 PM PDT 24
Peak memory 241904 kb
Host smart-52444dc6-9cce-4c17-bb85-f8b10c3d8048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443628680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.443628680
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.2418674337
Short name T448
Test name
Test status
Simulation time 171594619 ps
CPU time 6.43 seconds
Started Apr 18 03:44:38 PM PDT 24
Finished Apr 18 03:44:45 PM PDT 24
Peak memory 241768 kb
Host smart-145aa317-9862-41bf-ac7a-ad5e614d77d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418674337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.2418674337
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1158055899
Short name T291
Test name
Test status
Simulation time 187484641842 ps
CPU time 1715.1 seconds
Started Apr 18 03:44:34 PM PDT 24
Finished Apr 18 04:13:10 PM PDT 24
Peak memory 442700 kb
Host smart-e36df8d1-8698-48fc-991c-eff27412bb55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158055899 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.1158055899
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.2759508679
Short name T874
Test name
Test status
Simulation time 1900091866 ps
CPU time 5.13 seconds
Started Apr 18 03:44:35 PM PDT 24
Finished Apr 18 03:44:41 PM PDT 24
Peak memory 242096 kb
Host smart-b6a53333-c328-484a-8655-8b78ebb04f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759508679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.2759508679
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.27399868
Short name T243
Test name
Test status
Simulation time 451931040 ps
CPU time 6.74 seconds
Started Apr 18 03:44:36 PM PDT 24
Finished Apr 18 03:44:44 PM PDT 24
Peak memory 242052 kb
Host smart-8506528a-6ceb-4032-9e24-dbb7ddcb6222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27399868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.27399868
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.3951427634
Short name T750
Test name
Test status
Simulation time 59487430067 ps
CPU time 274.96 seconds
Started Apr 18 03:44:38 PM PDT 24
Finished Apr 18 03:49:14 PM PDT 24
Peak memory 279556 kb
Host smart-0c93f666-346e-44eb-a6e3-f9f004db898f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951427634 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.3951427634
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.110456102
Short name T307
Test name
Test status
Simulation time 1831233017 ps
CPU time 5.16 seconds
Started Apr 18 03:44:35 PM PDT 24
Finished Apr 18 03:44:41 PM PDT 24
Peak memory 242132 kb
Host smart-2123e048-c17a-471d-bbfb-656d3daa76e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110456102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.110456102
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.3905339250
Short name T1042
Test name
Test status
Simulation time 5023043485 ps
CPU time 13.88 seconds
Started Apr 18 03:44:35 PM PDT 24
Finished Apr 18 03:44:49 PM PDT 24
Peak memory 242336 kb
Host smart-2e569edb-ca2c-4d1c-bfed-b7f16ebbe6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905339250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3905339250
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.3317933741
Short name T702
Test name
Test status
Simulation time 313084905 ps
CPU time 4.41 seconds
Started Apr 18 03:44:36 PM PDT 24
Finished Apr 18 03:44:41 PM PDT 24
Peak memory 241848 kb
Host smart-18d6a0f7-188f-4830-ad11-a2f10518b2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317933741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.3317933741
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.1285678040
Short name T9
Test name
Test status
Simulation time 4566022727 ps
CPU time 23.49 seconds
Started Apr 18 03:44:40 PM PDT 24
Finished Apr 18 03:45:04 PM PDT 24
Peak memory 242092 kb
Host smart-af18aba1-0984-4bb8-97e5-46d8d224858c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285678040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1285678040
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.2827662095
Short name T652
Test name
Test status
Simulation time 575051107 ps
CPU time 5.13 seconds
Started Apr 18 03:44:43 PM PDT 24
Finished Apr 18 03:44:49 PM PDT 24
Peak memory 241872 kb
Host smart-c6008fa7-de0e-40e6-b01d-1d6233c132e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827662095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.2827662095
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.1802290942
Short name T250
Test name
Test status
Simulation time 525274609 ps
CPU time 7.87 seconds
Started Apr 18 03:44:43 PM PDT 24
Finished Apr 18 03:44:51 PM PDT 24
Peak memory 242012 kb
Host smart-953b08ca-e7ed-4a21-826c-05b68954cfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802290942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.1802290942
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.1952264482
Short name T613
Test name
Test status
Simulation time 74362591988 ps
CPU time 721.73 seconds
Started Apr 18 03:44:41 PM PDT 24
Finished Apr 18 03:56:43 PM PDT 24
Peak memory 327696 kb
Host smart-ee41dc49-31fe-4ae9-8773-dfecf76b67c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952264482 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.1952264482
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.1516072112
Short name T192
Test name
Test status
Simulation time 510348695 ps
CPU time 4.49 seconds
Started Apr 18 03:44:40 PM PDT 24
Finished Apr 18 03:44:45 PM PDT 24
Peak memory 241908 kb
Host smart-1144e91a-36bf-4df2-b6aa-8cc8a19935c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516072112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.1516072112
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.912385404
Short name T480
Test name
Test status
Simulation time 551296943 ps
CPU time 7.85 seconds
Started Apr 18 03:44:42 PM PDT 24
Finished Apr 18 03:44:51 PM PDT 24
Peak memory 241916 kb
Host smart-91911c46-ddee-4b9d-821f-f967286fd366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912385404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.912385404
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.1115825990
Short name T904
Test name
Test status
Simulation time 108371815047 ps
CPU time 673.35 seconds
Started Apr 18 03:44:42 PM PDT 24
Finished Apr 18 03:55:55 PM PDT 24
Peak memory 256944 kb
Host smart-0adf5d1e-81ec-4710-84f7-4be36d6cdfaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115825990 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.1115825990
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.3915941081
Short name T514
Test name
Test status
Simulation time 536299937 ps
CPU time 4.95 seconds
Started Apr 18 03:44:42 PM PDT 24
Finished Apr 18 03:44:47 PM PDT 24
Peak memory 241864 kb
Host smart-df65ad7a-1c6f-4a36-8c1b-05a64417f995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915941081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.3915941081
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.1883601743
Short name T723
Test name
Test status
Simulation time 1897539625 ps
CPU time 4.25 seconds
Started Apr 18 03:44:49 PM PDT 24
Finished Apr 18 03:44:54 PM PDT 24
Peak memory 242032 kb
Host smart-6a128bd8-6d4e-4425-87c4-309c907e1e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883601743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.1883601743
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.233409446
Short name T944
Test name
Test status
Simulation time 32236750474 ps
CPU time 534.76 seconds
Started Apr 18 03:44:46 PM PDT 24
Finished Apr 18 03:53:41 PM PDT 24
Peak memory 257092 kb
Host smart-971b05a5-837f-40a5-b569-134912840a08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233409446 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.233409446
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.1142747535
Short name T581
Test name
Test status
Simulation time 2005769827 ps
CPU time 6.71 seconds
Started Apr 18 03:44:47 PM PDT 24
Finished Apr 18 03:44:54 PM PDT 24
Peak memory 241884 kb
Host smart-dc04a71d-453d-4004-b3d1-233af4e8336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142747535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.1142747535
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.423745772
Short name T1114
Test name
Test status
Simulation time 558458305 ps
CPU time 4.65 seconds
Started Apr 18 03:44:48 PM PDT 24
Finished Apr 18 03:44:53 PM PDT 24
Peak memory 242000 kb
Host smart-671c30eb-4f1e-4574-81af-577dcfa54c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423745772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.423745772
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.1962076132
Short name T159
Test name
Test status
Simulation time 165992109 ps
CPU time 3.32 seconds
Started Apr 18 03:44:47 PM PDT 24
Finished Apr 18 03:44:50 PM PDT 24
Peak memory 241732 kb
Host smart-3597dfce-0bf3-4e53-b53d-ad1baf79ba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962076132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.1962076132
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.2006710850
Short name T323
Test name
Test status
Simulation time 447508233688 ps
CPU time 736.15 seconds
Started Apr 18 03:44:47 PM PDT 24
Finished Apr 18 03:57:03 PM PDT 24
Peak memory 301092 kb
Host smart-e0d5c85b-a9e7-4728-a566-ca491c34148f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006710850 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.2006710850
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.3294021271
Short name T231
Test name
Test status
Simulation time 914001624 ps
CPU time 2.66 seconds
Started Apr 18 03:38:41 PM PDT 24
Finished Apr 18 03:38:44 PM PDT 24
Peak memory 240148 kb
Host smart-a4ce2208-dc23-439a-81cf-600c278f5ca5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294021271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.3294021271
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.1601981263
Short name T883
Test name
Test status
Simulation time 364871791 ps
CPU time 4.15 seconds
Started Apr 18 03:38:30 PM PDT 24
Finished Apr 18 03:38:34 PM PDT 24
Peak memory 241748 kb
Host smart-8fa4161e-f8a4-40c2-8882-cbbaec88372c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601981263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1601981263
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.2042010318
Short name T989
Test name
Test status
Simulation time 10416887478 ps
CPU time 22.86 seconds
Started Apr 18 03:38:36 PM PDT 24
Finished Apr 18 03:38:59 PM PDT 24
Peak memory 248784 kb
Host smart-cb2d97e2-ed1a-4d8e-a75b-5bbe0513db9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042010318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2042010318
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.2809278712
Short name T563
Test name
Test status
Simulation time 1413157090 ps
CPU time 37.82 seconds
Started Apr 18 03:38:36 PM PDT 24
Finished Apr 18 03:39:14 PM PDT 24
Peak memory 242220 kb
Host smart-9b5a8fa6-804e-4ea1-9c0d-9e49e87c465f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809278712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.2809278712
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.595917002
Short name T372
Test name
Test status
Simulation time 5980588612 ps
CPU time 41.03 seconds
Started Apr 18 03:38:36 PM PDT 24
Finished Apr 18 03:39:18 PM PDT 24
Peak memory 241912 kb
Host smart-7969d9d0-c1bb-4824-9513-212d5790ff29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595917002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.595917002
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.3190046910
Short name T949
Test name
Test status
Simulation time 1484585894 ps
CPU time 3.53 seconds
Started Apr 18 03:38:29 PM PDT 24
Finished Apr 18 03:38:33 PM PDT 24
Peak memory 241792 kb
Host smart-24d884c1-4f41-48ea-9ac9-f13c12790a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190046910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.3190046910
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.748256769
Short name T1079
Test name
Test status
Simulation time 5425828768 ps
CPU time 46.8 seconds
Started Apr 18 03:38:37 PM PDT 24
Finished Apr 18 03:39:24 PM PDT 24
Peak memory 248848 kb
Host smart-20274967-e38b-4778-aba9-4f51fce5700a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748256769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.748256769
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.742645781
Short name T609
Test name
Test status
Simulation time 2254995973 ps
CPU time 43.46 seconds
Started Apr 18 03:38:35 PM PDT 24
Finished Apr 18 03:39:19 PM PDT 24
Peak memory 242164 kb
Host smart-c0d581e1-f937-4ecb-aa93-b91d954ef6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742645781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.742645781
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.921356569
Short name T430
Test name
Test status
Simulation time 318654910 ps
CPU time 7.55 seconds
Started Apr 18 03:38:35 PM PDT 24
Finished Apr 18 03:38:43 PM PDT 24
Peak memory 241868 kb
Host smart-3a0f6313-2f2c-4666-b974-8555bd9a444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921356569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.921356569
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.3618909272
Short name T1070
Test name
Test status
Simulation time 1774138214 ps
CPU time 16.49 seconds
Started Apr 18 03:38:54 PM PDT 24
Finished Apr 18 03:39:12 PM PDT 24
Peak memory 241696 kb
Host smart-428c361f-1e76-4202-8316-54991667df2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618909272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3618909272
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.3236077805
Short name T709
Test name
Test status
Simulation time 353366048 ps
CPU time 9.64 seconds
Started Apr 18 03:38:29 PM PDT 24
Finished Apr 18 03:38:39 PM PDT 24
Peak memory 241824 kb
Host smart-1032d432-1d52-475b-a458-fdac80c7ad00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236077805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.3236077805
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.2636603731
Short name T1023
Test name
Test status
Simulation time 29950081913 ps
CPU time 131.5 seconds
Started Apr 18 03:38:40 PM PDT 24
Finished Apr 18 03:40:53 PM PDT 24
Peak memory 253980 kb
Host smart-1171cfcc-c295-4228-8bac-76df4dc523fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636603731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
2636603731
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.1902092624
Short name T285
Test name
Test status
Simulation time 94304715696 ps
CPU time 1981.53 seconds
Started Apr 18 03:38:42 PM PDT 24
Finished Apr 18 04:11:44 PM PDT 24
Peak memory 290924 kb
Host smart-91a5522d-cdf7-46cd-b177-6f45bbd5c2c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902092624 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.1902092624
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.91972024
Short name T420
Test name
Test status
Simulation time 6058814684 ps
CPU time 15.82 seconds
Started Apr 18 03:38:42 PM PDT 24
Finished Apr 18 03:38:58 PM PDT 24
Peak memory 241896 kb
Host smart-273548af-42aa-44ab-af0b-556fa5092792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91972024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.91972024
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.2518077733
Short name T606
Test name
Test status
Simulation time 234440774 ps
CPU time 4.66 seconds
Started Apr 18 03:44:47 PM PDT 24
Finished Apr 18 03:44:53 PM PDT 24
Peak memory 241984 kb
Host smart-12ed4baf-f5cc-4e82-8474-031374c42af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518077733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.2518077733
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.1335709583
Short name T151
Test name
Test status
Simulation time 238043662 ps
CPU time 15.16 seconds
Started Apr 18 03:44:47 PM PDT 24
Finished Apr 18 03:45:03 PM PDT 24
Peak memory 241836 kb
Host smart-f592a70e-965c-4205-8ea8-02c1d6c9f1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335709583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.1335709583
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.3817536673
Short name T322
Test name
Test status
Simulation time 322384537236 ps
CPU time 2530.91 seconds
Started Apr 18 03:44:46 PM PDT 24
Finished Apr 18 04:26:57 PM PDT 24
Peak memory 396392 kb
Host smart-ecfa2078-68ad-43c4-b6a3-5dcf6796d8b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817536673 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.3817536673
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.2795336752
Short name T455
Test name
Test status
Simulation time 97339823 ps
CPU time 3.45 seconds
Started Apr 18 03:44:45 PM PDT 24
Finished Apr 18 03:44:49 PM PDT 24
Peak memory 241824 kb
Host smart-db56ef30-7267-49f7-9acb-9b6abfba9bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795336752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.2795336752
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.1173316728
Short name T1173
Test name
Test status
Simulation time 958981652 ps
CPU time 6.66 seconds
Started Apr 18 03:44:46 PM PDT 24
Finished Apr 18 03:44:53 PM PDT 24
Peak memory 241860 kb
Host smart-f6b57c6f-9fa6-4570-806d-9de0d619807b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173316728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1173316728
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.514158966
Short name T100
Test name
Test status
Simulation time 101882071072 ps
CPU time 1516.49 seconds
Started Apr 18 03:44:52 PM PDT 24
Finished Apr 18 04:10:09 PM PDT 24
Peak memory 275472 kb
Host smart-fa99fe71-1dc3-4f15-a2e0-3ee3d0d292d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514158966 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.514158966
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.384070332
Short name T1160
Test name
Test status
Simulation time 244155152 ps
CPU time 4.73 seconds
Started Apr 18 03:44:51 PM PDT 24
Finished Apr 18 03:44:57 PM PDT 24
Peak memory 241912 kb
Host smart-16f42cda-b84b-4a47-b2c9-887291aad350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384070332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.384070332
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.4144583588
Short name T444
Test name
Test status
Simulation time 148478512 ps
CPU time 8.05 seconds
Started Apr 18 03:44:51 PM PDT 24
Finished Apr 18 03:44:59 PM PDT 24
Peak memory 241828 kb
Host smart-20298deb-2c8d-4785-9dc7-334061e58065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144583588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.4144583588
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.829586794
Short name T901
Test name
Test status
Simulation time 337499023889 ps
CPU time 610.19 seconds
Started Apr 18 03:44:51 PM PDT 24
Finished Apr 18 03:55:02 PM PDT 24
Peak memory 338824 kb
Host smart-0f1d522a-6ad9-4b16-ae0e-4119982b1203
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829586794 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.829586794
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.1305569774
Short name T28
Test name
Test status
Simulation time 153167658 ps
CPU time 4.2 seconds
Started Apr 18 03:44:50 PM PDT 24
Finished Apr 18 03:44:55 PM PDT 24
Peak memory 241924 kb
Host smart-5202bdbd-3d52-47a1-a544-8718f950e6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305569774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.1305569774
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.2945449685
Short name T999
Test name
Test status
Simulation time 616968466 ps
CPU time 16.69 seconds
Started Apr 18 03:44:53 PM PDT 24
Finished Apr 18 03:45:11 PM PDT 24
Peak memory 241668 kb
Host smart-042b3dc2-c48c-4ceb-ae8d-d330cab73cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945449685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2945449685
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1513192650
Short name T284
Test name
Test status
Simulation time 34597046577 ps
CPU time 674.61 seconds
Started Apr 18 03:44:50 PM PDT 24
Finished Apr 18 03:56:06 PM PDT 24
Peak memory 257108 kb
Host smart-8d65e296-8fbc-4ada-946e-4182b6cefc67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513192650 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.1513192650
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.1161271978
Short name T1144
Test name
Test status
Simulation time 217609252 ps
CPU time 3.62 seconds
Started Apr 18 03:44:53 PM PDT 24
Finished Apr 18 03:44:57 PM PDT 24
Peak memory 242076 kb
Host smart-83f84f37-72b3-46be-aeb0-2544fb50af15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161271978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.1161271978
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.1475946964
Short name T255
Test name
Test status
Simulation time 328564601 ps
CPU time 9.95 seconds
Started Apr 18 03:44:52 PM PDT 24
Finished Apr 18 03:45:02 PM PDT 24
Peak memory 241872 kb
Host smart-c22b3d1e-236b-4c72-b0b4-01ea8a1823a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475946964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.1475946964
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.550625277
Short name T326
Test name
Test status
Simulation time 135841662016 ps
CPU time 1468.95 seconds
Started Apr 18 03:44:51 PM PDT 24
Finished Apr 18 04:09:21 PM PDT 24
Peak memory 347244 kb
Host smart-07aceaee-6e69-4780-8495-5639f9379b18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550625277 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.550625277
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.3860303683
Short name T886
Test name
Test status
Simulation time 2025626812 ps
CPU time 5.3 seconds
Started Apr 18 03:44:52 PM PDT 24
Finished Apr 18 03:44:58 PM PDT 24
Peak memory 241796 kb
Host smart-4fcd1ba0-0eea-4925-9613-aafc3d4b47d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860303683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3860303683
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.1296642017
Short name T148
Test name
Test status
Simulation time 176625656289 ps
CPU time 2312.92 seconds
Started Apr 18 03:44:55 PM PDT 24
Finished Apr 18 04:23:29 PM PDT 24
Peak memory 286636 kb
Host smart-99fa12d5-8d56-4875-ba75-6f7007197e7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296642017 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.1296642017
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.3258097431
Short name T206
Test name
Test status
Simulation time 159659671 ps
CPU time 8.53 seconds
Started Apr 18 03:44:59 PM PDT 24
Finished Apr 18 03:45:08 PM PDT 24
Peak memory 241672 kb
Host smart-4b461a13-42fc-4ea1-b8cb-b2075e0f6061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258097431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.3258097431
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.3060573979
Short name T837
Test name
Test status
Simulation time 20428347917 ps
CPU time 598.15 seconds
Started Apr 18 03:44:55 PM PDT 24
Finished Apr 18 03:54:54 PM PDT 24
Peak memory 306288 kb
Host smart-fabefdde-d304-4b13-b2a4-5616947133aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060573979 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.3060573979
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.3520802721
Short name T496
Test name
Test status
Simulation time 534440807 ps
CPU time 4.43 seconds
Started Apr 18 03:44:58 PM PDT 24
Finished Apr 18 03:45:03 PM PDT 24
Peak memory 241920 kb
Host smart-7c6b5b43-5bde-4e0b-85ef-9dd5d9264672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520802721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.3520802721
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.3424698205
Short name T413
Test name
Test status
Simulation time 1526930741 ps
CPU time 13.59 seconds
Started Apr 18 03:44:56 PM PDT 24
Finished Apr 18 03:45:11 PM PDT 24
Peak memory 242012 kb
Host smart-dd28a649-a73e-42d3-ab72-11cfd1c2d7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424698205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.3424698205
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.733595517
Short name T988
Test name
Test status
Simulation time 101379671814 ps
CPU time 1741.82 seconds
Started Apr 18 03:44:59 PM PDT 24
Finished Apr 18 04:14:01 PM PDT 24
Peak memory 285356 kb
Host smart-12a2c1f7-5b10-4930-8c6c-213be22dbe3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733595517 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.733595517
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.3805668754
Short name T805
Test name
Test status
Simulation time 107223512 ps
CPU time 3.91 seconds
Started Apr 18 03:45:00 PM PDT 24
Finished Apr 18 03:45:05 PM PDT 24
Peak memory 241852 kb
Host smart-8275586b-ab2b-4658-9165-21c43b9cffd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805668754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.3805668754
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.2208965568
Short name T146
Test name
Test status
Simulation time 429598635 ps
CPU time 13.44 seconds
Started Apr 18 03:45:02 PM PDT 24
Finished Apr 18 03:45:16 PM PDT 24
Peak memory 241768 kb
Host smart-39720f41-192e-42fa-8a58-a45bb5c7341f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208965568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.2208965568
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1351517417
Short name T1086
Test name
Test status
Simulation time 520471897064 ps
CPU time 1533.24 seconds
Started Apr 18 03:45:00 PM PDT 24
Finished Apr 18 04:10:34 PM PDT 24
Peak memory 299940 kb
Host smart-440bd01e-f1c9-471e-8301-f11ececa5e78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351517417 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.1351517417
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.1076098871
Short name T471
Test name
Test status
Simulation time 115463067 ps
CPU time 4.31 seconds
Started Apr 18 03:45:02 PM PDT 24
Finished Apr 18 03:45:07 PM PDT 24
Peak memory 242152 kb
Host smart-018a7d42-34e6-4e94-84f4-09a58596b044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076098871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.1076098871
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.3333881627
Short name T799
Test name
Test status
Simulation time 264988021 ps
CPU time 6.32 seconds
Started Apr 18 03:45:04 PM PDT 24
Finished Apr 18 03:45:11 PM PDT 24
Peak memory 241772 kb
Host smart-2168f235-0e69-49b4-838b-785e1f9cbb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333881627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3333881627
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.2781355631
Short name T1103
Test name
Test status
Simulation time 58287523978 ps
CPU time 690.95 seconds
Started Apr 18 03:45:04 PM PDT 24
Finished Apr 18 03:56:36 PM PDT 24
Peak memory 309772 kb
Host smart-f96927e2-bd0a-42e6-bb7c-3d8a008c88b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781355631 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.2781355631
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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