Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25488983

1

T1

4025

T2

2299

T3

322776

full_word

8337288

1

T1

721

T2

1560

T3

92329

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33825981	1			T1	4746		T2	3859		T3	415105
auto[TlIntgErrCmd]	96	1			T258	6		T259	8		T260	4
auto[TlIntgErrData]	93	1			T259	7		T260	4		T266	4
auto[TlIntgErrBoth]	101	1			T258	4		T259	5		T260	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9951801

1

T1

4519

T2

3462

T3

59357

auto[1]

23874470

1

T1

227

T2

397

T3

355748

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6335008	1			T1	3900		T2	2061		T3	35264
auto[TlIntgErrNone]	partial	auto[1]	19153714	1			T1	125		T2	238		T3	287512
auto[TlIntgErrNone]	full_word	auto[0]	3616663	1			T1	619		T2	1401		T3	24093
auto[TlIntgErrNone]	full_word	auto[1]	4720596	1			T1	102		T2	159		T3	68236
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T258	2		T259	2		T260	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T258	3		T259	6		T260	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T260	1		T327	1		T265	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T258	1		T323	1		T329	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T259	3		T260	1		T266	2
auto[TlIntgErrData]	partial	auto[1]	40	1			T259	3		T260	2		T266	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T259	1		T260	1		T266	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T324	1		T329	1		T330	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T258	1		T259	1		T260	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T258	2		T259	3		T260	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T258	1		T259	1		T330	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T325	1		T331	1		T328	1