Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.73	96.75	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.73	96.75	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.73	96.75	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T3,T7
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T17,T18,T19

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T79,T174,T173
1	Covered	T79,T174,T173

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T7

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T6
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T7
ReadWaitSt	252	Covered	T2,T3,T7
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T6
IdleSt->ReadSt	236	Covered	T2,T3,T7
InitSt->ErrorSt	315	Covered	T204,T205
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T114,T206,T207
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T4,T8
ReadSt->ReadWaitSt	252	Covered	T2,T3,T7
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T2,T3,T7
ResetSt->ErrorSt	315	Covered	T78,T79,T80
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T3,T4,T8
CheckFailError	317	Covered	T79,T174,T173
FsmStateError	289	Covered	T2,T3,T6
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T8,T9,T109
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T3,T4,T8
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T79,T174,T173
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T2,T3,T6
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T3,T4,T8
NoError->CheckFailError	317	Covered	T79,T174,T173
NoError->FsmStateError	289	Covered	T2,T3,T6
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T7
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T24,T36,T102
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T4,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T18,T19
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T6,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T6,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T79,T174,T173
1	0	Covered	T79,T174,T173
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T7,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	497874033	496969817	0	0
DigestKnown_A	497874033	496969817	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	497874033	22450	0	0
ErrorKnown_A	497874033	496969817	0	0
FsmStateKnown_A	497874033	496969817	0	0
InitDoneKnown_A	497874033	496969817	0	0
InitReadLocksPartition_A	497874033	75761859	0	0
InitWriteLocksPartition_A	497874033	75761859	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	497874033	496969817	0	0
OtpCmdKnown_A	497874033	496969817	0	0
OtpErrorState_A	497874033	0	0	0
OtpReqKnown_A	497874033	496969817	0	0
OtpSizeKnown_A	497874033	496969817	0	0
OtpWdataKnown_A	497874033	496969817	0	0
ReadLockPropagation_A	497874033	183101884	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	497874033	496969817	0	0
TlulRdataKnown_A	497874033	496969817	0	0
TlulReadOnReadLock_A	497874033	7700	0	0
TlulRerrorKnown_A	497874033	496969817	0	0
TlulRvalidKnown_A	497874033	496969817	0	0
WriteLockPropagation_A	497874033	2521344	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	497874033	30392832	0	0
u_state_regs_A	497874033	496969817	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	22450	0	0
T11	23420	0	0	0
T12	524978	0	0	0
T66	15230	0	0	0
T79	16033	3600	0	0
T100	33967	0	0	0
T122	13382	0	0	0
T144	146647	0	0	0
T170	110479	0	0	0
T173	0	2250	0	0
T174	0	2623	0	0
T175	9934	0	0	0
T176	14521	0	0	0
T180	0	2296	0	0
T181	0	4034	0	0
T182	0	3990	0	0
T185	0	3657	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	75761859	0	0
T1	32504	4517	0	0
T2	19924	4310	0	0
T3	487273	78519	0	0
T4	478159	23555	0	0
T5	70792	53571	0	0
T6	17238	8648	0	0
T7	11097	4880	0	0
T8	23067	8855	0	0
T9	301741	125630	0	0
T10	450663	142434	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	75761859	0	0
T1	32504	4517	0	0
T2	19924	4310	0	0
T3	487273	78519	0	0
T4	478159	23555	0	0
T5	70792	53571	0	0
T6	17238	8648	0	0
T7	11097	4880	0	0
T8	23067	8855	0	0
T9	301741	125630	0	0
T10	450663	142434	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	183101884	0	0
T1	32504	4138	0	0
T2	19924	0	0	0
T3	487273	444528	0	0
T4	478159	620671	0	0
T5	70792	0	0	0
T6	17238	8637	0	0
T7	11097	0	0	0
T8	23067	9666	0	0
T9	301741	143677	0	0
T10	450663	58180	0	0
T24	0	2146	0	0
T109	0	11894	0	0
T118	0	21106	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	7700	0	0
T2	19924	2	0	0
T3	487273	18	0	0
T4	478159	10	0	0
T5	70792	17	0	0
T6	17238	15	0	0
T7	11097	0	0	0
T8	23067	15	0	0
T9	301741	17	0	0
T10	450663	23	0	0
T17	0	7	0	0
T108	5222	0	0	0
T118	0	7	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	2521344	0	0
T5	70792	0	0	0
T8	23067	10337	0	0
T9	301741	0	0	0
T10	450663	7810	0	0
T17	103436	0	0	0
T24	0	2286	0	0
T36	0	563	0	0
T78	12422	0	0	0
T101	0	25460	0	0
T102	0	8545	0	0
T104	0	4440	0	0
T105	0	4635	0	0
T106	0	50797	0	0
T107	0	7099	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	30392832	0	0
T1	32504	13673	0	0
T2	19924	10708	0	0
T3	487273	0	0	0
T4	478159	0	0	0
T5	70792	0	0	0
T6	17238	0	0	0
T7	11097	0	0	0
T8	23067	15992	0	0
T9	301741	0	0	0
T10	450663	90218	0	0
T24	0	50498	0	0
T109	0	4459	0	0
T110	0	2937	0	0
T114	0	2479	0	0
T121	0	38619	0	0
T175	0	2354	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T175,T176

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T121,T111,T171

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T17,T18,T19

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T79,T174,T173
1	Covered	T79,T174,T173

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T3,T7

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T6
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T3,T7
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T6
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T114,T206,T207
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T178,T179,T194
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T3,T4
ReadSt->ReadWaitSt	252	Covered	T1,T3,T7
ReadWaitSt->ErrorSt	276	Covered	T121,T111,T144
ReadWaitSt->IdleSt	270	Covered	T1,T3,T7
ResetSt->ErrorSt	315	Covered	T78,T79,T80
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T3,T4
CheckFailError	317	Covered	T79,T174,T173
FsmStateError	289	Covered	T2,T3,T6
MacroEccCorrError	221	Covered	T7,T121,T111
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T9,T10
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T3,T4
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T79,T174,T173
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T6
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T7,T121,T111
MacroEccCorrError->NoError	235	Covered	T111,T69,T45
NoError->AccessError	256	Covered	T2,T3,T4
NoError->CheckFailError	317	Covered	T79,T174,T173
NoError->FsmStateError	289	Covered	T2,T3,T6
NoError->MacroEccCorrError	221	Covered	T7,T121,T111

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T7,T175,T176
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T178,T179,T194
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T7
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T24,T36,T102
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T121,T111,T171
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T121,T111,T144
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T18,T19
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T79,T174,T173
1	0	Covered	T79,T174,T173
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	497874033	496969817	0	0
DigestKnown_A	497874033	496969817	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	497874033	21858	0	0
ErrorKnown_A	497874033	496969817	0	0
FsmStateKnown_A	497874033	496969817	0	0
InitDoneKnown_A	497874033	496969817	0	0
InitReadLocksPartition_A	497874033	75953425	0	0
InitWriteLocksPartition_A	497874033	75953425	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	497874033	496969817	0	0
OtpCmdKnown_A	497874033	496969817	0	0
OtpErrorState_A	497874033	69	0	0
OtpReqKnown_A	497874033	496969817	0	0
OtpSizeKnown_A	497874033	496969817	0	0
OtpWdataKnown_A	497874033	496969817	0	0
ReadLockPropagation_A	497874033	191140501	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	497874033	496969817	0	0
TlulRdataKnown_A	497874033	496969817	0	0
TlulReadOnReadLock_A	497874033	8054	0	0
TlulRerrorKnown_A	497874033	496969817	0	0
TlulRvalidKnown_A	497874033	496969817	0	0
WriteLockPropagation_A	497874033	2779548	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	497874033	31026214	0	0
u_state_regs_A	497874033	496969817	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	21858	0	0
T11	23420	0	0	0
T12	524978	0	0	0
T66	15230	0	0	0
T79	16033	3600	0	0
T100	33967	0	0	0
T122	13382	0	0	0
T144	146647	0	0	0
T170	110479	0	0	0
T173	0	2250	0	0
T174	0	2623	0	0
T175	9934	0	0	0
T176	14521	0	0	0
T180	0	2296	0	0
T182	0	3990	0	0
T185	0	3657	0	0
T186	0	3442	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	75953425	0	0
T1	32504	4653	0	0
T2	19924	4412	0	0
T3	487273	78621	0	0
T4	478159	23674	0	0
T5	70792	53622	0	0
T6	17238	8699	0	0
T7	11097	4914	0	0
T8	23067	8923	0	0
T9	301741	125649	0	0
T10	450663	143029	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	75953425	0	0
T1	32504	4653	0	0
T2	19924	4412	0	0
T3	487273	78621	0	0
T4	478159	23674	0	0
T5	70792	53622	0	0
T6	17238	8699	0	0
T7	11097	4914	0	0
T8	23067	8923	0	0
T9	301741	125649	0	0
T10	450663	143029	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	69	0	0
T24	60799	0	0	0
T73	12233	0	0	0
T74	9366	0	0	0
T109	22198	0	0	0
T110	38937	0	0	0
T111	150905	1	0	0
T112	78603	0	0	0
T113	4881	0	0	0
T114	10019	0	0	0
T121	139758	1	0	0
T144	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T194	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	191140501	0	0
T1	32504	3743	0	0
T2	19924	1130	0	0
T3	487273	436856	0	0
T4	478159	656454	0	0
T5	70792	63310	0	0
T6	17238	8635	0	0
T7	11097	0	0	0
T8	23067	9700	0	0
T9	301741	104865	0	0
T10	450663	82085	0	0
T118	0	20518	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	8054	0	0
T2	19924	4	0	0
T3	487273	25	0	0
T4	478159	28	0	0
T5	70792	17	0	0
T6	17238	5	0	0
T7	11097	0	0	0
T8	23067	6	0	0
T9	301741	19	0	0
T10	450663	29	0	0
T17	0	62	0	0
T108	5222	0	0	0
T118	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	2779548	0	0
T2	19924	5093	0	0
T3	487273	0	0	0
T4	478159	0	0	0
T5	70792	0	0	0
T6	17238	0	0	0
T7	11097	0	0	0
T8	23067	0	0	0
T9	301741	0	0	0
T10	450663	31910	0	0
T70	0	11414	0	0
T101	0	12469	0	0
T102	0	1946	0	0
T104	0	3122	0	0
T106	0	58280	0	0
T107	0	11810	0	0
T108	5222	0	0	0
T115	0	12809	0	0
T197	0	3348	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	31026214	0	0
T1	32504	6685	0	0
T2	19924	14757	0	0
T3	487273	0	0	0
T4	478159	0	0	0
T5	70792	0	0	0
T6	17238	0	0	0
T7	11097	0	0	0
T8	23067	2932	0	0
T9	301741	0	0	0
T10	450663	84491	0	0
T24	0	50277	0	0
T36	0	106772	0	0
T109	0	4425	0	0
T110	0	2920	0	0
T118	0	3082	0	0
T178	0	2850	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T177,T75,T43

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T111,T144,T45

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T17,T18,T19

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T80,T174,T173
1	Covered	T80,T174,T173

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T6

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T6
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T6
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T114,T206,T207
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T73,T74,T175
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T3
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T171,T199,T208
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T78,T79,T80
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T3
CheckFailError	317	Covered	T80,T174,T173
FsmStateError	289	Covered	T2,T3,T6
MacroEccCorrError	221	Covered	T111,T144,T177
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T8,T5,T9
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T2,T3
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T80,T174,T173
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T6
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T111,T144,T177
MacroEccCorrError->NoError	235	Covered	T45,T77,T52
NoError->AccessError	256	Covered	T1,T2,T3
NoError->CheckFailError	317	Covered	T80,T174,T173
NoError->FsmStateError	289	Covered	T2,T3,T6
NoError->MacroEccCorrError	221	Covered	T111,T144,T177

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T177,T75,T43
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T73,T74,T175
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T24,T36,T147
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T111,T144,T45
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T171,T199,T208
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T18,T19
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T6,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T80,T174,T173
1	0	Covered	T80,T174,T173
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	497874033	496969817	0	0
DigestKnown_A	497874033	496969817	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	497874033	19996	0	0
ErrorKnown_A	497874033	496969817	0	0
FsmStateKnown_A	497874033	496969817	0	0
InitDoneKnown_A	497874033	496969817	0	0
InitReadLocksPartition_A	497874033	76143861	0	0
InitWriteLocksPartition_A	497874033	76143861	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	497874033	496969817	0	0
OtpCmdKnown_A	497874033	496969817	0	0
OtpErrorState_A	497874033	52	0	0
OtpReqKnown_A	497874033	496969817	0	0
OtpSizeKnown_A	497874033	496969817	0	0
OtpWdataKnown_A	497874033	496969817	0	0
ReadLockPropagation_A	497874033	187665965	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	497874033	496969817	0	0
TlulRdataKnown_A	497874033	496969817	0	0
TlulReadOnReadLock_A	497874033	8248	0	0
TlulRerrorKnown_A	497874033	496969817	0	0
TlulRvalidKnown_A	497874033	496969817	0	0
WriteLockPropagation_A	497874033	1611621	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	497874033	19174687	0	0
u_state_regs_A	497874033	496969817	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	19996	0	0
T20	15985	0	0	0
T34	788606	0	0	0
T67	12372	0	0	0
T80	9670	3097	0	0
T157	25079	0	0	0
T173	0	2250	0	0
T174	0	2623	0	0
T180	0	2296	0	0
T182	0	3990	0	0
T183	0	2083	0	0
T185	0	3657	0	0
T187	8869	0	0	0
T188	851256	0	0	0
T189	20595	0	0	0
T190	11051	0	0	0
T191	25437	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	76143861	0	0
T1	32504	4789	0	0
T2	19924	4514	0	0
T3	487273	78723	0	0
T4	478159	23793	0	0
T5	70792	53673	0	0
T6	17238	8750	0	0
T7	11097	4948	0	0
T8	23067	8991	0	0
T9	301741	125668	0	0
T10	450663	143624	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	76143861	0	0
T1	32504	4789	0	0
T2	19924	4514	0	0
T3	487273	78723	0	0
T4	478159	23793	0	0
T5	70792	53673	0	0
T6	17238	8750	0	0
T7	11097	4948	0	0
T8	23067	8991	0	0
T9	301741	125668	0	0
T10	450663	143624	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	52	0	0
T12	524978	0	0	0
T73	12233	1	0	0
T74	9366	1	0	0
T79	16033	0	0	0
T111	150905	0	0	0
T112	78603	0	0	0
T113	4881	0	0	0
T114	10019	0	0	0
T171	0	1	0	0
T175	9934	1	0	0
T176	14521	1	0	0
T190	0	1	0	0
T193	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0
T199	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	187665965	0	0
T1	32504	4132	0	0
T2	19924	1128	0	0
T3	487273	436827	0	0
T4	478159	656448	0	0
T5	70792	63304	0	0
T6	17238	0	0	0
T7	11097	0	0	0
T8	23067	10804	0	0
T9	301741	105542	0	0
T10	450663	17698	0	0
T24	0	1640	0	0
T118	0	21100	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	8248	0	0
T1	32504	2	0	0
T2	19924	1	0	0
T3	487273	16	0	0
T4	478159	24	0	0
T5	70792	9	0	0
T6	17238	8	0	0
T7	11097	0	0	0
T8	23067	8	0	0
T9	301741	17	0	0
T10	450663	31	0	0
T118	0	7	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	1611621	0	0
T24	60799	3488	0	0
T36	0	2771	0	0
T70	0	29124	0	0
T73	12233	0	0	0
T74	9366	0	0	0
T79	16033	0	0	0
T102	0	6599	0	0
T106	0	54316	0	0
T107	0	3554	0	0
T109	22198	0	0	0
T110	38937	0	0	0
T111	150905	0	0	0
T112	78603	0	0	0
T113	4881	0	0	0
T114	10019	0	0	0
T116	0	1552	0	0
T117	0	19458	0	0
T157	0	11821	0	0
T203	0	1438	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	19174687	0	0
T1	32504	19574	0	0
T2	19924	14672	0	0
T3	487273	0	0	0
T4	478159	0	0	0
T5	70792	0	0	0
T6	17238	0	0	0
T7	11097	0	0	0
T8	23067	0	0	0
T9	301741	0	0	0
T10	450663	106846	0	0
T24	0	50056	0	0
T73	0	4085	0	0
T74	0	2501	0	0
T109	0	4391	0	0
T110	0	2903	0	0
T118	0	3048	0	0
T175	0	2332	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497874033	496969817	0	0
T1	32504	31918	0	0
T2	19924	19418	0	0
T3	487273	487261	0	0
T4	478159	478138	0	0
T5	70792	70543	0	0
T6	17238	16978	0	0
T7	11097	10816	0	0
T8	23067	22797	0	0
T9	301741	301730	0	0
T10	450663	447703	0	0