Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25574629

1

T1

1826

T2

608

T3

3463

full_word

8317282

1

T1

287

T2

237

T3

2495

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33891611	1			T1	2113		T2	845		T3	5958
auto[TlIntgErrCmd]	85	1			T275	2		T276	4		T277	4
auto[TlIntgErrData]	119	1			T275	5		T276	11		T277	2
auto[TlIntgErrBoth]	96	1			T275	3		T276	5		T277	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9663026

1

T1

2011

T2

538

T3

5471

auto[1]

24228885

1

T1

102

T2

307

T3

487

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6123394	1			T1	1769		T2	425		T3	3191
auto[TlIntgErrNone]	partial	auto[1]	19450966	1			T1	57		T2	183		T3	272
auto[TlIntgErrNone]	full_word	auto[0]	3539483	1			T1	242		T2	113		T3	2280
auto[TlIntgErrNone]	full_word	auto[1]	4777768	1			T1	45		T2	124		T3	215
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T275	1		T276	3		T277	1
auto[TlIntgErrCmd]	partial	auto[1]	35	1			T275	1		T276	1		T277	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T286	1		T392	1		T282	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T284	1		T285	1		-	-
auto[TlIntgErrData]	partial	auto[0]	52	1			T275	1		T276	5		T277	1
auto[TlIntgErrData]	partial	auto[1]	50	1			T275	4		T276	4		T277	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T276	1		T286	2		T393	1
auto[TlIntgErrData]	full_word	auto[1]	13	1			T276	1		T387	3		T284	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T276	2		T277	2		T286	2
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T275	2		T276	3		T277	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T387	1		T394	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T275	1		T391	1		T394	1