Group : dv_base_reg_pkg::mubi_cov#(4,32'b00000000000000000000000000000101,32'b00000000000000000000000000001010)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(4,32'b00000000000000000000000000000101,32'b00000000000000000000000000001010)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

5 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi4_cov_of_tb.dut.u_lc_check_byp_en_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_tb.dut.u_lc_dft_en_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if 100.00 1 100 1 64 64




Group Instance : mubi4_cov_of_tb.dut.u_lc_check_byp_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_check_byp_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_check_byp_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_dft_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_dft_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_dft_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 624 1 T9 2 T30 2 T113 1
others[1] 577 1 T1 1 T5 2 T9 1
others[2] 584 1 T2 1 T3 1 T5 3
others[3] 1026 1 T1 2 T5 2 T6 1
false 5824 1 T1 4 T2 2 T3 1
true 8076 1 T1 4 T2 1 T3 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 283 1 T5 1 T10 1 T30 1
others[1] 265 1 T30 1 T113 1 T13 3
others[2] 272 1 T30 1 T113 1 T104 1
others[3] 437 1 T5 2 T9 1 T7 2
false 2219 1 T5 2 T9 4 T6 2
true 16517 1 T1 8 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 1490 1 T5 3 T9 3 T12 3
others[1] 1616 1 T1 2 T5 4 T9 6
others[2] 1568 1 T5 4 T121 2 T113 2
others[3] 2803 1 T1 3 T5 7 T11 2
false 13242 1 T1 6 T2 4 T3 4
true 5052 1 T7 12 T15 1 T8 11


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 30 1 T144 1 T81 1 T109 1
others[1] 21 1 T70 1 T411 1 T165 1
others[2] 18 1 T372 1 T16 1 T83 1
others[3] 28 1 T121 1 T373 1 T71 1
false 14724 1 T1 8 T2 4 T3 5
true 207 1 T3 1 T10 1 T138 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 929 1 T30 3 T114 3 T201 1
others[1] 993 1 T5 6 T41 3 T168 3
others[2] 1017 1 T5 3 T10 2 T30 3
others[3] 1626 1 T4 3 T5 6 T11 3
false 7603 1 T1 3 T2 3 T3 2
true 7758 1 T1 6 T2 2 T3 3

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