Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.52	96.10	96.15	96.71		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	458228655	8226761	0	0
check_regwen_rd_A	458228655	3401	0	0
check_timeout_rd_A	458228655	3194	0	0
check_trigger_regwen_rd_A	458228655	3626	0	0
consistency_check_period_rd_A	458228655	3760	0	0
creator_sw_cfg_read_lock_rd_A	458228655	3118	0	0
direct_access_address_rd_A	458228655	1964	0	0
direct_access_wdata_0_rd_A	458228655	1316	0	0
direct_access_wdata_1_rd_A	458228655	1382	0	0
integrity_check_period_rd_A	458228655	3534	0	0
intr_enable_rd_A	458228655	4162	0	0
owner_sw_cfg_read_lock_rd_A	458228655	2741	0	0
rot_creator_auth_codesign_read_lock_rd_A	458228655	3183	0	0
rot_creator_auth_state_read_lock_rd_A	458228655	2853	0	0
vendor_test_read_lock_rd_A	458228655	2727	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	8226761	0	0
T7	230994	49505	0	0
T8	220734	34268	0	0
T13	0	140893	0	0
T15	5605	0	0	0
T16	0	17269	0	0
T20	0	64208	0	0
T51	16247	0	0	0
T118	18706	0	0	0
T123	15419	0	0	0
T138	23272	0	0	0
T140	0	31962	0	0
T151	0	203440	0	0
T152	0	137437	0	0
T155	0	392016	0	0
T168	45684	0	0	0
T182	9113	0	0	0
T184	0	44946	0	0
T201	9479	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	3401	0	0
T8	220734	19	0	0
T13	636756	0	0	0
T32	153944	0	0	0
T47	11927	0	0	0
T81	13971	0	0	0
T104	17663	0	0	0
T119	19844	0	0	0
T140	0	30	0	0
T144	15252	0	0	0
T145	92514	0	0	0
T146	23508	0	0	0
T270	0	58	0	0
T299	0	100	0	0
T300	0	111	0	0
T360	0	56	0	0
T366	0	128	0	0
T367	0	70	0	0
T368	0	58	0	0
T369	0	43	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	3194	0	0
T8	220734	54	0	0
T13	636756	0	0	0
T32	153944	0	0	0
T47	11927	0	0	0
T81	13971	0	0	0
T104	17663	0	0	0
T119	19844	0	0	0
T140	0	38	0	0
T144	15252	0	0	0
T145	92514	0	0	0
T146	23508	0	0	0
T270	0	60	0	0
T299	0	95	0	0
T300	0	126	0	0
T360	0	62	0	0
T366	0	143	0	0
T367	0	82	0	0
T368	0	73	0	0
T369	0	42	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	3626	0	0
T8	220734	32	0	0
T13	636756	0	0	0
T32	153944	0	0	0
T47	11927	0	0	0
T81	13971	0	0	0
T104	17663	0	0	0
T119	19844	0	0	0
T140	0	22	0	0
T144	15252	0	0	0
T145	92514	0	0	0
T146	23508	0	0	0
T270	0	43	0	0
T299	0	88	0	0
T300	0	131	0	0
T360	0	69	0	0
T366	0	89	0	0
T367	0	59	0	0
T368	0	45	0	0
T369	0	22	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	3760	0	0
T8	220734	34	0	0
T13	636756	0	0	0
T32	153944	0	0	0
T47	11927	0	0	0
T81	13971	0	0	0
T104	17663	0	0	0
T119	19844	0	0	0
T140	0	59	0	0
T144	15252	0	0	0
T145	92514	0	0	0
T146	23508	0	0	0
T270	0	62	0	0
T299	0	118	0	0
T300	0	60	0	0
T360	0	70	0	0
T366	0	153	0	0
T367	0	78	0	0
T368	0	39	0	0
T369	0	38	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	3118	0	0
T8	220734	28	0	0
T13	636756	0	0	0
T32	153944	0	0	0
T47	11927	0	0	0
T81	13971	0	0	0
T104	17663	0	0	0
T119	19844	0	0	0
T140	0	32	0	0
T144	15252	0	0	0
T145	92514	0	0	0
T146	23508	0	0	0
T270	0	39	0	0
T299	0	72	0	0
T300	0	92	0	0
T360	0	44	0	0
T366	0	127	0	0
T367	0	65	0	0
T368	0	68	0	0
T369	0	36	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	1964	0	0
T8	220734	59	0	0
T13	636756	0	0	0
T32	153944	0	0	0
T47	11927	0	0	0
T81	13971	0	0	0
T104	17663	0	0	0
T119	19844	0	0	0
T140	0	36	0	0
T144	15252	0	0	0
T145	92514	0	0	0
T146	23508	0	0	0
T270	0	55	0	0
T299	0	122	0	0
T300	0	101	0	0
T360	0	65	0	0
T366	0	187	0	0
T367	0	92	0	0
T368	0	65	0	0
T369	0	35	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	1316	0	0
T8	220734	3	0	0
T13	636756	0	0	0
T32	153944	0	0	0
T47	11927	0	0	0
T81	13971	0	0	0
T104	17663	0	0	0
T119	19844	0	0	0
T140	0	13	0	0
T144	15252	0	0	0
T145	92514	0	0	0
T146	23508	0	0	0
T270	0	9	0	0
T299	0	71	0	0
T300	0	80	0	0
T360	0	45	0	0
T366	0	123	0	0
T367	0	49	0	0
T368	0	41	0	0
T369	0	4	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	1382	0	0
T8	220734	7	0	0
T13	636756	0	0	0
T32	153944	0	0	0
T47	11927	0	0	0
T81	13971	0	0	0
T104	17663	0	0	0
T119	19844	0	0	0
T140	0	5	0	0
T144	15252	0	0	0
T145	92514	0	0	0
T146	23508	0	0	0
T270	0	32	0	0
T299	0	95	0	0
T300	0	70	0	0
T360	0	16	0	0
T366	0	112	0	0
T367	0	68	0	0
T368	0	34	0	0
T369	0	25	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	3534	0	0
T8	220734	40	0	0
T13	636756	0	0	0
T32	153944	0	0	0
T47	11927	0	0	0
T81	13971	0	0	0
T104	17663	0	0	0
T119	19844	0	0	0
T140	0	29	0	0
T144	15252	0	0	0
T145	92514	0	0	0
T146	23508	0	0	0
T270	0	58	0	0
T299	0	76	0	0
T300	0	54	0	0
T360	0	37	0	0
T366	0	139	0	0
T367	0	65	0	0
T368	0	29	0	0
T369	0	26	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	4162	0	0
T8	220734	34	0	0
T13	636756	0	0	0
T32	153944	0	0	0
T47	11927	0	0	0
T81	13971	0	0	0
T104	17663	0	0	0
T117	0	93	0	0
T119	19844	0	0	0
T140	0	23	0	0
T144	15252	0	0	0
T145	92514	0	0	0
T146	23508	0	0	0
T246	0	27	0	0
T270	0	31	0	0
T299	0	95	0	0
T360	0	38	0	0
T366	0	165	0	0
T367	0	79	0	0
T368	0	53	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	2741	0	0
T8	220734	21	0	0
T13	636756	0	0	0
T32	153944	0	0	0
T47	11927	0	0	0
T81	13971	0	0	0
T104	17663	0	0	0
T119	19844	0	0	0
T140	0	18	0	0
T144	15252	0	0	0
T145	92514	0	0	0
T146	23508	0	0	0
T270	0	53	0	0
T299	0	91	0	0
T300	0	106	0	0
T360	0	42	0	0
T366	0	119	0	0
T367	0	55	0	0
T368	0	47	0	0
T369	0	27	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	3183	0	0
T8	220734	44	0	0
T13	636756	0	0	0
T32	153944	0	0	0
T47	11927	0	0	0
T81	13971	0	0	0
T104	17663	0	0	0
T119	19844	0	0	0
T140	0	30	0	0
T144	15252	0	0	0
T145	92514	0	0	0
T146	23508	0	0	0
T270	0	86	0	0
T299	0	140	0	0
T300	0	81	0	0
T360	0	85	0	0
T366	0	207	0	0
T367	0	49	0	0
T368	0	86	0	0
T369	0	32	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	2853	0	0
T8	220734	15	0	0
T13	636756	0	0	0
T32	153944	0	0	0
T47	11927	0	0	0
T81	13971	0	0	0
T104	17663	0	0	0
T119	19844	0	0	0
T140	0	48	0	0
T144	15252	0	0	0
T145	92514	0	0	0
T146	23508	0	0	0
T270	0	60	0	0
T299	0	84	0	0
T300	0	86	0	0
T360	0	58	0	0
T366	0	154	0	0
T367	0	53	0	0
T368	0	55	0	0
T369	0	29	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458228655	2727	0	0
T8	220734	14	0	0
T13	636756	0	0	0
T32	153944	0	0	0
T47	11927	0	0	0
T81	13971	0	0	0
T104	17663	0	0	0
T119	19844	0	0	0
T140	0	10	0	0
T144	15252	0	0	0
T145	92514	0	0	0
T146	23508	0	0	0
T270	0	15	0	0
T299	0	80	0	0
T300	0	114	0	0
T360	0	51	0	0
T366	0	122	0	0
T367	0	47	0	0
T368	0	34	0	0
T369	0	18	0	0