Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	100.00	100.00		85.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.73	100.00	100.00	100.00	85.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.52	96.10	96.15	96.71		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.52	96.10	96.15	96.71		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.52	96.10	96.15	96.71		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T5,T11
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T82,T177,T178
1	Covered	T82,T177,T178

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T11

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T2,T5,T11

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T5,T11
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T5,T11
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T53,T73,T30

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T53,T73,T30

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T5,T6
ReadWaitSt	252	Covered	T2,T5,T11
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T5
IdleSt->ReadSt	236	Covered	T2,T5,T6
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T217,T218,T188
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T6,T30,T31
ReadSt->ReadWaitSt	252	Covered	T2,T5,T11
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T2,T5,T11
ResetSt->ErrorSt	315	Covered	T82,T83,T84
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T6,T30,T31
CheckFailError	317	Covered	T82,T177,T178
FsmStateError	289	Covered	T2,T3,T5
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T6,T144,T219
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T30,T31,T65
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T82,T177,T178
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T2,T3,T5
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T6,T30,T31
NoError->CheckFailError	317	Covered	T82,T177,T178
NoError->FsmStateError	289	Covered	T2,T3,T5
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T11

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T11

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T53,T73,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T5,T11
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T41,T111,T70
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T30,T31
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T5,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T5,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T82,T177,T178
1	0	Covered	T82,T177,T178
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T5,T9,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	455232615	454354290	0	0
DigestKnown_A	455232615	454354290	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	455232615	15384	0	0
ErrorKnown_A	455232615	454354290	0	0
FsmStateKnown_A	455232615	454354290	0	0
InitDoneKnown_A	455232615	454354290	0	0
InitReadLocksPartition_A	455232615	103426325	0	0
InitWriteLocksPartition_A	455232615	103426325	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	455232615	454354290	0	0
OtpCmdKnown_A	455232615	454354290	0	0
OtpErrorState_A	455232615	0	0	0
OtpReqKnown_A	455232615	454354290	0	0
OtpSizeKnown_A	455232615	454354290	0	0
OtpWdataKnown_A	455232615	454354290	0	0
ReadLockPropagation_A	455232615	212740312	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	455232615	454354290	0	0
TlulRdataKnown_A	455232615	454354290	0	0
TlulReadOnReadLock_A	455232615	7440	0	0
TlulRerrorKnown_A	455232615	454354290	0	0
TlulRvalidKnown_A	455232615	454354290	0	0
WriteLockPropagation_A	455232615	2086627	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	455232615	26427808	0	0
u_state_regs_A	455232615	454354290	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	15384	0	0
T82	13880	2908	0	0
T177	0	2079	0	0
T178	0	3005	0	0
T179	0	3817	0	0
T180	0	3575	0	0
T184	204852	0	0	0
T185	12966	0	0	0
T186	30679	0	0	0
T187	13658	0	0	0
T188	14765	0	0	0
T189	48879	0	0	0
T190	12219	0	0	0
T191	14044	0	0	0
T192	423172	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	103426325	0	0
T1	23133	312	0	0
T2	17037	4712	0	0
T3	18206	11197	0	0
T4	10591	1151	0	0
T5	155044	52396	0	0
T6	32117	16078	0	0
T9	53801	4409	0	0
T10	22565	15487	0	0
T11	12173	3455	0	0
T12	19058	248	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	103426325	0	0
T1	23133	312	0	0
T2	17037	4712	0	0
T3	18206	11197	0	0
T4	10591	1151	0	0
T5	155044	52396	0	0
T6	32117	16078	0	0
T9	53801	4409	0	0
T10	22565	15487	0	0
T11	12173	3455	0	0
T12	19058	248	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	212740312	0	0
T6	32117	20464	0	0
T7	0	115311	0	0
T8	0	90151	0	0
T10	22565	0	0	0
T11	12173	0	0	0
T12	19058	0	0	0
T30	97743	20165	0	0
T31	0	13827	0	0
T41	0	3223	0	0
T53	29224	5658	0	0
T65	0	13556	0	0
T73	13069	0	0	0
T112	4634	0	0	0
T113	140530	0	0	0
T121	19583	0	0	0
T144	0	8607	0	0
T168	0	31069	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	7440	0	0
T3	18206	9	0	0
T4	10591	0	0	0
T5	155044	9	0	0
T6	32117	3	0	0
T9	53801	0	0	0
T10	22565	2	0	0
T11	12173	0	0	0
T12	19058	0	0	0
T30	0	16	0	0
T31	0	1	0	0
T41	0	4	0	0
T53	29224	0	0	0
T65	0	4	0	0
T73	13069	0	0	0
T113	0	13	0	0
T121	0	4	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	2086627	0	0
T30	97743	4812	0	0
T31	64187	0	0	0
T32	0	4907	0	0
T41	29062	3665	0	0
T46	10665	0	0	0
T65	42383	5070	0	0
T72	13348	0	0	0
T105	0	1368	0	0
T106	0	3114	0	0
T108	0	913	0	0
T109	0	6339	0	0
T110	0	3730	0	0
T112	4634	0	0	0
T113	140530	0	0	0
T114	12561	0	0	0
T115	9143	0	0	0
T116	0	21933	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	26427808	0	0
T30	97743	87139	0	0
T31	64187	49842	0	0
T41	0	22474	0	0
T53	29224	16293	0	0
T65	0	24013	0	0
T72	13348	0	0	0
T73	13069	3065	0	0
T112	4634	0	0	0
T113	140530	0	0	0
T114	12561	0	0	0
T115	9143	0	0	0
T121	19583	0	0	0
T123	0	3945	0	0
T144	0	2479	0	0
T168	0	4603	0	0
T182	0	2053	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T73,T123

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T113,T31,T77

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T82,T84,T177
1	Covered	T82,T84,T177

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T53,T30,T31

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T53,T30,T31

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T6
ReadWaitSt	252	Covered	T1,T2,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T5
IdleSt->ReadSt	236	Covered	T1,T2,T6
InitSt->ErrorSt	315	Covered	T217,T218,T188
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T115,T182,T201
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T6,T53,T30
ReadSt->ReadWaitSt	252	Covered	T1,T2,T6
ReadWaitSt->ErrorSt	276	Covered	T145,T220,T221
ReadWaitSt->IdleSt	270	Covered	T1,T2,T6
ResetSt->ErrorSt	315	Covered	T82,T83,T84
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T6,T53,T30
CheckFailError	317	Covered	T82,T84,T177
FsmStateError	289	Covered	T2,T3,T5
MacroEccCorrError	221	Covered	T11,T73,T113
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T8,T144
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T53,T30,T31
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T82,T84,T177
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T11,T73,T113
MacroEccCorrError->NoError	235	Covered	T31,T77,T56
NoError->AccessError	256	Covered	T6,T53,T30
NoError->CheckFailError	317	Covered	T82,T84,T177
NoError->FsmStateError	289	Covered	T2,T3,T5
NoError->MacroEccCorrError	221	Covered	T11,T73,T113

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T53,T30,T31
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T11,T73,T123
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T115,T182,T201
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T111,T70,T71
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T53,T30
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T113,T31,T77
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T145,T220,T221
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T82,T84,T177
1	0	Covered	T82,T84,T177
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	455232615	454354290	0	0
DigestKnown_A	455232615	454354290	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	455232615	15361	0	0
ErrorKnown_A	455232615	454354290	0	0
FsmStateKnown_A	455232615	454354290	0	0
InitDoneKnown_A	455232615	454354290	0	0
InitReadLocksPartition_A	455232615	103611265	0	0
InitWriteLocksPartition_A	455232615	103611265	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	455232615	454354290	0	0
OtpCmdKnown_A	455232615	454354290	0	0
OtpErrorState_A	455232615	77	0	0
OtpReqKnown_A	455232615	454354290	0	0
OtpSizeKnown_A	455232615	454354290	0	0
OtpWdataKnown_A	455232615	454354290	0	0
ReadLockPropagation_A	455232615	194857236	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	455232615	454354290	0	0
TlulRdataKnown_A	455232615	454354290	0	0
TlulReadOnReadLock_A	455232615	7912	0	0
TlulRerrorKnown_A	455232615	454354290	0	0
TlulRvalidKnown_A	455232615	454354290	0	0
WriteLockPropagation_A	455232615	2280643	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	455232615	25334519	0	0
u_state_regs_A	455232615	454354290	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	15361	0	0
T82	13880	2908	0	0
T84	0	3423	0	0
T177	0	2079	0	0
T179	0	3817	0	0
T181	0	3134	0	0
T184	204852	0	0	0
T185	12966	0	0	0
T186	30679	0	0	0
T187	13658	0	0	0
T188	14765	0	0	0
T189	48879	0	0	0
T190	12219	0	0	0
T191	14044	0	0	0
T192	423172	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	103611265	0	0
T1	23133	380	0	0
T2	17037	4746	0	0
T3	18206	11248	0	0
T4	10591	1202	0	0
T5	155044	52719	0	0
T6	32117	16112	0	0
T9	53801	4528	0	0
T10	22565	15538	0	0
T11	12173	3489	0	0
T12	19058	350	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	103611265	0	0
T1	23133	380	0	0
T2	17037	4746	0	0
T3	18206	11248	0	0
T4	10591	1202	0	0
T5	155044	52719	0	0
T6	32117	16112	0	0
T9	53801	4528	0	0
T10	22565	15538	0	0
T11	12173	3489	0	0
T12	19058	350	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	77	0	0
T7	230994	0	0	0
T15	5605	0	0	0
T41	29062	0	0	0
T46	10665	0	0	0
T51	16247	0	0	0
T65	42383	0	0	0
T115	9143	1	0	0
T123	15419	0	0	0
T138	23272	0	0	0
T145	0	1	0	0
T182	9113	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0
T211	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	194857236	0	0
T3	18206	11042	0	0
T4	10591	0	0	0
T5	155044	0	0	0
T6	32117	20452	0	0
T7	0	115310	0	0
T8	0	90148	0	0
T9	53801	0	0	0
T10	22565	0	0	0
T11	12173	0	0	0
T12	19058	0	0	0
T30	0	22644	0	0
T31	0	8634	0	0
T41	0	3033	0	0
T53	29224	8262	0	0
T65	0	14074	0	0
T73	13069	0	0	0
T168	0	31224	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	7912	0	0
T3	18206	15	0	0
T4	10591	0	0	0
T5	155044	10	0	0
T6	32117	4	0	0
T9	53801	0	0	0
T10	22565	5	0	0
T11	12173	0	0	0
T12	19058	0	0	0
T30	0	11	0	0
T31	0	2	0	0
T41	0	4	0	0
T53	29224	3	0	0
T65	0	4	0	0
T73	13069	0	0	0
T113	0	20	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	2280643	0	0
T30	97743	22834	0	0
T31	64187	9121	0	0
T32	0	4907	0	0
T41	29062	0	0	0
T46	10665	0	0	0
T56	0	4656	0	0
T65	42383	7732	0	0
T70	0	44227	0	0
T72	13348	0	0	0
T105	0	1368	0	0
T109	0	6037	0	0
T112	4634	0	0	0
T113	140530	0	0	0
T114	12561	0	0	0
T115	9143	0	0	0
T117	0	105900	0	0
T128	0	6925	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	25334519	0	0
T30	97743	86907	0	0
T31	64187	49757	0	0
T41	0	13567	0	0
T53	29224	16242	0	0
T65	0	23911	0	0
T72	13348	0	0	0
T73	13069	0	0	0
T112	4634	0	0	0
T113	140530	0	0	0
T114	12561	0	0	0
T115	9143	2457	0	0
T121	19583	0	0	0
T144	0	2462	0	0
T168	0	4569	0	0
T182	0	2048	0	0
T201	0	2524	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T46,T47,T62

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T6,T11
1	Covered	T31,T145,T77

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T84,T177,T179
1	Covered	T84,T177,T179

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T11

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T9
1	1	Covered	T2,T6,T11

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T5,T9
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T5,T9
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T30,T65

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T30,T65

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T5,T9
ReadWaitSt	252	Covered	T2,T5,T9
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T5
IdleSt->ReadSt	236	Covered	T2,T5,T9
InitSt->ErrorSt	315	Covered	T217,T218,T188
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T11,T115,T182
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T53,T30,T31
ReadSt->ReadWaitSt	252	Covered	T2,T5,T9
ReadWaitSt->ErrorSt	276	Covered	T5,T9,T222
ReadWaitSt->IdleSt	270	Covered	T2,T6,T11
ResetSt->ErrorSt	315	Covered	T82,T83,T84
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T53,T30,T31
CheckFailError	317	Covered	T84,T177,T179
FsmStateError	289	Covered	T2,T3,T5
MacroEccCorrError	221	Covered	T31,T46,T47
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T168,T144,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T53,T30,T31
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T84,T177,T179
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T46,T47,T145
MacroEccCorrError->NoError	235	Covered	T31,T77,T56
NoError->AccessError	256	Covered	T53,T30,T31
NoError->CheckFailError	317	Covered	T84,T177,T179
NoError->FsmStateError	289	Covered	T2,T3,T5
NoError->MacroEccCorrError	221	Covered	T31,T46,T47

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T9

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T9

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T30,T65
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T46,T47,T62
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T11,T203,T206
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T5,T9
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T5,T9
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T111,T70,T137
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T53,T30,T31
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T31,T145,T77
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T6,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T5,T9,T222
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T5,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T84,T177,T179
1	0	Covered	T84,T177,T179
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	455232615	454354290	0	0
DigestKnown_A	455232615	454354290	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	455232615	9319	0	0
ErrorKnown_A	455232615	454354290	0	0
FsmStateKnown_A	455232615	454354290	0	0
InitDoneKnown_A	455232615	454354290	0	0
InitReadLocksPartition_A	455232615	103794830	0	0
InitWriteLocksPartition_A	455232615	103794830	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	455232615	454354290	0	0
OtpCmdKnown_A	455232615	454354290	0	0
OtpErrorState_A	455232615	55	0	0
OtpReqKnown_A	455232615	454354290	0	0
OtpSizeKnown_A	455232615	454354290	0	0
OtpWdataKnown_A	455232615	454354290	0	0
ReadLockPropagation_A	455232615	209163059	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	455232615	454354290	0	0
TlulRdataKnown_A	455232615	454354290	0	0
TlulReadOnReadLock_A	455232615	7998	0	0
TlulRerrorKnown_A	455232615	454354290	0	0
TlulRvalidKnown_A	455232615	454354290	0	0
WriteLockPropagation_A	455232615	1498566	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	455232615	16968625	0	0
u_state_regs_A	455232615	454354290	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	9319	0	0
T84	12941	3423	0	0
T167	557147	0	0	0
T177	0	2079	0	0
T179	0	3817	0	0
T193	87185	0	0	0
T194	15142	0	0	0
T195	12293	0	0	0
T196	21246	0	0	0
T197	56001	0	0	0
T198	20450	0	0	0
T199	55604	0	0	0
T200	19160	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	103794830	0	0
T1	23133	448	0	0
T2	17037	4780	0	0
T3	18206	11299	0	0
T4	10591	1253	0	0
T5	155044	53044	0	0
T6	32117	16146	0	0
T9	53801	4649	0	0
T10	22565	15589	0	0
T11	12173	3513	0	0
T12	19058	452	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	103794830	0	0
T1	23133	448	0	0
T2	17037	4780	0	0
T3	18206	11299	0	0
T4	10591	1253	0	0
T5	155044	53044	0	0
T6	32117	16146	0	0
T9	53801	4649	0	0
T10	22565	15589	0	0
T11	12173	3513	0	0
T12	19058	452	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	55	0	0
T5	155044	1	0	0
T6	32117	0	0	0
T9	53801	1	0	0
T10	22565	0	0	0
T11	12173	1	0	0
T12	19058	0	0	0
T30	97743	0	0	0
T53	29224	0	0	0
T73	13069	0	0	0
T121	19583	0	0	0
T191	0	1	0	0
T203	0	1	0	0
T206	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T212	0	1	0	0
T213	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	209163059	0	0
T3	18206	10996	0	0
T4	10591	0	0	0
T5	155044	0	0	0
T6	32117	20444	0	0
T7	0	115185	0	0
T8	0	90138	0	0
T9	53801	0	0	0
T10	22565	0	0	0
T11	12173	0	0	0
T12	19058	0	0	0
T30	0	19358	0	0
T31	0	13531	0	0
T41	0	1971	0	0
T53	29224	8245	0	0
T65	0	13546	0	0
T73	13069	0	0	0
T168	0	34964	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	7998	0	0
T3	18206	8	0	0
T4	10591	0	0	0
T5	155044	16	0	0
T6	32117	2	0	0
T9	53801	0	0	0
T10	22565	1	0	0
T11	12173	0	0	0
T12	19058	0	0	0
T30	0	15	0	0
T31	0	4	0	0
T53	29224	1	0	0
T65	0	8	0	0
T73	13069	0	0	0
T113	0	20	0	0
T121	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	1498566	0	0
T7	230994	0	0	0
T15	5605	0	0	0
T41	29062	3665	0	0
T51	16247	0	0	0
T70	0	14753	0	0
T71	0	58830	0	0
T108	0	1250	0	0
T109	0	6126	0	0
T110	0	2303	0	0
T111	0	4069	0	0
T117	0	33450	0	0
T118	18706	0	0	0
T123	15419	0	0	0
T128	0	3161	0	0
T138	23272	0	0	0
T143	0	7588	0	0
T168	45684	0	0	0
T182	9113	0	0	0
T201	9479	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	16968625	0	0
T11	12173	2715	0	0
T12	19058	0	0	0
T30	97743	86686	0	0
T31	64187	0	0	0
T41	0	22304	0	0
T53	29224	0	0	0
T65	0	23809	0	0
T73	13069	0	0	0
T104	0	9017	0	0
T105	0	30160	0	0
T106	0	14216	0	0
T112	4634	0	0	0
T113	140530	0	0	0
T114	12561	0	0	0
T121	19583	0	0	0
T144	0	2445	0	0
T145	0	9787	0	0
T168	0	4535	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455232615	454354290	0	0
T1	23133	22606	0	0
T2	17037	16759	0	0
T3	18206	17957	0	0
T4	10591	10390	0	0
T5	155044	153432	0	0
T6	32117	31934	0	0
T9	53801	52997	0	0
T10	22565	22334	0	0
T11	12173	11920	0	0
T12	19058	18718	0	0