Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

26825692

1

T1

862

T2

70

T3

504

full_word

8642989

1

T1

251

T2

17

T3

264

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35468391	1			T1	1113		T2	87		T3	768
auto[TlIntgErrCmd]	83	1			T264	4		T266	4		T271	4
auto[TlIntgErrData]	118	1			T264	5		T265	8		T266	2
auto[TlIntgErrBoth]	89	1			T264	1		T265	2		T266	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9990392

1

T1

840

T2

1

T3

467

auto[1]

25478289

1

T1

273

T2

86

T3

301

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6353586	1			T1	709		T3	340		T7	1029
auto[TlIntgErrNone]	partial	auto[1]	20471841	1			T1	153		T2	70		T3	164
auto[TlIntgErrNone]	full_word	auto[0]	3636688	1			T1	131		T2	1		T3	127
auto[TlIntgErrNone]	full_word	auto[1]	5006276	1			T1	120		T2	16		T3	137
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T271	3		T272	1		T273	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T264	1		T266	3		T271	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T264	1		T266	1		T268	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T264	2		T272	1		T365	2
auto[TlIntgErrData]	partial	auto[0]	50	1			T264	2		T265	3		T266	1
auto[TlIntgErrData]	partial	auto[1]	59	1			T264	2		T265	5		T266	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T272	1		T367	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T264	1		T360	1		T368	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T265	1		T360	1		T361	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T264	1		T266	4		T271	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T272	1		T362	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T265	1		T364	1		T359	1