Module Definition
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Module : prim_subreg
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3 94.44 83.33 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4 94.44 83.33 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5 94.44 83.33 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6 94.44 83.33 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7 94.44 83.33 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8 94.44 83.33 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2 94.44 83.33 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3 94.44 83.33 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4 94.44 83.33 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5 94.44 83.33 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0 94.44 83.33 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1 94.44 83.33 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2 94.44 83.33 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3 94.44 83.33 100.00 100.00
tb.dut.u_reg_core.u_intr_state_otp_operation_done 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_state_otp_error 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_otp_operation_done 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_otp_error 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_direct_access_address 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_direct_access_wdata_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_direct_access_wdata_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_check_trigger_regwen 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_check_regwen 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_check_timeout 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_integrity_check_period 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_consistency_check_period 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_vendor_test_read_lock 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_creator_sw_cfg_read_lock 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_owner_sw_cfg_read_lock 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_rot_creator_auth_codesign_read_lock 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_rot_creator_auth_state_read_lock 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field0 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field1 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field2 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field3 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field4 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field0 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field1 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field2 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field3 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field4 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr2 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2 100.00 100.00 100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Module : prim_subreg ( parameter DW=11,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_direct_access_address

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field4

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7
Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 + DW=1,SwAccess=5,RESVAL=1,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_state_otp_operation_done

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_state_otp_error

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_otp_operation_done

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_otp_error

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field0

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field1

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field2

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field1

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field3

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr2

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_check_trigger_regwen

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_check_regwen

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_vendor_test_read_lock

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_creator_sw_cfg_read_lock

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_owner_sw_cfg_read_lock

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_rot_creator_auth_codesign_read_lock

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_rot_creator_auth_state_read_lock

SCORECOND
94.44 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3

SCORECOND
94.44 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4

SCORECOND
94.44 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5

SCORECOND
94.44 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6

SCORECOND
94.44 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7

SCORECOND
94.44 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8

SCORECOND
94.44 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2

SCORECOND
94.44 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4

SCORECOND
94.44 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5

SCORECOND
94.44 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2

SCORECOND
94.44 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7
Cond Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_direct_access_wdata_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_direct_access_wdata_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_check_timeout

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_integrity_check_period

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_consistency_check_period

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7
Cond Coverage for Module : prim_subreg ( parameter DW=16,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field4

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T15,T13
Cond Coverage for Module : prim_subreg ( parameter DW=10,SwAccess=0,RESVAL=0,Mubi=0 + DW=10,SwAccess=3,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field3

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T15,T13
Cond Coverage for Module : prim_subreg ( parameter DW=7,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field0

SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field2

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T15,T13
Cond Coverage for Module : prim_subreg ( parameter DW=3,SwAccess=3,RESVAL=0,Mubi=0 + DW=3,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0

SCORECOND
94.44 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3

SCORECOND
94.44 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T15,T13
Cond Coverage for Module : prim_subreg ( parameter DW=2,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T13,T16
Cond Coverage for Module : prim_subreg ( parameter DW=6,SwAccess=0,RESVAL=0,Mubi=0 + DW=6,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0

SCORECOND
94.44 100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T13,T16
Branch Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T7
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T7
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%