Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25880553

1

T1

3317

T2

3107

T3

4791

full_word

8564576

1

T1

1996

T2

1762

T3

4310

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34444829	1			T1	5313		T2	4869		T3	9101
auto[TlIntgErrCmd]	107	1			T266	3		T267	10		T268	9
auto[TlIntgErrData]	84	1			T266	2		T267	1		T268	6
auto[TlIntgErrBoth]	109	1			T266	5		T267	9		T268	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9716997

1

T1

4857

T2

4442

T3

7710

auto[1]

24728132

1

T1

456

T2

427

T3

1391

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6032394	1			T1	3074		T2	2895		T3	4046
auto[TlIntgErrNone]	partial	auto[1]	19847870	1			T1	243		T2	212		T3	745
auto[TlIntgErrNone]	full_word	auto[0]	3684476	1			T1	1783		T2	1547		T3	3664
auto[TlIntgErrNone]	full_word	auto[1]	4880089	1			T1	213		T2	215		T3	646
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T266	1		T267	5		T268	3
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T266	2		T267	5		T268	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T357	2		T361	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T268	1		T359	1		-	-
auto[TlIntgErrData]	partial	auto[0]	38	1			T266	2		T268	2		T271	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T267	1		T268	4		T356	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T356	1		T362	1		T359	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T356	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T266	2		T267	3		T268	2
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T266	3		T267	6		T268	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T271	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T361	1		-	-		-	-