Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.98	98.05	96.15	97.10		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	487040994	8433879	0	0
check_regwen_rd_A	487040994	4015	0	0
check_timeout_rd_A	487040994	2805	0	0
check_trigger_regwen_rd_A	487040994	4071	0	0
consistency_check_period_rd_A	487040994	4251	0	0
creator_sw_cfg_read_lock_rd_A	487040994	2961	0	0
direct_access_address_rd_A	487040994	2347	0	0
direct_access_wdata_0_rd_A	487040994	1662	0	0
direct_access_wdata_1_rd_A	487040994	1785	0	0
integrity_check_period_rd_A	487040994	4040	0	0
intr_enable_rd_A	487040994	4880	0	0
owner_sw_cfg_read_lock_rd_A	487040994	2831	0	0
rot_creator_auth_codesign_read_lock_rd_A	487040994	2941	0	0
rot_creator_auth_state_read_lock_rd_A	487040994	2840	0	0
vendor_test_read_lock_rd_A	487040994	2694	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	8433879	0	0
T8	339769	104377	0	0
T9	99771	0	0	0
T14	0	132777	0	0
T15	0	74516	0	0
T18	5027	0	0	0
T19	86975	0	0	0
T20	0	62528	0	0
T21	0	89769	0	0
T31	81034	0	0	0
T40	0	35379	0	0
T44	12179	0	0	0
T50	11118	0	0	0
T56	11644	0	0	0
T100	0	119136	0	0
T110	16906	0	0	0
T150	41957	0	0	0
T259	0	51383	0	0
T274	0	108139	0	0
T275	0	81087	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	4015	0	0
T25	109493	0	0	0
T32	88448	0	0	0
T58	17159	0	0	0
T100	594441	116	0	0
T101	21316	0	0	0
T102	6744	0	0	0
T103	31316	0	0	0
T141	999969	0	0	0
T163	10634	0	0	0
T193	9555	0	0	0
T243	0	52	0	0
T251	0	150	0	0
T252	0	97	0	0
T282	0	30	0	0
T335	0	112	0	0
T338	0	160	0	0
T339	0	88	0	0
T340	0	57	0	0
T341	0	61	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	2805	0	0
T25	109493	0	0	0
T32	88448	0	0	0
T58	17159	0	0	0
T100	594441	116	0	0
T101	21316	0	0	0
T102	6744	0	0	0
T103	31316	0	0	0
T141	999969	0	0	0
T163	10634	0	0	0
T193	9555	0	0	0
T243	0	54	0	0
T251	0	165	0	0
T252	0	131	0	0
T282	0	31	0	0
T335	0	115	0	0
T338	0	170	0	0
T339	0	87	0	0
T340	0	71	0	0
T341	0	49	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	4071	0	0
T25	109493	0	0	0
T32	88448	0	0	0
T58	17159	0	0	0
T100	594441	187	0	0
T101	21316	0	0	0
T102	6744	0	0	0
T103	31316	0	0	0
T141	999969	0	0	0
T163	10634	0	0	0
T193	9555	0	0	0
T243	0	40	0	0
T251	0	123	0	0
T252	0	163	0	0
T282	0	17	0	0
T335	0	102	0	0
T338	0	121	0	0
T339	0	67	0	0
T340	0	77	0	0
T341	0	59	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	4251	0	0
T25	109493	0	0	0
T32	88448	0	0	0
T58	17159	0	0	0
T100	594441	145	0	0
T101	21316	0	0	0
T102	6744	0	0	0
T103	31316	0	0	0
T141	999969	0	0	0
T163	10634	0	0	0
T193	9555	0	0	0
T243	0	81	0	0
T251	0	200	0	0
T252	0	130	0	0
T282	0	32	0	0
T335	0	117	0	0
T338	0	212	0	0
T339	0	66	0	0
T340	0	30	0	0
T341	0	79	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	2961	0	0
T25	109493	0	0	0
T32	88448	0	0	0
T58	17159	0	0	0
T100	594441	130	0	0
T101	21316	0	0	0
T102	6744	0	0	0
T103	31316	0	0	0
T141	999969	0	0	0
T163	10634	0	0	0
T193	9555	0	0	0
T243	0	65	0	0
T251	0	155	0	0
T252	0	142	0	0
T282	0	40	0	0
T335	0	190	0	0
T338	0	170	0	0
T339	0	81	0	0
T340	0	35	0	0
T341	0	48	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	2347	0	0
T25	109493	0	0	0
T32	88448	0	0	0
T58	17159	0	0	0
T100	594441	161	0	0
T101	21316	0	0	0
T102	6744	0	0	0
T103	31316	0	0	0
T141	999969	0	0	0
T163	10634	0	0	0
T193	9555	0	0	0
T243	0	44	0	0
T251	0	172	0	0
T252	0	171	0	0
T282	0	18	0	0
T335	0	119	0	0
T338	0	174	0	0
T339	0	109	0	0
T340	0	67	0	0
T341	0	62	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	1662	0	0
T25	109493	0	0	0
T32	88448	0	0	0
T58	17159	0	0	0
T100	594441	135	0	0
T101	21316	0	0	0
T102	6744	0	0	0
T103	31316	0	0	0
T141	999969	0	0	0
T163	10634	0	0	0
T193	9555	0	0	0
T243	0	35	0	0
T251	0	91	0	0
T252	0	107	0	0
T282	0	7	0	0
T335	0	127	0	0
T338	0	74	0	0
T339	0	36	0	0
T340	0	48	0	0
T341	0	33	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	1785	0	0
T25	109493	0	0	0
T32	88448	0	0	0
T58	17159	0	0	0
T100	594441	78	0	0
T101	21316	0	0	0
T102	6744	0	0	0
T103	31316	0	0	0
T141	999969	0	0	0
T163	10634	0	0	0
T193	9555	0	0	0
T243	0	37	0	0
T251	0	133	0	0
T252	0	112	0	0
T282	0	6	0	0
T335	0	119	0	0
T338	0	130	0	0
T339	0	48	0	0
T340	0	45	0	0
T341	0	41	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	4040	0	0
T25	109493	0	0	0
T32	88448	0	0	0
T58	17159	0	0	0
T100	594441	187	0	0
T101	21316	0	0	0
T102	6744	0	0	0
T103	31316	0	0	0
T141	999969	0	0	0
T163	10634	0	0	0
T193	9555	0	0	0
T243	0	34	0	0
T251	0	123	0	0
T252	0	93	0	0
T282	0	26	0	0
T335	0	119	0	0
T338	0	148	0	0
T339	0	73	0	0
T340	0	96	0	0
T341	0	67	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	4880	0	0
T57	11811	0	0	0
T67	14332	0	0	0
T68	19268	0	0	0
T100	0	165	0	0
T108	959612	45	0	0
T109	102682	0	0	0
T119	572135	0	0	0
T141	0	24	0	0
T158	115643	0	0	0
T190	10171	0	0	0
T203	79592	0	0	0
T242	19087	0	0	0
T243	0	55	0	0
T251	0	187	0	0
T252	0	202	0	0
T335	0	98	0	0
T338	0	207	0	0
T339	0	122	0	0
T342	0	5	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	2831	0	0
T25	109493	0	0	0
T32	88448	0	0	0
T58	17159	0	0	0
T100	594441	153	0	0
T101	21316	0	0	0
T102	6744	0	0	0
T103	31316	0	0	0
T141	999969	0	0	0
T163	10634	0	0	0
T193	9555	0	0	0
T243	0	55	0	0
T251	0	165	0	0
T252	0	145	0	0
T282	0	37	0	0
T335	0	108	0	0
T338	0	124	0	0
T339	0	90	0	0
T340	0	61	0	0
T341	0	53	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	2941	0	0
T25	109493	0	0	0
T32	88448	0	0	0
T58	17159	0	0	0
T100	594441	111	0	0
T101	21316	0	0	0
T102	6744	0	0	0
T103	31316	0	0	0
T141	999969	0	0	0
T163	10634	0	0	0
T193	9555	0	0	0
T243	0	69	0	0
T251	0	137	0	0
T252	0	122	0	0
T282	0	38	0	0
T335	0	106	0	0
T338	0	191	0	0
T339	0	73	0	0
T340	0	77	0	0
T341	0	78	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	2840	0	0
T25	109493	0	0	0
T32	88448	0	0	0
T58	17159	0	0	0
T100	594441	208	0	0
T101	21316	0	0	0
T102	6744	0	0	0
T103	31316	0	0	0
T141	999969	0	0	0
T163	10634	0	0	0
T193	9555	0	0	0
T243	0	43	0	0
T251	0	179	0	0
T252	0	122	0	0
T282	0	37	0	0
T335	0	118	0	0
T338	0	157	0	0
T339	0	67	0	0
T340	0	90	0	0
T341	0	51	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487040994	2694	0	0
T25	109493	0	0	0
T32	88448	0	0	0
T58	17159	0	0	0
T100	594441	141	0	0
T101	21316	0	0	0
T102	6744	0	0	0
T103	31316	0	0	0
T141	999969	0	0	0
T163	10634	0	0	0
T193	9555	0	0	0
T243	0	49	0	0
T251	0	104	0	0
T252	0	89	0	0
T282	0	42	0	0
T335	0	64	0	0
T338	0	162	0	0
T339	0	94	0	0
T340	0	25	0	0
T341	0	34	0	0