Unified Coverage Report :: Module :: prim_ram_1p_adv

Module : prim_ram_1p_adv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.58	98.31	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.45	97.27	100.00		100.00	100.00	100.00	gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_mem	98.85	96.55				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_ram_1p_adv

	Line No.	Total	Covered	Percent
TOTAL		30	30	100.00
ALWAYS	106	3	3	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	210	0	0
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
ALWAYS	226	11	11	100.00
ALWAYS	251	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
106	1	1
107	1	1
109	1	1
113	1	1
114	1	1
115	1	1
116	1	1
117	1	1
118	1	1
210		unreachable
211	1	1
213	1	1
217	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
251	1	1
252	1	1
253	1	1
254	1	1
256	1	1
257	1	1
259	1	1

---

Cond Coverage for Module : prim_ram_1p_adv

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       109
 EXPRESSION (req_q & ((~write_q)))
             --1--   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_ram_1p_adv

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	106	2	2	100.00
IF	226	2	2	100.00
IF	251	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	106	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	226	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	251	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_ram_1p_adv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CannotHaveEccAndParity_A	1151	1151	0	0

CannotHaveEccAndParity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0