Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

28843089

1

T1

86

T2

578

T3

4752

full_word

9342219

1

T1

28

T2

240

T3

4356

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	38185028	1			T1	114		T2	818		T3	9108
auto[TlIntgErrCmd]	97	1			T270	4		T271	3		T272	6
auto[TlIntgErrData]	82	1			T270	8		T271	1		T272	3
auto[TlIntgErrBoth]	101	1			T270	8		T271	6		T272	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10285635

1

T1

1

T2

521

T3

7699

auto[1]

27899673

1

T1

113

T2

297

T3

1409

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6430203	1			T2	404		T3	4005		T4	5335
auto[TlIntgErrNone]	partial	auto[1]	22412629	1			T1	86		T2	174		T3	747
auto[TlIntgErrNone]	full_word	auto[0]	3855324	1			T1	1		T2	117		T3	3694
auto[TlIntgErrNone]	full_word	auto[1]	5486872	1			T1	27		T2	123		T3	662
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T270	1		T271	2		T272	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T270	3		T272	2		T278	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T272	2		T372	1		T377	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T271	1		T378	1		T379	1
auto[TlIntgErrData]	partial	auto[0]	32	1			T270	2		T271	1		T272	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T270	6		T272	1		T278	4
auto[TlIntgErrData]	full_word	auto[0]	2	1			T374	1		T380	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T278	1		T371	1		T372	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T270	6		T271	2		T278	3
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T270	2		T271	3		T272	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T374	1		T376	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T271	1		T380	3		T372	1