Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.86	97.40	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	533639534	9535311	0	0
check_regwen_rd_A	533639534	2857	0	0
check_timeout_rd_A	533639534	2626	0	0
check_trigger_regwen_rd_A	533639534	2871	0	0
consistency_check_period_rd_A	533639534	3074	0	0
creator_sw_cfg_read_lock_rd_A	533639534	2523	0	0
direct_access_address_rd_A	533639534	2329	0	0
direct_access_wdata_0_rd_A	533639534	1401	0	0
direct_access_wdata_1_rd_A	533639534	1531	0	0
integrity_check_period_rd_A	533639534	2865	0	0
intr_enable_rd_A	533639534	3611	0	0
owner_sw_cfg_read_lock_rd_A	533639534	2302	0	0
rot_creator_auth_codesign_read_lock_rd_A	533639534	2504	0	0
rot_creator_auth_state_read_lock_rd_A	533639534	2460	0	0
vendor_test_read_lock_rd_A	533639534	2216	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	9535311	0	0
T6	475481	70962	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	124820	0	0
T12	0	47269	0	0
T14	0	52366	0	0
T15	0	41020	0	0
T26	63057	0	0	0
T33	0	109278	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T191	0	57584	0	0
T192	0	88344	0	0
T280	0	161684	0	0
T281	0	24134	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	2857	0	0
T6	475481	118	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	83	0	0
T16	0	68	0	0
T26	63057	0	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T192	0	58	0	0
T246	0	86	0	0
T260	0	103	0	0
T281	0	43	0	0
T359	0	140	0	0
T360	0	65	0	0
T361	0	60	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	2626	0	0
T6	475481	117	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	88	0	0
T16	0	94	0	0
T26	63057	0	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T192	0	71	0	0
T246	0	55	0	0
T260	0	118	0	0
T281	0	14	0	0
T359	0	126	0	0
T360	0	95	0	0
T361	0	47	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	2871	0	0
T6	475481	93	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	105	0	0
T16	0	109	0	0
T26	63057	0	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T192	0	38	0	0
T246	0	43	0	0
T260	0	67	0	0
T281	0	2	0	0
T359	0	95	0	0
T360	0	83	0	0
T361	0	50	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	3074	0	0
T6	475481	119	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	98	0	0
T16	0	139	0	0
T26	63057	0	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T192	0	33	0	0
T246	0	40	0	0
T260	0	76	0	0
T281	0	21	0	0
T359	0	99	0	0
T360	0	54	0	0
T361	0	36	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	2523	0	0
T6	475481	135	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	102	0	0
T16	0	159	0	0
T26	63057	0	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T192	0	48	0	0
T246	0	47	0	0
T260	0	108	0	0
T281	0	42	0	0
T359	0	75	0	0
T360	0	83	0	0
T361	0	68	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	2329	0	0
T6	475481	128	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	100	0	0
T16	0	109	0	0
T26	63057	0	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T192	0	35	0	0
T246	0	60	0	0
T260	0	122	0	0
T281	0	21	0	0
T359	0	131	0	0
T360	0	104	0	0
T361	0	37	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	1401	0	0
T6	475481	56	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	75	0	0
T16	0	69	0	0
T26	63057	0	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T192	0	55	0	0
T246	0	10	0	0
T260	0	40	0	0
T281	0	26	0	0
T359	0	116	0	0
T360	0	90	0	0
T361	0	17	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	1531	0	0
T6	475481	49	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	42	0	0
T16	0	114	0	0
T26	63057	0	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T192	0	53	0	0
T246	0	26	0	0
T260	0	29	0	0
T281	0	13	0	0
T359	0	56	0	0
T360	0	30	0	0
T361	0	34	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	2865	0	0
T6	475481	123	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	70	0	0
T16	0	92	0	0
T26	63057	0	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T192	0	85	0	0
T246	0	55	0	0
T260	0	98	0	0
T281	0	27	0	0
T359	0	111	0	0
T360	0	69	0	0
T361	0	37	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	3611	0	0
T6	475481	77	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	139	0	0
T16	0	116	0	0
T26	63057	0	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T65	0	21	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T130	0	36	0	0
T192	0	66	0	0
T260	0	96	0	0
T281	0	15	0	0
T288	0	13	0	0
T362	0	25	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	2302	0	0
T6	475481	101	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	81	0	0
T16	0	111	0	0
T26	63057	0	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T192	0	63	0	0
T246	0	51	0	0
T260	0	83	0	0
T281	0	33	0	0
T359	0	111	0	0
T360	0	85	0	0
T361	0	37	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	2504	0	0
T6	475481	73	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	45	0	0
T16	0	108	0	0
T26	63057	0	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T192	0	50	0	0
T246	0	50	0	0
T260	0	94	0	0
T281	0	14	0	0
T359	0	108	0	0
T360	0	121	0	0
T361	0	44	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	2460	0	0
T6	475481	90	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	85	0	0
T16	0	58	0	0
T26	63057	0	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T192	0	33	0	0
T246	0	42	0	0
T260	0	100	0	0
T281	0	24	0	0
T359	0	91	0	0
T360	0	63	0	0
T361	0	68	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533639534	2216	0	0
T6	475481	67	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T10	20961	0	0	0
T11	0	77	0	0
T16	0	136	0	0
T26	63057	0	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T70	15054	0	0	0
T111	11023	0	0	0
T192	0	47	0	0
T246	0	46	0	0
T260	0	100	0	0
T281	0	22	0	0
T359	0	71	0	0
T360	0	53	0	0
T361	0	61	0	0