Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.86	97.40	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.86	97.40	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T84,T23,T140

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T64,T34,T67

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T81,T141,T142
1	Covered	T81,T141,T142

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T9
1	1	Covered	T2,T6,T7

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T42,T26

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T42,T26

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T9,T6
ReadWaitSt	252	Covered	T2,T6,T7
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T4
IdleSt->ReadSt	236	Covered	T2,T9,T6
InitSt->ErrorSt	315	Covered	T109,T146,T187
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T72,T128,T148
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T9,T6,T7
ReadSt->ReadWaitSt	252	Covered	T2,T6,T7
ReadWaitSt->ErrorSt	276	Covered	T147,T168,T174
ReadWaitSt->IdleSt	270	Covered	T2,T6,T7
ResetSt->ErrorSt	315	Covered	T42,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T9,T6,T7
CheckFailError	317	Covered	T81,T141,T142
FsmStateError	289	Covered	T2,T3,T4
MacroEccCorrError	221	Covered	T64,T34,T67
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T129,T11
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T9,T6,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T81,T141,T142
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T64,T84,T147
MacroEccCorrError->NoError	235	Covered	T64,T34,T67
NoError->AccessError	256	Covered	T9,T6,T7
NoError->CheckFailError	317	Covered	T81,T141,T142
NoError->FsmStateError	289	Covered	T2,T3,T4
NoError->MacroEccCorrError	221	Covered	T64,T34,T67

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T7

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T7

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T42,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T84,T23,T140
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T128,T166,T97
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T9,T6
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T6,T7
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T7,T35,T11
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T9,T6,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T64,T34,T67
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T6,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T147,T168,T174
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T6,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T81,T141,T142
1	0	Covered	T81,T141,T142
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	530865084	529979703	0	0
DigestKnown_A	530865084	529979703	0	0
DigestOffsetMustBeRepresentable_A	1154	1154	0	0
EccErrorState_A	530865084	9562	0	0
ErrorKnown_A	530865084	529979703	0	0
FsmStateKnown_A	530865084	529979703	0	0
InitDoneKnown_A	530865084	529979703	0	0
InitReadLocksPartition_A	530865084	113918790	0	0
InitWriteLocksPartition_A	530865084	113918790	0	0
OffsetMustBeBlockAligned_A	1154	1154	0	0
OtpAddrKnown_A	530865084	529979703	0	0
OtpCmdKnown_A	530865084	529979703	0	0
OtpErrorState_A	530865084	44	0	0
OtpReqKnown_A	530865084	529979703	0	0
OtpSizeKnown_A	530865084	529979703	0	0
OtpWdataKnown_A	530865084	529979703	0	0
ReadLockPropagation_A	530865084	239944979	0	0
SizeMustBeBlockAligned_A	1154	1154	0	0
TlulGntKnown_A	530865084	529979703	0	0
TlulRdataKnown_A	530865084	529979703	0	0
TlulReadOnReadLock_A	530865084	8168	0	0
TlulRerrorKnown_A	530865084	529979703	0	0
TlulRvalidKnown_A	530865084	529979703	0	0
WriteLockPropagation_A	530865084	2293714	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	530865084	26543805	0	0
u_state_regs_A	530865084	529979703	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	9562	0	0
T33	526763	0	0	0
T45	118416	0	0	0
T81	14599	2822	0	0
T141	0	3502	0	0
T142	0	3238	0	0
T189	43983	0	0	0
T190	195098	0	0	0
T191	625711	0	0	0
T192	475786	0	0	0
T193	71149	0	0	0
T194	27195	0	0	0
T195	35071	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	113918790	0	0
T1	54412	1012	0	0
T2	19016	4460	0	0
T3	70543	57111	0	0
T4	90335	81945	0	0
T5	28065	695	0	0
T6	475481	186632	0	0
T7	23526	1022	0	0
T8	132191	116075	0	0
T9	12916	603	0	0
T10	20961	5299	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	113918790	0	0
T1	54412	1012	0	0
T2	19016	4460	0	0
T3	70543	57111	0	0
T4	90335	81945	0	0
T5	28065	695	0	0
T6	475481	186632	0	0
T7	23526	1022	0	0
T8	132191	116075	0	0
T9	12916	603	0	0
T10	20961	5299	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	44	0	0
T53	11897	0	0	0
T69	11077	0	0	0
T97	0	1	0	0
T110	24253	0	0	0
T112	21023	0	0	0
T113	16125	0	0	0
T128	15865	1	0	0
T129	28482	0	0	0
T146	22555	0	0	0
T147	0	1	0	0
T166	0	1	0	0
T168	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T179	99257	0	0	0
T180	4201	0	0	0
T196	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	239944979	0	0
T5	28065	2776	0	0
T6	475481	307501	0	0
T7	23526	2317	0	0
T8	132191	0	0	0
T9	12916	1249	0	0
T10	20961	0	0	0
T13	0	1866	0	0
T26	0	5384	0	0
T34	0	1603	0	0
T35	0	4608	0	0
T42	21968	0	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T65	0	117925	0	0
T70	15054	0	0	0
T107	0	4605	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	8168	0	0
T3	70543	12	0	0
T4	90335	27	0	0
T5	28065	0	0	0
T6	475481	73	0	0
T7	23526	2	0	0
T8	132191	15	0	0
T9	12916	1	0	0
T10	20961	0	0	0
T26	0	3	0	0
T35	0	5	0	0
T42	0	1	0	0
T50	23690	0	0	0
T64	0	3	0	0
T70	15054	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	2293714	0	0
T35	75357	3314	0	0
T65	339660	34869	0	0
T66	0	8810	0	0
T67	0	1760	0	0
T71	14210	0	0	0
T72	9364	0	0	0
T76	0	10767	0	0
T102	0	7181	0	0
T104	0	3960	0	0
T105	0	19794	0	0
T107	34750	0	0	0
T108	30361	0	0	0
T109	21634	0	0	0
T110	24253	0	0	0
T127	0	4492	0	0
T128	15865	0	0	0
T129	28482	0	0	0
T133	0	52215	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	26543805	0	0
T5	28065	18420	0	0
T6	475481	0	0	0
T7	23526	0	0	0
T8	132191	0	0	0
T9	12916	0	0	0
T10	20961	0	0	0
T26	0	51458	0	0
T34	0	17362	0	0
T35	0	63991	0	0
T42	21968	3385	0	0
T50	23690	0	0	0
T64	96333	0	0	0
T65	0	272164	0	0
T70	15054	0	0	0
T106	0	18239	0	0
T107	0	25630	0	0
T108	0	2897	0	0
T109	0	2703	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T71,T84,T135

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T76,T44,T77

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T145,T142
1	Covered	T145,T142

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T3,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T70,T26,T34

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T70,T26,T34

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T5
ReadWaitSt	252	Covered	T2,T3,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T4
IdleSt->ReadSt	236	Covered	T2,T3,T5
InitSt->ErrorSt	315	Covered	T72,T109,T146
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T70,T128,T166
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T5,T9
ReadSt->ReadWaitSt	252	Covered	T2,T3,T5
ReadWaitSt->ErrorSt	276	Covered	T95,T147,T199
ReadWaitSt->IdleSt	270	Covered	T2,T3,T5
ResetSt->ErrorSt	315	Covered	T42,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T5,T9
CheckFailError	317	Covered	T145,T142
FsmStateError	289	Covered	T2,T3,T4
MacroEccCorrError	221	Covered	T71,T76,T84
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T3,T6,T179
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T5,T9
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T145,T142
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T71,T84,T147
MacroEccCorrError->NoError	235	Covered	T76,T44,T77
NoError->AccessError	256	Covered	T3,T5,T9
NoError->CheckFailError	317	Covered	T145,T142
NoError->FsmStateError	289	Covered	T2,T4,T6
NoError->MacroEccCorrError	221	Covered	T71,T76,T84

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T70,T26,T34
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T71,T84,T135
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T70,T200,T201
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T35,T107
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T76,T44,T77
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T95,T147,T199
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T4,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T145,T142
1	0	Covered	T145,T142
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	530865084	529979703	0	0
DigestKnown_A	530865084	529979703	0	0
DigestOffsetMustBeRepresentable_A	1154	1154	0	0
EccErrorState_A	530865084	7000	0	0
ErrorKnown_A	530865084	529979703	0	0
FsmStateKnown_A	530865084	529979703	0	0
InitDoneKnown_A	530865084	529979703	0	0
InitReadLocksPartition_A	530865084	114101457	0	0
InitWriteLocksPartition_A	530865084	114101457	0	0
OffsetMustBeBlockAligned_A	1154	1154	0	0
OtpAddrKnown_A	530865084	529979703	0	0
OtpCmdKnown_A	530865084	529979703	0	0
OtpErrorState_A	530865084	37	0	0
OtpReqKnown_A	530865084	529979703	0	0
OtpSizeKnown_A	530865084	529979703	0	0
OtpWdataKnown_A	530865084	529979703	0	0
ReadLockPropagation_A	530865084	239810074	0	0
SizeMustBeBlockAligned_A	1154	1154	0	0
TlulGntKnown_A	530865084	529979703	0	0
TlulRdataKnown_A	530865084	529979703	0	0
TlulReadOnReadLock_A	530865084	7942	0	0
TlulRerrorKnown_A	530865084	529979703	0	0
TlulRvalidKnown_A	530865084	529979703	0	0
WriteLockPropagation_A	530865084	826638	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	530865084	10102632	0	0
u_state_regs_A	530865084	529979703	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	7000	0	0
T23	15109	0	0	0
T142	0	3238	0	0
T145	9874	3762	0	0
T149	44565	0	0	0
T150	30876	0	0	0
T151	37093	0	0	0
T152	130498	0	0	0
T153	11728	0	0	0
T154	13696	0	0	0
T155	72442	0	0	0
T156	187339	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	114101457	0	0
T1	54412	1029	0	0
T2	19016	4511	0	0
T3	70543	57145	0	0
T4	90335	81996	0	0
T5	28065	814	0	0
T6	475481	186654	0	0
T7	23526	1124	0	0
T8	132191	116109	0	0
T9	12916	688	0	0
T10	20961	5350	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	114101457	0	0
T1	54412	1029	0	0
T2	19016	4511	0	0
T3	70543	57145	0	0
T4	90335	81996	0	0
T5	28065	814	0	0
T6	475481	186654	0	0
T7	23526	1124	0	0
T8	132191	116109	0	0
T9	12916	688	0	0
T10	20961	5350	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	37	0	0
T13	32621	0	0	0
T26	63057	0	0	0
T34	27459	0	0	0
T35	75357	0	0	0
T42	21968	0	0	0
T64	96333	0	0	0
T70	15054	1	0	0
T95	0	1	0	0
T106	22348	0	0	0
T107	34750	0	0	0
T111	11023	0	0	0
T140	0	1	0	0
T147	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	239810074	0	0
T3	70543	61192	0	0
T4	90335	0	0	0
T5	28065	2621	0	0
T6	475481	306115	0	0
T7	23526	3521	0	0
T8	132191	0	0	0
T9	12916	1247	0	0
T10	20961	0	0	0
T13	0	1403	0	0
T26	0	5636	0	0
T34	0	1601	0	0
T35	0	6081	0	0
T50	23690	0	0	0
T70	15054	0	0	0
T106	0	1092	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	7942	0	0
T3	70543	14	0	0
T4	90335	28	0	0
T5	28065	3	0	0
T6	475481	68	0	0
T7	23526	3	0	0
T8	132191	20	0	0
T9	12916	1	0	0
T10	20961	0	0	0
T34	0	1	0	0
T42	0	2	0	0
T50	23690	0	0	0
T64	0	1	0	0
T70	15054	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	826638	0	0
T13	32621	0	0	0
T26	63057	3322	0	0
T34	27459	695	0	0
T35	75357	0	0	0
T71	14210	0	0	0
T72	9364	0	0	0
T76	0	10767	0	0
T98	0	11289	0	0
T100	0	4086	0	0
T102	0	2726	0	0
T103	0	4378	0	0
T104	0	3895	0	0
T106	22348	0	0	0
T107	34750	0	0	0
T108	30361	0	0	0
T111	11023	0	0	0
T133	0	13939	0	0
T182	0	8203	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	10102632	0	0
T13	32621	11323	0	0
T26	63057	51288	0	0
T34	27459	17277	0	0
T35	75357	0	0	0
T42	21968	0	0	0
T64	96333	0	0	0
T66	0	22978	0	0
T70	15054	3665	0	0
T76	0	66425	0	0
T78	0	12804	0	0
T101	0	29882	0	0
T102	0	82074	0	0
T106	22348	0	0	0
T107	34750	0	0	0
T109	0	2669	0	0
T111	11023	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530865084	529979703	0	0
T1	54412	54316	0	0
T2	19016	18765	0	0
T3	70543	70331	0	0
T4	90335	90055	0	0
T5	28065	27559	0	0
T6	475481	475454	0	0
T7	23526	23014	0	0
T8	132191	131951	0	0
T9	12916	12500	0	0
T10	20961	20705	0	0