Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.05	93.83	96.30	95.68	92.84	97.00	96.33	93.35

Total test records in report: 1329

T1260	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1216747777	Apr 30 03:38:02 PM PDT 24	Apr 30 03:38:03 PM PDT 24	77632792 ps
T314	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2928875817	Apr 30 03:37:46 PM PDT 24	Apr 30 03:37:51 PM PDT 24	148017139 ps
T1261	/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.180208846	Apr 30 03:39:04 PM PDT 24	Apr 30 03:39:06 PM PDT 24	81049028 ps
T1262	/workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.479112133	Apr 30 03:39:44 PM PDT 24	Apr 30 03:39:46 PM PDT 24	39285190 ps
T342	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.311332569	Apr 30 03:39:04 PM PDT 24	Apr 30 03:39:06 PM PDT 24	75755568 ps
T1263	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3079199883	Apr 30 03:37:07 PM PDT 24	Apr 30 03:37:09 PM PDT 24	517494701 ps
T1264	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.4184260817	Apr 30 03:38:33 PM PDT 24	Apr 30 03:38:54 PM PDT 24	18993445698 ps
T1265	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.610034394	Apr 30 03:38:19 PM PDT 24	Apr 30 03:38:26 PM PDT 24	179268540 ps
T1266	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.4098844039	Apr 30 03:38:28 PM PDT 24	Apr 30 03:38:39 PM PDT 24	10370408329 ps
T1267	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.493498780	Apr 30 03:39:06 PM PDT 24	Apr 30 03:39:08 PM PDT 24	133326931 ps
T1268	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2243909932	Apr 30 03:37:09 PM PDT 24	Apr 30 03:37:13 PM PDT 24	1460555386 ps
T1269	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.668287942	Apr 30 03:37:44 PM PDT 24	Apr 30 03:37:49 PM PDT 24	121934129 ps
T1270	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1266903439	Apr 30 03:37:44 PM PDT 24	Apr 30 03:37:48 PM PDT 24	1629888691 ps
T1271	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3959051993	Apr 30 03:38:42 PM PDT 24	Apr 30 03:38:45 PM PDT 24	82965510 ps
T1272	/workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.4002176505	Apr 30 03:39:32 PM PDT 24	Apr 30 03:39:34 PM PDT 24	55661119 ps
T375	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3650241662	Apr 30 03:37:28 PM PDT 24	Apr 30 03:37:41 PM PDT 24	2467735557 ps
T1273	/workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1271528238	Apr 30 03:38:02 PM PDT 24	Apr 30 03:38:04 PM PDT 24	45509715 ps
T1274	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3932273646	Apr 30 03:38:28 PM PDT 24	Apr 30 03:38:36 PM PDT 24	669429777 ps
T1275	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2198013005	Apr 30 03:38:57 PM PDT 24	Apr 30 03:39:01 PM PDT 24	1595065551 ps
T1276	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.1390117473	Apr 30 03:39:24 PM PDT 24	Apr 30 03:39:27 PM PDT 24	588361253 ps
T1277	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.2861779825	Apr 30 03:38:57 PM PDT 24	Apr 30 03:39:00 PM PDT 24	184056193 ps
T1278	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1383422567	Apr 30 03:38:13 PM PDT 24	Apr 30 03:38:26 PM PDT 24	6750207431 ps
T1279	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.522332359	Apr 30 03:37:58 PM PDT 24	Apr 30 03:38:04 PM PDT 24	431976048 ps
T1280	/workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1129084049	Apr 30 03:38:10 PM PDT 24	Apr 30 03:38:12 PM PDT 24	155403060 ps
T1281	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3155510716	Apr 30 03:38:13 PM PDT 24	Apr 30 03:38:15 PM PDT 24	579715441 ps
T1282	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.181916719	Apr 30 03:39:09 PM PDT 24	Apr 30 03:39:12 PM PDT 24	425837704 ps
T1283	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3259590383	Apr 30 03:38:34 PM PDT 24	Apr 30 03:38:37 PM PDT 24	1653069913 ps
T1284	/workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.578437606	Apr 30 03:39:37 PM PDT 24	Apr 30 03:39:39 PM PDT 24	68380592 ps
T1285	/workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3159872394	Apr 30 03:38:23 PM PDT 24	Apr 30 03:38:26 PM PDT 24	255703536 ps
T1286	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2985848544	Apr 30 03:38:55 PM PDT 24	Apr 30 03:39:02 PM PDT 24	163242781 ps
T1287	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.1847819475	Apr 30 03:37:59 PM PDT 24	Apr 30 03:38:01 PM PDT 24	56629276 ps
T1288	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.445729431	Apr 30 03:38:56 PM PDT 24	Apr 30 03:39:01 PM PDT 24	128883866 ps
T1289	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2899274751	Apr 30 03:37:53 PM PDT 24	Apr 30 03:37:54 PM PDT 24	40598838 ps
T1290	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2126665707	Apr 30 03:39:23 PM PDT 24	Apr 30 03:39:26 PM PDT 24	204720434 ps
T373	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1704353724	Apr 30 03:38:01 PM PDT 24	Apr 30 03:38:13 PM PDT 24	1598434834 ps
T1291	/workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3416955406	Apr 30 03:39:35 PM PDT 24	Apr 30 03:39:37 PM PDT 24	155556452 ps
T1292	/workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.4249510705	Apr 30 03:39:36 PM PDT 24	Apr 30 03:39:38 PM PDT 24	39299896 ps
T1293	/workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.796983546	Apr 30 03:39:36 PM PDT 24	Apr 30 03:39:38 PM PDT 24	42541907 ps
T1294	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1657712726	Apr 30 03:38:22 PM PDT 24	Apr 30 03:38:34 PM PDT 24	1263383292 ps
T1295	/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3224837995	Apr 30 03:38:55 PM PDT 24	Apr 30 03:38:57 PM PDT 24	70210543 ps
T1296	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1489038497	Apr 30 03:39:07 PM PDT 24	Apr 30 03:39:09 PM PDT 24	37756865 ps
T1297	/workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.938760820	Apr 30 03:39:43 PM PDT 24	Apr 30 03:39:45 PM PDT 24	536001439 ps
T1298	/workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3737885067	Apr 30 03:39:37 PM PDT 24	Apr 30 03:39:39 PM PDT 24	147490592 ps
T377	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.775673417	Apr 30 03:38:57 PM PDT 24	Apr 30 03:39:17 PM PDT 24	2885356027 ps
T1299	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.1218498614	Apr 30 03:38:10 PM PDT 24	Apr 30 03:38:11 PM PDT 24	78959644 ps
T1300	/workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2767180844	Apr 30 03:39:19 PM PDT 24	Apr 30 03:39:22 PM PDT 24	621629424 ps
T1301	/workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3390961764	Apr 30 03:39:40 PM PDT 24	Apr 30 03:39:42 PM PDT 24	145079339 ps
T1302	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3415646504	Apr 30 03:39:07 PM PDT 24	Apr 30 03:39:16 PM PDT 24	643218500 ps
T1303	/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2428784830	Apr 30 03:38:55 PM PDT 24	Apr 30 03:38:59 PM PDT 24	185987323 ps
T1304	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2227714196	Apr 30 03:38:05 PM PDT 24	Apr 30 03:38:09 PM PDT 24	429732761 ps
T1305	/workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3955878390	Apr 30 03:38:56 PM PDT 24	Apr 30 03:38:58 PM PDT 24	691363388 ps
T1306	/workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.588901754	Apr 30 03:38:30 PM PDT 24	Apr 30 03:38:32 PM PDT 24	256347921 ps
T1307	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.388305787	Apr 30 03:37:03 PM PDT 24	Apr 30 03:37:07 PM PDT 24	162085301 ps
T1308	/workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1893716577	Apr 30 03:39:26 PM PDT 24	Apr 30 03:39:28 PM PDT 24	150265222 ps
T1309	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1716601950	Apr 30 03:37:32 PM PDT 24	Apr 30 03:37:34 PM PDT 24	74931314 ps
T1310	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3617308995	Apr 30 03:39:03 PM PDT 24	Apr 30 03:39:09 PM PDT 24	1688490673 ps
T1311	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2072321134	Apr 30 03:39:00 PM PDT 24	Apr 30 03:39:02 PM PDT 24	46333866 ps
T1312	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.1989676274	Apr 30 03:37:59 PM PDT 24	Apr 30 03:38:01 PM PDT 24	69240868 ps
T1313	/workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.566276522	Apr 30 03:39:36 PM PDT 24	Apr 30 03:39:39 PM PDT 24	39226524 ps
T1314	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3920678661	Apr 30 03:38:08 PM PDT 24	Apr 30 03:38:10 PM PDT 24	181120004 ps
T378	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.186021881	Apr 30 03:39:17 PM PDT 24	Apr 30 03:39:39 PM PDT 24	10357894038 ps
T1315	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.765107061	Apr 30 03:39:07 PM PDT 24	Apr 30 03:39:12 PM PDT 24	169803379 ps
T379	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.179639433	Apr 30 03:38:43 PM PDT 24	Apr 30 03:38:54 PM PDT 24	703854427 ps
T1316	/workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.3349129363	Apr 30 03:39:41 PM PDT 24	Apr 30 03:39:43 PM PDT 24	555767169 ps
T1317	/workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.821602225	Apr 30 03:39:45 PM PDT 24	Apr 30 03:39:47 PM PDT 24	38893287 ps
T315	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.705117465	Apr 30 03:39:25 PM PDT 24	Apr 30 03:39:27 PM PDT 24	73270859 ps
T1318	/workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1338271094	Apr 30 03:38:18 PM PDT 24	Apr 30 03:38:20 PM PDT 24	174595934 ps
T1319	/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.918970956	Apr 30 03:39:14 PM PDT 24	Apr 30 03:39:18 PM PDT 24	985032349 ps
T1320	/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2717264991	Apr 30 03:37:08 PM PDT 24	Apr 30 03:37:10 PM PDT 24	579047710 ps
T1321	/workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.3710528097	Apr 30 03:39:43 PM PDT 24	Apr 30 03:39:45 PM PDT 24	40876159 ps
T1322	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1892423411	Apr 30 03:38:08 PM PDT 24	Apr 30 03:38:13 PM PDT 24	121705172 ps
T1323	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3071748320	Apr 30 03:39:19 PM PDT 24	Apr 30 03:39:21 PM PDT 24	106615040 ps
T316	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3523042968	Apr 30 03:38:13 PM PDT 24	Apr 30 03:38:17 PM PDT 24	1571651078 ps
T1324	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1870672276	Apr 30 03:38:57 PM PDT 24	Apr 30 03:39:01 PM PDT 24	147174399 ps
T1325	/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.3786389848	Apr 30 03:39:18 PM PDT 24	Apr 30 03:39:20 PM PDT 24	144496169 ps
T1326	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.68186228	Apr 30 03:39:14 PM PDT 24	Apr 30 03:39:18 PM PDT 24	1729880271 ps
T1327	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.519736846	Apr 30 03:38:24 PM PDT 24	Apr 30 03:38:28 PM PDT 24	1569946429 ps
T1328	/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.1583830858	Apr 30 03:39:07 PM PDT 24	Apr 30 03:39:09 PM PDT 24	55105857 ps
T1329	/workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3850481071	Apr 30 03:39:51 PM PDT 24	Apr 30 03:39:52 PM PDT 24	37780007 ps

Test location	/workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.3308342823
Short name	T6
Test name
Test status
Simulation time	190192529299 ps
CPU time	1146.23 seconds
Started	Apr 30 03:46:06 PM PDT 24
Finished	Apr 30 04:05:13 PM PDT 24
Peak memory	346332 kb
Host	smart-53f1706a-e5d6-498c-a644-52738cb2eea4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308342823 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.3308342823
Directory	/workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.otp_ctrl_stress_all.1348393467
Short name	T133
Test name
Test status
Simulation time	9244649535 ps
CPU time	197.89 seconds
Started	Apr 30 03:42:32 PM PDT 24
Finished	Apr 30 03:45:51 PM PDT 24
Peak memory	265408 kb
Host	smart-222de569-127d-4759-a4f1-7489b2cb3be8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348393467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all .1348393467
Directory	/workspace/19.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.otp_ctrl_check_fail.458941258
Short name	T34
Test name
Test status
Simulation time	286071453 ps
CPU time	8.75 seconds
Started	Apr 30 03:42:40 PM PDT 24
Finished	Apr 30 03:42:49 PM PDT 24
Peak memory	241792 kb
Host	smart-ae0fdf45-b9fd-4c52-99bb-6c25e621f50b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=458941258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.458941258
Directory	/workspace/21.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/13.otp_ctrl_stress_all.1436449298
Short name	T66
Test name
Test status
Simulation time	9287054402 ps
CPU time	104.99 seconds
Started	Apr 30 03:41:46 PM PDT 24
Finished	Apr 30 03:43:32 PM PDT 24
Peak memory	245744 kb
Host	smart-22d9ec67-996c-4799-b181-0b44b1efae81
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436449298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all .1436449298
Directory	/workspace/13.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.otp_ctrl_stress_all.2984585772
Short name	T130
Test name
Test status
Simulation time	26215889290 ps
CPU time	343.04 seconds
Started	Apr 30 03:42:25 PM PDT 24
Finished	Apr 30 03:48:08 PM PDT 24
Peak memory	307888 kb
Host	smart-182834c7-bdc3-4f3c-9617-6a2202433ba8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984585772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all .2984585772
Directory	/workspace/17.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.otp_ctrl_sec_cm.4006475143
Short name	T20
Test name
Test status
Simulation time	37123122755 ps
CPU time	189.38 seconds
Started	Apr 30 03:40:26 PM PDT 24
Finished	Apr 30 03:43:36 PM PDT 24
Peak memory	266524 kb
Host	smart-1e47d0d3-9087-4575-9994-cb70f9d1fbc6
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006475143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.4006475143
Directory	/workspace/4.otp_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/171.otp_ctrl_init_fail.541767897
Short name	T81
Test name
Test status
Simulation time	152105122 ps
CPU time	4.36 seconds
Started	Apr 30 03:48:08 PM PDT 24
Finished	Apr 30 03:48:13 PM PDT 24
Peak memory	241440 kb
Host	smart-958de219-42af-477a-b818-b74530ec1ace
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=541767897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.541767897
Directory	/workspace/171.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/81.otp_ctrl_init_fail.3478702098
Short name	T10
Test name
Test status
Simulation time	209641383 ps
CPU time	4.69 seconds
Started	Apr 30 03:46:33 PM PDT 24
Finished	Apr 30 03:46:38 PM PDT 24
Peak memory	241796 kb
Host	smart-fe68e850-8796-4816-b671-ef33ac713c88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3478702098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.3478702098
Directory	/workspace/81.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/6.otp_ctrl_macro_errs.45606982
Short name	T147
Test name
Test status
Simulation time	1199705542 ps
CPU time	29.1 seconds
Started	Apr 30 03:40:49 PM PDT 24
Finished	Apr 30 03:41:18 PM PDT 24
Peak memory	247692 kb
Host	smart-a0ef5f3d-58e8-485b-999c-14b9ee3981fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45606982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.45606982
Directory	/workspace/6.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/12.otp_ctrl_stress_all.1564309062
Short name	T235
Test name
Test status
Simulation time	25837804966 ps
CPU time	253.48 seconds
Started	Apr 30 03:41:41 PM PDT 24
Finished	Apr 30 03:45:55 PM PDT 24
Peak memory	259020 kb
Host	smart-12578d79-2ad4-480f-9dc8-86755ae70ace
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564309062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all .1564309062
Directory	/workspace/12.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/150.otp_ctrl_init_fail.3350792302
Short name	T69
Test name
Test status
Simulation time	1846378129 ps
CPU time	4.36 seconds
Started	Apr 30 03:47:52 PM PDT 24
Finished	Apr 30 03:47:57 PM PDT 24
Peak memory	241276 kb
Host	smart-02260e93-0bfb-4695-80b4-71a4885f1727
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350792302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.3350792302
Directory	/workspace/150.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.688730322
Short name	T374
Test name
Test status
Simulation time	2584892479 ps
CPU time	20.71 seconds
Started	Apr 30 03:37:03 PM PDT 24
Finished	Apr 30 03:37:24 PM PDT 24
Peak memory	244804 kb
Host	smart-6fa7a93e-6ea6-4d78-b876-435672f244c6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688730322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_int g_err.688730322
Directory	/workspace/0.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/38.otp_ctrl_init_fail.1951513687
Short name	T142
Test name
Test status
Simulation time	586494903 ps
CPU time	4.5 seconds
Started	Apr 30 03:44:35 PM PDT 24
Finished	Apr 30 03:44:40 PM PDT 24
Peak memory	241340 kb
Host	smart-86bee247-2f39-4135-85ac-423ebaf0dcd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1951513687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.1951513687
Directory	/workspace/38.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/2.otp_ctrl_check_fail.160527018
Short name	T46
Test name
Test status
Simulation time	2293323723 ps
CPU time	39.8 seconds
Started	Apr 30 03:40:10 PM PDT 24
Finished	Apr 30 03:40:50 PM PDT 24
Peak memory	246512 kb
Host	smart-d13b7461-cb5d-4ee1-afe2-fefcbe09e183
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=160527018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.160527018
Directory	/workspace/2.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.2493250263
Short name	T17
Test name
Test status
Simulation time	330014871907 ps
CPU time	1235.6 seconds
Started	Apr 30 03:40:13 PM PDT 24
Finished	Apr 30 04:00:49 PM PDT 24
Peak memory	276496 kb
Host	smart-0ff4e6d3-3a27-4d5d-b071-2a4796ba0afd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493250263 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.2493250263
Directory	/workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/101.otp_ctrl_init_fail.2493680553
Short name	T23
Test name
Test status
Simulation time	629615121 ps
CPU time	4.75 seconds
Started	Apr 30 03:46:59 PM PDT 24
Finished	Apr 30 03:47:05 PM PDT 24
Peak memory	241764 kb
Host	smart-d05c8f7e-ba33-4ed0-a2c5-c0001f665098
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2493680553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.2493680553
Directory	/workspace/101.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/78.otp_ctrl_init_fail.113710064
Short name	T72
Test name
Test status
Simulation time	130084109 ps
CPU time	3.66 seconds
Started	Apr 30 03:46:38 PM PDT 24
Finished	Apr 30 03:46:43 PM PDT 24
Peak memory	241464 kb
Host	smart-67382c32-da39-4c47-b9ef-5d4e8e0fd84f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113710064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.113710064
Directory	/workspace/78.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/124.otp_ctrl_init_fail.3189620942
Short name	T479
Test name
Test status
Simulation time	613665369 ps
CPU time	4.44 seconds
Started	Apr 30 03:47:22 PM PDT 24
Finished	Apr 30 03:47:27 PM PDT 24
Peak memory	241440 kb
Host	smart-f1cebe76-3f3d-462e-bb43-44468e3c1f1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3189620942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.3189620942
Directory	/workspace/124.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.1792432203
Short name	T11
Test name
Test status
Simulation time	418252347267 ps
CPU time	1977.05 seconds
Started	Apr 30 03:41:53 PM PDT 24
Finished	Apr 30 04:14:51 PM PDT 24
Peak memory	368264 kb
Host	smart-6d1048ac-9e16-41ee-953f-e389cf635bf2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792432203 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.1792432203
Directory	/workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3168442380
Short name	T308
Test name
Test status
Simulation time	145482022 ps
CPU time	1.49 seconds
Started	Apr 30 03:37:42 PM PDT 24
Finished	Apr 30 03:37:44 PM PDT 24
Peak memory	239756 kb
Host	smart-9f5e401f-c503-45ee-846b-1c3fef87c210
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168442380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.3168442380
Directory	/workspace/1.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/default/9.otp_ctrl_stress_all.527898675
Short name	T65
Test name
Test status
Simulation time	6793240174 ps
CPU time	65.18 seconds
Started	Apr 30 03:41:19 PM PDT 24
Finished	Apr 30 03:42:25 PM PDT 24
Peak memory	243308 kb
Host	smart-4fc371fd-17d3-41b7-abcf-5da16e838d46
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527898675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.527898675
Directory	/workspace/9.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/140.otp_ctrl_init_fail.1229121456
Short name	T61
Test name
Test status
Simulation time	175057587 ps
CPU time	4.81 seconds
Started	Apr 30 03:47:44 PM PDT 24
Finished	Apr 30 03:47:49 PM PDT 24
Peak memory	241320 kb
Host	smart-d7e8873d-8cc3-4d8a-85df-7702a63e9b51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1229121456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.1229121456
Directory	/workspace/140.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/27.otp_ctrl_check_fail.434406858
Short name	T27
Test name
Test status
Simulation time	2955265912 ps
CPU time	16.4 seconds
Started	Apr 30 03:43:22 PM PDT 24
Finished	Apr 30 03:43:39 PM PDT 24
Peak memory	248176 kb
Host	smart-f59792b4-7d61-4b0d-a027-570acafdca20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=434406858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.434406858
Directory	/workspace/27.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/280.otp_ctrl_init_fail.3048712128
Short name	T68
Test name
Test status
Simulation time	1929233362 ps
CPU time	6.35 seconds
Started	Apr 30 03:49:01 PM PDT 24
Finished	Apr 30 03:49:09 PM PDT 24
Peak memory	241404 kb
Host	smart-2adeab8b-3edf-42d7-8b46-9d02244097b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048712128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.3048712128
Directory	/workspace/280.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/17.otp_ctrl_init_fail.314922990
Short name	T53
Test name
Test status
Simulation time	495756924 ps
CPU time	4.21 seconds
Started	Apr 30 03:42:24 PM PDT 24
Finished	Apr 30 03:42:29 PM PDT 24
Peak memory	241480 kb
Host	smart-5c61379a-a0c1-4ee8-8b28-13d3b81e0380
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=314922990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.314922990
Directory	/workspace/17.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/121.otp_ctrl_init_fail.1271807565
Short name	T2
Test name
Test status
Simulation time	388097323 ps
CPU time	5.02 seconds
Started	Apr 30 03:47:23 PM PDT 24
Finished	Apr 30 03:47:28 PM PDT 24
Peak memory	241360 kb
Host	smart-39ae1ec2-8e3a-4ad3-b4ea-831978a787a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1271807565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.1271807565
Directory	/workspace/121.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/178.otp_ctrl_init_fail.3227628311
Short name	T41
Test name
Test status
Simulation time	191471039 ps
CPU time	4.54 seconds
Started	Apr 30 03:48:17 PM PDT 24
Finished	Apr 30 03:48:22 PM PDT 24
Peak memory	241404 kb
Host	smart-94939f27-37b0-4c37-a7a8-f3ac1f78fc4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3227628311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.3227628311
Directory	/workspace/178.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.4048037638
Short name	T225
Test name
Test status
Simulation time	334526682 ps
CPU time	8.05 seconds
Started	Apr 30 03:46:34 PM PDT 24
Finished	Apr 30 03:46:43 PM PDT 24
Peak memory	241324 kb
Host	smart-3286dccb-7a3c-4dc8-8d9a-b60a8b3821fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4048037638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.4048037638
Directory	/workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/16.otp_ctrl_stress_all.140503263
Short name	T183
Test name
Test status
Simulation time	49561425585 ps
CPU time	151.89 seconds
Started	Apr 30 03:42:12 PM PDT 24
Finished	Apr 30 03:44:45 PM PDT 24
Peak memory	248584 kb
Host	smart-9a658375-cd38-4480-8fcd-f98dab77776c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140503263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all. 140503263
Directory	/workspace/16.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.3075383079
Short name	T290
Test name
Test status
Simulation time	958611803273 ps
CPU time	2413.75 seconds
Started	Apr 30 03:46:34 PM PDT 24
Finished	Apr 30 04:26:49 PM PDT 24
Peak memory	375076 kb
Host	smart-5518e0d7-190c-497a-a1a8-218457a1db5d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075383079 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.3075383079
Directory	/workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.otp_ctrl_check_fail.1437478241
Short name	T57
Test name
Test status
Simulation time	2048808557 ps
CPU time	29.8 seconds
Started	Apr 30 03:45:08 PM PDT 24
Finished	Apr 30 03:45:39 PM PDT 24
Peak memory	242856 kb
Host	smart-437d839b-2e64-4baa-86c6-9f60d5db4143
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1437478241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.1437478241
Directory	/workspace/42.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/16.otp_ctrl_alert_test.2117751493
Short name	T180
Test name
Test status
Simulation time	175162198 ps
CPU time	1.71 seconds
Started	Apr 30 03:42:19 PM PDT 24
Finished	Apr 30 03:42:21 PM PDT 24
Peak memory	240216 kb
Host	smart-eae5e230-fe74-4cad-8dc3-46e1bb1328e0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117751493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.2117751493
Directory	/workspace/16.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.otp_ctrl_macro_errs.865244511
Short name	T64
Test name
Test status
Simulation time	3853432095 ps
CPU time	21.11 seconds
Started	Apr 30 03:43:30 PM PDT 24
Finished	Apr 30 03:43:52 PM PDT 24
Peak memory	248076 kb
Host	smart-8d477e69-d4c6-4447-8ee8-2034a501f3ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865244511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.865244511
Directory	/workspace/28.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.2428754137
Short name	T14
Test name
Test status
Simulation time	20675862165 ps
CPU time	545 seconds
Started	Apr 30 03:46:47 PM PDT 24
Finished	Apr 30 03:55:53 PM PDT 24
Peak memory	313796 kb
Host	smart-0851aba4-5cf7-41fa-bd82-15d055d31340
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428754137 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.2428754137
Directory	/workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.otp_ctrl_regwen.1741318628
Short name	T383
Test name
Test status
Simulation time	288950536 ps
CPU time	9.29 seconds
Started	Apr 30 03:43:47 PM PDT 24
Finished	Apr 30 03:43:57 PM PDT 24
Peak memory	241224 kb
Host	smart-9339c56c-ec64-487c-9e3c-58baac583283
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1741318628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.1741318628
Directory	/workspace/30.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/44.otp_ctrl_stress_all.1775143787
Short name	T283
Test name
Test status
Simulation time	5443752943 ps
CPU time	123.97 seconds
Started	Apr 30 03:45:28 PM PDT 24
Finished	Apr 30 03:47:33 PM PDT 24
Peak memory	256280 kb
Host	smart-312ab474-a76c-40d6-a3b7-e70359c00bf2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775143787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all .1775143787
Directory	/workspace/44.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.otp_ctrl_stress_all.1227406293
Short name	T255
Test name
Test status
Simulation time	20123642248 ps
CPU time	202.55 seconds
Started	Apr 30 03:40:09 PM PDT 24
Finished	Apr 30 03:43:32 PM PDT 24
Peak memory	278088 kb
Host	smart-dd687d03-187b-4fb8-ba6b-48be373c388d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227406293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all. 1227406293
Directory	/workspace/1.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/92.otp_ctrl_init_fail.4014552894
Short name	T25
Test name
Test status
Simulation time	732941767 ps
CPU time	4.94 seconds
Started	Apr 30 03:46:50 PM PDT 24
Finished	Apr 30 03:46:56 PM PDT 24
Peak memory	241408 kb
Host	smart-c9edea8f-53cb-4856-817f-55c965dea997
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4014552894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.4014552894
Directory	/workspace/92.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.1934784920
Short name	T352
Test name
Test status
Simulation time	2042430878927 ps
CPU time	4286.66 seconds
Started	Apr 30 03:45:57 PM PDT 24
Finished	Apr 30 04:57:25 PM PDT 24
Peak memory	578284 kb
Host	smart-e76d37b4-f80b-4831-a77c-d569523a6e63
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934784920 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.1934784920
Directory	/workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/123.otp_ctrl_init_fail.3939483423
Short name	T173
Test name
Test status
Simulation time	114012400 ps
CPU time	4.26 seconds
Started	Apr 30 03:47:21 PM PDT 24
Finished	Apr 30 03:47:26 PM PDT 24
Peak memory	241468 kb
Host	smart-b2b4a2f4-f1ba-47d0-ab9c-93016c848a2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3939483423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.3939483423
Directory	/workspace/123.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.1942589959
Short name	T109
Test name
Test status
Simulation time	3605984142 ps
CPU time	15.29 seconds
Started	Apr 30 03:48:21 PM PDT 24
Finished	Apr 30 03:48:37 PM PDT 24
Peak memory	241576 kb
Host	smart-c7fb58d3-f0bc-41a5-8b76-cc0b3cc4de1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942589959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.1942589959
Directory	/workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/158.otp_ctrl_init_fail.2274149988
Short name	T123
Test name
Test status
Simulation time	247681723 ps
CPU time	3.68 seconds
Started	Apr 30 03:47:58 PM PDT 24
Finished	Apr 30 03:48:02 PM PDT 24
Peak memory	241664 kb
Host	smart-cb9466e5-b41b-455f-9799-f2b095d296c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2274149988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.2274149988
Directory	/workspace/158.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/254.otp_ctrl_init_fail.2063134165
Short name	T58
Test name
Test status
Simulation time	2396766117 ps
CPU time	4.94 seconds
Started	Apr 30 03:48:52 PM PDT 24
Finished	Apr 30 03:48:57 PM PDT 24
Peak memory	241560 kb
Host	smart-e22f9559-49fc-4b8b-92d2-4436eb4e3b24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2063134165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.2063134165
Directory	/workspace/254.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/35.otp_ctrl_stress_all.95457883
Short name	T1162
Test name
Test status
Simulation time	18632683775 ps
CPU time	230.44 seconds
Started	Apr 30 03:44:20 PM PDT 24
Finished	Apr 30 03:48:11 PM PDT 24
Peak memory	256344 kb
Host	smart-5c73eccc-ca0e-42dd-9c27-c02b9867e72e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95457883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.95457883
Directory	/workspace/35.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.otp_ctrl_stress_all.2707846382
Short name	T184
Test name
Test status
Simulation time	3721617161 ps
CPU time	115.32 seconds
Started	Apr 30 03:40:54 PM PDT 24
Finished	Apr 30 03:42:50 PM PDT 24
Peak memory	245128 kb
Host	smart-b29988d2-0b7c-4d9c-b895-559bac31fe91
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707846382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all. 2707846382
Directory	/workspace/6.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1757398313
Short name	T372
Test name
Test status
Simulation time	1524836019 ps
CPU time	19.63 seconds
Started	Apr 30 03:39:04 PM PDT 24
Finished	Apr 30 03:39:24 PM PDT 24
Peak memory	244204 kb
Host	smart-0f206128-72b7-41ae-96fd-687c7bd7dde6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757398313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i ntg_err.1757398313
Directory	/workspace/13.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/8.otp_ctrl_stress_all.2990894090
Short name	T297
Test name
Test status
Simulation time	7655075437 ps
CPU time	180.41 seconds
Started	Apr 30 03:41:10 PM PDT 24
Finished	Apr 30 03:44:11 PM PDT 24
Peak memory	256296 kb
Host	smart-faa34b1d-8aee-4487-a6fa-a0c660f37938
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990894090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all. 2990894090
Directory	/workspace/8.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.1592592696
Short name	T42
Test name
Test status
Simulation time	267920378 ps
CPU time	6.35 seconds
Started	Apr 30 03:41:52 PM PDT 24
Finished	Apr 30 03:41:59 PM PDT 24
Peak memory	241340 kb
Host	smart-eccaa86d-d03d-4895-bcd5-7b1cc30cfbd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592592696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.1592592696
Directory	/workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/31.otp_ctrl_regwen.2795347924
Short name	T384
Test name
Test status
Simulation time	354189764 ps
CPU time	12.94 seconds
Started	Apr 30 03:43:52 PM PDT 24
Finished	Apr 30 03:44:06 PM PDT 24
Peak memory	241552 kb
Host	smart-6ba4cf0c-f0f9-4c34-9830-1067e1cd8c20
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2795347924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2795347924
Directory	/workspace/31.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.4033199129
Short name	T211
Test name
Test status
Simulation time	142533446 ps
CPU time	5.92 seconds
Started	Apr 30 03:41:22 PM PDT 24
Finished	Apr 30 03:41:28 PM PDT 24
Peak memory	241416 kb
Host	smart-f732949a-79cc-4a31-b53d-89c06b15831d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033199129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.4033199129
Directory	/workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.3116903431
Short name	T222
Test name
Test status
Simulation time	1197893984 ps
CPU time	15.81 seconds
Started	Apr 30 03:47:07 PM PDT 24
Finished	Apr 30 03:47:24 PM PDT 24
Peak memory	241800 kb
Host	smart-00842def-4b50-4fad-8139-dbbf6b01fb3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3116903431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3116903431
Directory	/workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/14.otp_ctrl_stress_all.2212624259
Short name	T75
Test name
Test status
Simulation time	14261514953 ps
CPU time	154.53 seconds
Started	Apr 30 03:41:53 PM PDT 24
Finished	Apr 30 03:44:28 PM PDT 24
Peak memory	248124 kb
Host	smart-7e1fc284-83ab-4439-9534-2fe7fe0eb290
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212624259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all .2212624259
Directory	/workspace/14.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.2899010582
Short name	T79
Test name
Test status
Simulation time	785535998 ps
CPU time	21.51 seconds
Started	Apr 30 03:48:04 PM PDT 24
Finished	Apr 30 03:48:26 PM PDT 24
Peak memory	241212 kb
Host	smart-968cf712-7b87-40aa-a870-3ead39548d8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899010582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.2899010582
Directory	/workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.2887741589
Short name	T210
Test name
Test status
Simulation time	53231602723 ps
CPU time	636.1 seconds
Started	Apr 30 03:43:13 PM PDT 24
Finished	Apr 30 03:53:50 PM PDT 24
Peak memory	344076 kb
Host	smart-0886e32e-c587-47a7-b74c-0108f793fc64
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887741589 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.2887741589
Directory	/workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.872476399
Short name	T217
Test name
Test status
Simulation time	1821945752 ps
CPU time	21.49 seconds
Started	Apr 30 03:44:15 PM PDT 24
Finished	Apr 30 03:44:37 PM PDT 24
Peak memory	241840 kb
Host	smart-c303491d-bb66-4cbc-8f3e-35febc2c22f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872476399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.872476399
Directory	/workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.2722699221
Short name	T121
Test name
Test status
Simulation time	360576857 ps
CPU time	16.52 seconds
Started	Apr 30 03:44:19 PM PDT 24
Finished	Apr 30 03:44:36 PM PDT 24
Peak memory	241380 kb
Host	smart-271f431c-fa7f-404b-8832-9afbd2e7d4e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2722699221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.2722699221
Directory	/workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/37.otp_ctrl_check_fail.1815259882
Short name	T77
Test name
Test status
Simulation time	2577994758 ps
CPU time	23.78 seconds
Started	Apr 30 03:44:31 PM PDT 24
Finished	Apr 30 03:44:55 PM PDT 24
Peak memory	241844 kb
Host	smart-5ce72683-c990-46b8-9d5e-f59daa2ec602
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815259882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.1815259882
Directory	/workspace/37.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.2108638304
Short name	T228
Test name
Test status
Simulation time	348699857 ps
CPU time	9.84 seconds
Started	Apr 30 03:46:17 PM PDT 24
Finished	Apr 30 03:46:27 PM PDT 24
Peak memory	241836 kb
Host	smart-59e157cd-bda3-4af4-934c-fac5810f1926
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2108638304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.2108638304
Directory	/workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.3833057215
Short name	T218
Test name
Test status
Simulation time	2191897621 ps
CPU time	6.68 seconds
Started	Apr 30 03:46:21 PM PDT 24
Finished	Apr 30 03:46:28 PM PDT 24
Peak memory	241308 kb
Host	smart-0112a1f1-844b-452b-80de-6966c83a64e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833057215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3833057215
Directory	/workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.3826606020
Short name	T649
Test name
Test status
Simulation time	41549875892 ps
CPU time	533.11 seconds
Started	Apr 30 03:45:55 PM PDT 24
Finished	Apr 30 03:54:48 PM PDT 24
Peak memory	256396 kb
Host	smart-ef67064a-8e81-4e80-8cf5-1b80a2c357fa
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826606020 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.3826606020
Directory	/workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.4049798869
Short name	T271
Test name
Test status
Simulation time	1264889506 ps
CPU time	10.91 seconds
Started	Apr 30 03:39:25 PM PDT 24
Finished	Apr 30 03:39:36 PM PDT 24
Peak memory	243996 kb
Host	smart-6131010b-010e-4f45-ab6b-c7effcdcb1aa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049798869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i ntg_err.4049798869
Directory	/workspace/17.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/10.otp_ctrl_check_fail.3469674736
Short name	T51
Test name
Test status
Simulation time	1548112441 ps
CPU time	11.15 seconds
Started	Apr 30 03:41:25 PM PDT 24
Finished	Apr 30 03:41:36 PM PDT 24
Peak memory	247940 kb
Host	smart-9a4f89de-5438-43a7-ad07-10d9a982b6de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3469674736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.3469674736
Directory	/workspace/10.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/33.otp_ctrl_stress_all.2593897937
Short name	T206
Test name
Test status
Simulation time	26591649455 ps
CPU time	260.51 seconds
Started	Apr 30 03:44:08 PM PDT 24
Finished	Apr 30 03:48:29 PM PDT 24
Peak memory	272772 kb
Host	smart-e3777232-37cf-4b03-b770-537013e21051
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593897937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all .2593897937
Directory	/workspace/33.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.otp_ctrl_init_fail.2806716640
Short name	T138
Test name
Test status
Simulation time	371820811 ps
CPU time	3.17 seconds
Started	Apr 30 03:45:10 PM PDT 24
Finished	Apr 30 03:45:15 PM PDT 24
Peak memory	241280 kb
Host	smart-616d8e5f-23ed-46a2-8943-b4e92d720974
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2806716640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.2806716640
Directory	/workspace/44.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/46.otp_ctrl_stress_all.3995261350
Short name	T481
Test name
Test status
Simulation time	58865337096 ps
CPU time	178.08 seconds
Started	Apr 30 03:45:31 PM PDT 24
Finished	Apr 30 03:48:29 PM PDT 24
Peak memory	248152 kb
Host	smart-555d6f69-8708-48b2-98c3-23be24682c43
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995261350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all .3995261350
Directory	/workspace/46.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.otp_ctrl_check_fail.1354939508
Short name	T119
Test name
Test status
Simulation time	411643090 ps
CPU time	9.5 seconds
Started	Apr 30 03:41:36 PM PDT 24
Finished	Apr 30 03:41:46 PM PDT 24
Peak memory	243328 kb
Host	smart-6cf2db8d-9ab1-400f-8a5d-e5aca3650659
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1354939508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.1354939508
Directory	/workspace/12.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/104.otp_ctrl_init_fail.1300061038
Short name	T70
Test name
Test status
Simulation time	602257396 ps
CPU time	5.11 seconds
Started	Apr 30 03:47:06 PM PDT 24
Finished	Apr 30 03:47:11 PM PDT 24
Peak memory	241492 kb
Host	smart-24b3bae8-9c7f-4539-b14e-69e44026a8a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1300061038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.1300061038
Directory	/workspace/104.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/136.otp_ctrl_init_fail.3114802500
Short name	T473
Test name
Test status
Simulation time	2017651813 ps
CPU time	5.25 seconds
Started	Apr 30 03:47:34 PM PDT 24
Finished	Apr 30 03:47:40 PM PDT 24
Peak memory	241788 kb
Host	smart-275df72e-329d-4904-a14d-9cb0fe8118df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3114802500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.3114802500
Directory	/workspace/136.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.3525446804
Short name	T250
Test name
Test status
Simulation time	49712267202 ps
CPU time	1254.73 seconds
Started	Apr 30 03:46:54 PM PDT 24
Finished	Apr 30 04:07:49 PM PDT 24
Peak memory	264624 kb
Host	smart-89029c64-b096-4b16-818a-8bde5087659c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525446804 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.3525446804
Directory	/workspace/99.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3650241662
Short name	T375
Test name
Test status
Simulation time	2467735557 ps
CPU time	12.78 seconds
Started	Apr 30 03:37:28 PM PDT 24
Finished	Apr 30 03:37:41 PM PDT 24
Peak memory	244404 kb
Host	smart-311a45ba-7f4e-4326-ad5b-fda03f9c34b6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650241662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in tg_err.3650241662
Directory	/workspace/1.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/10.otp_ctrl_macro_errs.1239183674
Short name	T556
Test name
Test status
Simulation time	1325394197 ps
CPU time	17.02 seconds
Started	Apr 30 03:41:26 PM PDT 24
Finished	Apr 30 03:41:43 PM PDT 24
Peak memory	245288 kb
Host	smart-5e9c65f7-812e-4b86-bbae-bdee390c8e69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1239183674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.1239183674
Directory	/workspace/10.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/12.otp_ctrl_regwen.58286619
Short name	T50
Test name
Test status
Simulation time	3948761173 ps
CPU time	9.53 seconds
Started	Apr 30 03:41:41 PM PDT 24
Finished	Apr 30 03:41:51 PM PDT 24
Peak memory	241788 kb
Host	smart-3ce4af2f-5171-4f46-bd3b-93fe74ffd677
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=58286619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.58286619
Directory	/workspace/12.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.3335663780
Short name	T301
Test name
Test status
Simulation time	47414336275 ps
CPU time	934.73 seconds
Started	Apr 30 03:42:16 PM PDT 24
Finished	Apr 30 03:57:52 PM PDT 24
Peak memory	261580 kb
Host	smart-d91d2cef-c5c1-41a3-89b1-a989a272126b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335663780 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.3335663780
Directory	/workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.otp_ctrl_regwen.2540991566
Short name	T323
Test name
Test status
Simulation time	614214452 ps
CPU time	11.85 seconds
Started	Apr 30 03:44:52 PM PDT 24
Finished	Apr 30 03:45:05 PM PDT 24
Peak memory	241588 kb
Host	smart-71be56b7-ba6e-40a6-b469-56f62a1a0450
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2540991566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.2540991566
Directory	/workspace/40.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/56.otp_ctrl_init_fail.4253206764
Short name	T264
Test name
Test status
Simulation time	2179291426 ps
CPU time	5.33 seconds
Started	Apr 30 03:46:01 PM PDT 24
Finished	Apr 30 03:46:06 PM PDT 24
Peak memory	241352 kb
Host	smart-7e03c647-b03d-4177-872c-5d9cc9166ef0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4253206764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.4253206764
Directory	/workspace/56.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/10.otp_ctrl_stress_all.2469737735
Short name	T98
Test name
Test status
Simulation time	7358557434 ps
CPU time	135.63 seconds
Started	Apr 30 03:41:24 PM PDT 24
Finished	Apr 30 03:43:40 PM PDT 24
Peak memory	247644 kb
Host	smart-5ac16b04-506c-4b2b-8908-a3ef38d97d06
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469737735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all .2469737735
Directory	/workspace/10.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.otp_ctrl_stress_all.2909783154
Short name	T362
Test name
Test status
Simulation time	5393311579 ps
CPU time	51.43 seconds
Started	Apr 30 03:43:13 PM PDT 24
Finished	Apr 30 03:44:05 PM PDT 24
Peak memory	243076 kb
Host	smart-6c29aa5a-53ae-4682-a998-1a417b541745
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909783154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all .2909783154
Directory	/workspace/25.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/71.otp_ctrl_init_fail.467556163
Short name	T92
Test name
Test status
Simulation time	2127960312 ps
CPU time	4.37 seconds
Started	Apr 30 03:46:19 PM PDT 24
Finished	Apr 30 03:46:24 PM PDT 24
Peak memory	241432 kb
Host	smart-182dfd48-bb98-48aa-a941-f20e63bc6569
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=467556163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.467556163
Directory	/workspace/71.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1017296287
Short name	T275
Test name
Test status
Simulation time	1841634233 ps
CPU time	6.87 seconds
Started	Apr 30 03:37:17 PM PDT 24
Finished	Apr 30 03:37:24 PM PDT 24
Peak memory	239012 kb
Host	smart-debd61ef-c6d3-4567-b635-7d10e4de2c11
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017296287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia sing.1017296287
Directory	/workspace/0.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.1843062839
Short name	T258
Test name
Test status
Simulation time	98187688411 ps
CPU time	1101.93 seconds
Started	Apr 30 03:39:51 PM PDT 24
Finished	Apr 30 03:58:14 PM PDT 24
Peak memory	263948 kb
Host	smart-8a965632-92b1-456a-8fd5-f1a0779cbbde
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843062839 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.1843062839
Directory	/workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.otp_ctrl_test_access.3792536435
Short name	T156
Test name
Test status
Simulation time	7493642139 ps
CPU time	34.92 seconds
Started	Apr 30 03:42:48 PM PDT 24
Finished	Apr 30 03:43:24 PM PDT 24
Peak memory	241716 kb
Host	smart-a5ebc731-2c1e-4e93-90a7-1ba235464785
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3792536435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.3792536435
Directory	/workspace/22.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.4024944922
Short name	T361
Test name
Test status
Simulation time	64323945800 ps
CPU time	624.25 seconds
Started	Apr 30 03:41:27 PM PDT 24
Finished	Apr 30 03:51:51 PM PDT 24
Peak memory	273364 kb
Host	smart-573faedb-b858-41bb-8af5-d85b350c2839
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024944922 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.4024944922
Directory	/workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.otp_ctrl_parallel_lc_req.141297865
Short name	T510
Test name
Test status
Simulation time	721852230 ps
CPU time	22.24 seconds
Started	Apr 30 03:42:13 PM PDT 24
Finished	Apr 30 03:42:36 PM PDT 24
Peak memory	241356 kb
Host	smart-8e7776f7-d785-4d0e-9f9e-0feb781870b3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=141297865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.141297865
Directory	/workspace/17.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/181.otp_ctrl_init_fail.2745009636
Short name	T88
Test name
Test status
Simulation time	2209299483 ps
CPU time	4.67 seconds
Started	Apr 30 03:48:14 PM PDT 24
Finished	Apr 30 03:48:20 PM PDT 24
Peak memory	241740 kb
Host	smart-ab4ee6ca-9c66-4f6b-a62d-84135ac3cfd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2745009636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.2745009636
Directory	/workspace/181.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/248.otp_ctrl_init_fail.4114559291
Short name	T86
Test name
Test status
Simulation time	106089745 ps
CPU time	3.25 seconds
Started	Apr 30 03:48:54 PM PDT 24
Finished	Apr 30 03:48:58 PM PDT 24
Peak memory	241332 kb
Host	smart-40bb018d-1439-4d62-bad8-75755066f156
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4114559291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.4114559291
Directory	/workspace/248.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/15.otp_ctrl_parallel_lc_req.4173079810
Short name	T104
Test name
Test status
Simulation time	3186900834 ps
CPU time	26.15 seconds
Started	Apr 30 03:41:56 PM PDT 24
Finished	Apr 30 03:42:22 PM PDT 24
Peak memory	241416 kb
Host	smart-e3ae21aa-02b1-466c-955c-ce3dabebd482
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4173079810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.4173079810
Directory	/workspace/15.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/220.otp_ctrl_init_fail.4086682518
Short name	T943
Test name
Test status
Simulation time	1524653516 ps
CPU time	3.5 seconds
Started	Apr 30 03:48:40 PM PDT 24
Finished	Apr 30 03:48:44 PM PDT 24
Peak memory	241728 kb
Host	smart-b89dec64-1a58-4f97-9e8c-db569490f14e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4086682518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.4086682518
Directory	/workspace/220.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/262.otp_ctrl_init_fail.593102558
Short name	T801
Test name
Test status
Simulation time	304128038 ps
CPU time	4.39 seconds
Started	Apr 30 03:49:04 PM PDT 24
Finished	Apr 30 03:49:09 PM PDT 24
Peak memory	241288 kb
Host	smart-65b52144-83f6-4423-8b38-d8c449cb6801
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=593102558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.593102558
Directory	/workspace/262.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/1.otp_ctrl_init_fail.2930083905
Short name	T43
Test name
Test status
Simulation time	2369536167 ps
CPU time	7.11 seconds
Started	Apr 30 03:39:57 PM PDT 24
Finished	Apr 30 03:40:04 PM PDT 24
Peak memory	241816 kb
Host	smart-968a508c-51a7-4370-9024-5872d2da7811
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2930083905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.2930083905
Directory	/workspace/1.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1395055865
Short name	T1210
Test name
Test status
Simulation time	142309458 ps
CPU time	6.09 seconds
Started	Apr 30 03:37:17 PM PDT 24
Finished	Apr 30 03:37:23 PM PDT 24
Peak memory	230792 kb
Host	smart-f1c1fbed-4604-4cff-ae05-9cde05c49c25
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395055865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_ bash.1395055865
Directory	/workspace/0.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2243909932
Short name	T1268
Test name
Test status
Simulation time	1460555386 ps
CPU time	4.56 seconds
Started	Apr 30 03:37:09 PM PDT 24
Finished	Apr 30 03:37:13 PM PDT 24
Peak memory	239072 kb
Host	smart-7729b338-bca6-4b39-abdd-82d66d157880
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243909932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r eset.2243909932
Directory	/workspace/0.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3587902892
Short name	T273
Test name
Test status
Simulation time	262758983 ps
CPU time	2.29 seconds
Started	Apr 30 03:37:24 PM PDT 24
Finished	Apr 30 03:37:26 PM PDT 24
Peak memory	245536 kb
Host	smart-96d962c9-6a17-4856-bcf7-97eb2ee906ee
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587902892 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.3587902892
Directory	/workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.684181843
Short name	T274
Test name
Test status
Simulation time	82563741 ps
CPU time	1.67 seconds
Started	Apr 30 03:37:13 PM PDT 24
Finished	Apr 30 03:37:15 PM PDT 24
Peak memory	240736 kb
Host	smart-adffc452-e289-471b-92a7-e8e5e254c869
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684181843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.684181843
Directory	/workspace/0.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2717264991
Short name	T1320
Test name
Test status
Simulation time	579047710 ps
CPU time	1.68 seconds
Started	Apr 30 03:37:08 PM PDT 24
Finished	Apr 30 03:37:10 PM PDT 24
Peak memory	231052 kb
Host	smart-54bd346d-c0a5-4e96-9752-355bd1419fff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717264991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2717264991
Directory	/workspace/0.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.4015832490
Short name	T1224
Test name
Test status
Simulation time	69152005 ps
CPU time	1.47 seconds
Started	Apr 30 03:37:07 PM PDT 24
Finished	Apr 30 03:37:09 PM PDT 24
Peak memory	229616 kb
Host	smart-3cb7743c-9b95-4d01-898f-29a4eb7ad5ac
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015832490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr l_mem_partial_access.4015832490
Directory	/workspace/0.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3079199883
Short name	T1263
Test name
Test status
Simulation time	517494701 ps
CPU time	1.36 seconds
Started	Apr 30 03:37:07 PM PDT 24
Finished	Apr 30 03:37:09 PM PDT 24
Peak memory	230860 kb
Host	smart-b5104528-9e36-40d4-961f-eb8774a4b7c6
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079199883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk .3079199883
Directory	/workspace/0.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.2062931005
Short name	T347
Test name
Test status
Simulation time	99256831 ps
CPU time	1.84 seconds
Started	Apr 30 03:37:17 PM PDT 24
Finished	Apr 30 03:37:20 PM PDT 24
Peak memory	238048 kb
Host	smart-75028edc-d4b1-42c2-a5bc-3df02e4fb5ec
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062931005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c trl_same_csr_outstanding.2062931005
Directory	/workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.388305787
Short name	T1307
Test name
Test status
Simulation time	162085301 ps
CPU time	3.62 seconds
Started	Apr 30 03:37:03 PM PDT 24
Finished	Apr 30 03:37:07 PM PDT 24
Peak memory	247196 kb
Host	smart-fb056ca9-617c-4a80-9f71-302d03c0d25c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388305787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.388305787
Directory	/workspace/0.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2928875817
Short name	T314
Test name
Test status
Simulation time	148017139 ps
CPU time	4.7 seconds
Started	Apr 30 03:37:46 PM PDT 24
Finished	Apr 30 03:37:51 PM PDT 24
Peak memory	239084 kb
Host	smart-c0f9d22b-c285-4f25-9adb-79a022aed9c7
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928875817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia sing.2928875817
Directory	/workspace/1.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.668287942
Short name	T1269
Test name
Test status
Simulation time	121934129 ps
CPU time	3.84 seconds
Started	Apr 30 03:37:44 PM PDT 24
Finished	Apr 30 03:37:49 PM PDT 24
Peak memory	238068 kb
Host	smart-052a009a-9ea8-4956-b430-4508ffb8cbc6
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668287942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_b ash.668287942
Directory	/workspace/1.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.4083357227
Short name	T341
Test name
Test status
Simulation time	221322492 ps
CPU time	2.68 seconds
Started	Apr 30 03:37:40 PM PDT 24
Finished	Apr 30 03:37:43 PM PDT 24
Peak memory	239036 kb
Host	smart-5e3e33c7-bc2b-4cd0-9874-344e3679e314
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083357227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r eset.4083357227
Directory	/workspace/1.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1266903439
Short name	T1270
Test name
Test status
Simulation time	1629888691 ps
CPU time	3.53 seconds
Started	Apr 30 03:37:44 PM PDT 24
Finished	Apr 30 03:37:48 PM PDT 24
Peak memory	245096 kb
Host	smart-2ff14ad1-2471-407a-8873-160631d5c699
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266903439 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.1266903439
Directory	/workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3590387063
Short name	T1219
Test name
Test status
Simulation time	54186680 ps
CPU time	1.43 seconds
Started	Apr 30 03:37:33 PM PDT 24
Finished	Apr 30 03:37:35 PM PDT 24
Peak memory	229892 kb
Host	smart-ce3c149b-943a-4e70-926b-43eb74d78e2a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590387063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3590387063
Directory	/workspace/1.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3774556198
Short name	T1221
Test name
Test status
Simulation time	38984300 ps
CPU time	1.3 seconds
Started	Apr 30 03:37:38 PM PDT 24
Finished	Apr 30 03:37:40 PM PDT 24
Peak memory	229388 kb
Host	smart-3e1b69d3-ee44-4357-a56c-4241a1ca3a98
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774556198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr l_mem_partial_access.3774556198
Directory	/workspace/1.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1716601950
Short name	T1309
Test name
Test status
Simulation time	74931314 ps
CPU time	1.4 seconds
Started	Apr 30 03:37:32 PM PDT 24
Finished	Apr 30 03:37:34 PM PDT 24
Peak memory	229416 kb
Host	smart-a7ce59af-4aed-42dd-8890-487de42349a3
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716601950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk .1716601950
Directory	/workspace/1.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2426929156
Short name	T343
Test name
Test status
Simulation time	1093590432 ps
CPU time	2.53 seconds
Started	Apr 30 03:37:44 PM PDT 24
Finished	Apr 30 03:37:47 PM PDT 24
Peak memory	238068 kb
Host	smart-990975c9-e119-49b9-9a78-762509ef53ee
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426929156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c trl_same_csr_outstanding.2426929156
Directory	/workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1590561164
Short name	T1197
Test name
Test status
Simulation time	66784885 ps
CPU time	4.09 seconds
Started	Apr 30 03:37:28 PM PDT 24
Finished	Apr 30 03:37:32 PM PDT 24
Peak memory	246664 kb
Host	smart-e2b62d9b-5e83-427b-9e8e-a9bdb46004ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590561164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.1590561164
Directory	/workspace/1.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1870672276
Short name	T1324
Test name
Test status
Simulation time	147174399 ps
CPU time	3 seconds
Started	Apr 30 03:38:57 PM PDT 24
Finished	Apr 30 03:39:01 PM PDT 24
Peak memory	247288 kb
Host	smart-10d6c26e-1a79-46e5-b6e1-47dbb8c689b5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870672276 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.1870672276
Directory	/workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3974118548
Short name	T1243
Test name
Test status
Simulation time	46353814 ps
CPU time	1.59 seconds
Started	Apr 30 03:38:55 PM PDT 24
Finished	Apr 30 03:38:57 PM PDT 24
Peak memory	239108 kb
Host	smart-c474c4ef-eb65-4975-aa92-74bc50902403
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974118548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3974118548
Directory	/workspace/10.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3371786309
Short name	T1209
Test name
Test status
Simulation time	128345711 ps
CPU time	1.46 seconds
Started	Apr 30 03:38:42 PM PDT 24
Finished	Apr 30 03:38:44 PM PDT 24
Peak memory	230824 kb
Host	smart-f08cb8ef-e369-4daa-8c45-0d4beeef375a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371786309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.3371786309
Directory	/workspace/10.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.587890993
Short name	T1256
Test name
Test status
Simulation time	322974084 ps
CPU time	2.93 seconds
Started	Apr 30 03:38:56 PM PDT 24
Finished	Apr 30 03:39:00 PM PDT 24
Peak memory	238924 kb
Host	smart-2581a5c8-c7a1-41a3-a8b3-35c9be3a5cbd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587890993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_c trl_same_csr_outstanding.587890993
Directory	/workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.1736004914
Short name	T1202
Test name
Test status
Simulation time	998933599 ps
CPU time	4.44 seconds
Started	Apr 30 03:38:42 PM PDT 24
Finished	Apr 30 03:38:47 PM PDT 24
Peak memory	239152 kb
Host	smart-37cf1163-6688-4b24-aa26-10a5d1c2b4a6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736004914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.1736004914
Directory	/workspace/10.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.179639433
Short name	T379
Test name
Test status
Simulation time	703854427 ps
CPU time	10.89 seconds
Started	Apr 30 03:38:43 PM PDT 24
Finished	Apr 30 03:38:54 PM PDT 24
Peak memory	239052 kb
Host	smart-8d71a813-dbb5-4629-940e-6ca2e14aeed5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179639433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_in tg_err.179639433
Directory	/workspace/10.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.2861779825
Short name	T1277
Test name
Test status
Simulation time	184056193 ps
CPU time	2.92 seconds
Started	Apr 30 03:38:57 PM PDT 24
Finished	Apr 30 03:39:00 PM PDT 24
Peak memory	247388 kb
Host	smart-bbb41f5c-c47b-4b97-a658-d7da889f12f4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861779825 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.2861779825
Directory	/workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2517133291
Short name	T311
Test name
Test status
Simulation time	46128016 ps
CPU time	1.53 seconds
Started	Apr 30 03:38:56 PM PDT 24
Finished	Apr 30 03:38:58 PM PDT 24
Peak memory	239052 kb
Host	smart-7a08f1a8-3b90-426c-bd65-965b7fa946ee
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517133291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.2517133291
Directory	/workspace/11.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.4067706156
Short name	T1227
Test name
Test status
Simulation time	40570753 ps
CPU time	1.4 seconds
Started	Apr 30 03:38:56 PM PDT 24
Finished	Apr 30 03:38:58 PM PDT 24
Peak memory	229496 kb
Host	smart-9025465c-ca65-4bb9-b56c-f319a04f95aa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067706156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.4067706156
Directory	/workspace/11.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1106004940
Short name	T1235
Test name
Test status
Simulation time	202648150 ps
CPU time	2.54 seconds
Started	Apr 30 03:38:57 PM PDT 24
Finished	Apr 30 03:39:01 PM PDT 24
Peak memory	238168 kb
Host	smart-d643ba20-9614-46c3-a4cf-aaf4aaa3973d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106004940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ ctrl_same_csr_outstanding.1106004940
Directory	/workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.445729431
Short name	T1288
Test name
Test status
Simulation time	128883866 ps
CPU time	4.48 seconds
Started	Apr 30 03:38:56 PM PDT 24
Finished	Apr 30 03:39:01 PM PDT 24
Peak memory	246816 kb
Host	smart-1baa8498-92b0-4255-87fe-2a53f73fcbfa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445729431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.445729431
Directory	/workspace/11.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1793953549
Short name	T272
Test name
Test status
Simulation time	686948006 ps
CPU time	11.45 seconds
Started	Apr 30 03:38:57 PM PDT 24
Finished	Apr 30 03:39:09 PM PDT 24
Peak memory	239028 kb
Host	smart-c70dd834-0bc8-4d7e-ad8f-cbf57de1ffad
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793953549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i ntg_err.1793953549
Directory	/workspace/11.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1912314006
Short name	T1222
Test name
Test status
Simulation time	1626072649 ps
CPU time	3.66 seconds
Started	Apr 30 03:39:02 PM PDT 24
Finished	Apr 30 03:39:06 PM PDT 24
Peak memory	247308 kb
Host	smart-70675591-0298-4951-81f3-074ebac8d83b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912314006 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.1912314006
Directory	/workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.4010836681
Short name	T313
Test name
Test status
Simulation time	43108260 ps
CPU time	1.49 seconds
Started	Apr 30 03:38:58 PM PDT 24
Finished	Apr 30 03:39:00 PM PDT 24
Peak memory	239976 kb
Host	smart-fe65e4b6-3dec-49eb-a8ff-50599f868e8d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010836681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.4010836681
Directory	/workspace/12.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2974980384
Short name	T1231
Test name
Test status
Simulation time	69130185 ps
CPU time	1.47 seconds
Started	Apr 30 03:38:57 PM PDT 24
Finished	Apr 30 03:38:59 PM PDT 24
Peak memory	230856 kb
Host	smart-188f31d0-ff2a-4d2b-b67c-a0cb535b5dd7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974980384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.2974980384
Directory	/workspace/12.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2428784830
Short name	T1303
Test name
Test status
Simulation time	185987323 ps
CPU time	3.13 seconds
Started	Apr 30 03:38:55 PM PDT 24
Finished	Apr 30 03:38:59 PM PDT 24
Peak memory	238064 kb
Host	smart-b4c0c7e2-e42b-4613-95b3-896c69d9a18f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428784830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ ctrl_same_csr_outstanding.2428784830
Directory	/workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2198013005
Short name	T1275
Test name
Test status
Simulation time	1595065551 ps
CPU time	3.82 seconds
Started	Apr 30 03:38:57 PM PDT 24
Finished	Apr 30 03:39:01 PM PDT 24
Peak memory	246636 kb
Host	smart-82f80bc3-9172-4f28-a833-6a3229b11516
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198013005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.2198013005
Directory	/workspace/12.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.775673417
Short name	T377
Test name
Test status
Simulation time	2885356027 ps
CPU time	19.29 seconds
Started	Apr 30 03:38:57 PM PDT 24
Finished	Apr 30 03:39:17 PM PDT 24
Peak memory	245892 kb
Host	smart-97029ab5-1ae0-4632-b5f9-67b8ca135258
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775673417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_in tg_err.775673417
Directory	/workspace/12.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.426814070
Short name	T1242
Test name
Test status
Simulation time	100567330 ps
CPU time	3.18 seconds
Started	Apr 30 03:39:00 PM PDT 24
Finished	Apr 30 03:39:04 PM PDT 24
Peak memory	247284 kb
Host	smart-9b7c531d-b08b-4fc0-8543-d1d7870459ec
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426814070 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.426814070
Directory	/workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.311332569
Short name	T342
Test name
Test status
Simulation time	75755568 ps
CPU time	1.63 seconds
Started	Apr 30 03:39:04 PM PDT 24
Finished	Apr 30 03:39:06 PM PDT 24
Peak memory	239008 kb
Host	smart-b65f0617-5859-4540-9e21-a6db20e36270
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311332569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.311332569
Directory	/workspace/13.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2881528042
Short name	T1249
Test name
Test status
Simulation time	40119452 ps
CPU time	1.45 seconds
Started	Apr 30 03:38:59 PM PDT 24
Finished	Apr 30 03:39:02 PM PDT 24
Peak memory	230868 kb
Host	smart-0d5f3066-8497-47fc-8430-40d7fb92c6f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881528042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.2881528042
Directory	/workspace/13.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.4199808326
Short name	T1228
Test name
Test status
Simulation time	1189553148 ps
CPU time	2.46 seconds
Started	Apr 30 03:39:04 PM PDT 24
Finished	Apr 30 03:39:07 PM PDT 24
Peak memory	237984 kb
Host	smart-bd598747-9e36-4544-b8a7-eff1793b45b9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199808326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ ctrl_same_csr_outstanding.4199808326
Directory	/workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3617308995
Short name	T1310
Test name
Test status
Simulation time	1688490673 ps
CPU time	5.3 seconds
Started	Apr 30 03:39:03 PM PDT 24
Finished	Apr 30 03:39:09 PM PDT 24
Peak memory	246888 kb
Host	smart-312f1229-de1d-4bcb-b7dc-0e211c046740
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617308995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3617308995
Directory	/workspace/13.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.493498780
Short name	T1267
Test name
Test status
Simulation time	133326931 ps
CPU time	2.1 seconds
Started	Apr 30 03:39:06 PM PDT 24
Finished	Apr 30 03:39:08 PM PDT 24
Peak memory	244920 kb
Host	smart-659c1d26-c170-446e-9600-2ea811fdbce9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493498780 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.493498780
Directory	/workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2072321134
Short name	T1311
Test name
Test status
Simulation time	46333866 ps
CPU time	1.73 seconds
Started	Apr 30 03:39:00 PM PDT 24
Finished	Apr 30 03:39:02 PM PDT 24
Peak memory	238944 kb
Host	smart-1675d208-d396-47ab-8adb-5a3fad98075b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072321134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.2072321134
Directory	/workspace/14.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2375819213
Short name	T1245
Test name
Test status
Simulation time	162027491 ps
CPU time	1.49 seconds
Started	Apr 30 03:39:01 PM PDT 24
Finished	Apr 30 03:39:03 PM PDT 24
Peak memory	230832 kb
Host	smart-2f4594dc-08eb-4513-bf2e-b0d7e62999c9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375819213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.2375819213
Directory	/workspace/14.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.180208846
Short name	T1261
Test name
Test status
Simulation time	81049028 ps
CPU time	2.36 seconds
Started	Apr 30 03:39:04 PM PDT 24
Finished	Apr 30 03:39:06 PM PDT 24
Peak memory	237976 kb
Host	smart-58110f06-d4c6-4d25-8ac8-c2d5552da3ad
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180208846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_c trl_same_csr_outstanding.180208846
Directory	/workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2977026139
Short name	T1205
Test name
Test status
Simulation time	347440204 ps
CPU time	6.37 seconds
Started	Apr 30 03:39:02 PM PDT 24
Finished	Apr 30 03:39:09 PM PDT 24
Peak memory	239036 kb
Host	smart-bf94c630-fcd8-48f8-96af-7abbe8effaec
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977026139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.2977026139
Directory	/workspace/14.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3243920712
Short name	T278
Test name
Test status
Simulation time	18921858930 ps
CPU time	39.62 seconds
Started	Apr 30 03:39:03 PM PDT 24
Finished	Apr 30 03:39:43 PM PDT 24
Peak memory	244928 kb
Host	smart-e83ed609-c998-429a-aba8-dbc2a7eb8b36
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243920712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i ntg_err.3243920712
Directory	/workspace/14.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.181916719
Short name	T1282
Test name
Test status
Simulation time	425837704 ps
CPU time	3.36 seconds
Started	Apr 30 03:39:09 PM PDT 24
Finished	Apr 30 03:39:12 PM PDT 24
Peak memory	247312 kb
Host	smart-3f43eee6-ac67-4bf3-9cc0-3d8358824362
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181916719 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.181916719
Directory	/workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1489038497
Short name	T1296
Test name
Test status
Simulation time	37756865 ps
CPU time	1.45 seconds
Started	Apr 30 03:39:07 PM PDT 24
Finished	Apr 30 03:39:09 PM PDT 24
Peak memory	240000 kb
Host	smart-d3c10a7e-ecb6-459b-87f4-04e64098ae4a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489038497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.1489038497
Directory	/workspace/15.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.1583830858
Short name	T1328
Test name
Test status
Simulation time	55105857 ps
CPU time	1.38 seconds
Started	Apr 30 03:39:07 PM PDT 24
Finished	Apr 30 03:39:09 PM PDT 24
Peak memory	230912 kb
Host	smart-9a3bc499-9d6f-462d-8e0a-88e85bc52bbd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583830858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.1583830858
Directory	/workspace/15.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.4020595652
Short name	T346
Test name
Test status
Simulation time	967381969 ps
CPU time	2.8 seconds
Started	Apr 30 03:39:08 PM PDT 24
Finished	Apr 30 03:39:11 PM PDT 24
Peak memory	239068 kb
Host	smart-0ea21020-867b-4f19-a4f3-44e7341aed7e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020595652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ ctrl_same_csr_outstanding.4020595652
Directory	/workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.765107061
Short name	T1315
Test name
Test status
Simulation time	169803379 ps
CPU time	5.52 seconds
Started	Apr 30 03:39:07 PM PDT 24
Finished	Apr 30 03:39:12 PM PDT 24
Peak memory	246740 kb
Host	smart-2819bda8-50c3-44de-8d63-23a1e37bc4db
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765107061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.765107061
Directory	/workspace/15.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3415646504
Short name	T1302
Test name
Test status
Simulation time	643218500 ps
CPU time	9.11 seconds
Started	Apr 30 03:39:07 PM PDT 24
Finished	Apr 30 03:39:16 PM PDT 24
Peak memory	238900 kb
Host	smart-53858af6-6483-4b74-a7df-c3502baa9ad4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415646504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i ntg_err.3415646504
Directory	/workspace/15.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2270461832
Short name	T398
Test name
Test status
Simulation time	193435247 ps
CPU time	3.53 seconds
Started	Apr 30 03:39:14 PM PDT 24
Finished	Apr 30 03:39:18 PM PDT 24
Peak memory	246576 kb
Host	smart-b9e25999-9f07-4948-b7a0-d131c06544ec
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270461832 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.2270461832
Directory	/workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.4294881637
Short name	T312
Test name
Test status
Simulation time	683155145 ps
CPU time	1.69 seconds
Started	Apr 30 03:39:14 PM PDT 24
Finished	Apr 30 03:39:16 PM PDT 24
Peak memory	240408 kb
Host	smart-8685b7a6-c7b1-42f5-a941-78011666cac7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294881637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.4294881637
Directory	/workspace/16.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.303114976
Short name	T1206
Test name
Test status
Simulation time	37425078 ps
CPU time	1.51 seconds
Started	Apr 30 03:39:14 PM PDT 24
Finished	Apr 30 03:39:16 PM PDT 24
Peak memory	229884 kb
Host	smart-03b9f8fa-315d-4e4a-b665-335edb0e5f48
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303114976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.303114976
Directory	/workspace/16.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.918970956
Short name	T1319
Test name
Test status
Simulation time	985032349 ps
CPU time	2.81 seconds
Started	Apr 30 03:39:14 PM PDT 24
Finished	Apr 30 03:39:18 PM PDT 24
Peak memory	238948 kb
Host	smart-e72dee82-d88c-4a68-87b1-03446bece22d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918970956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_c trl_same_csr_outstanding.918970956
Directory	/workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.246876409
Short name	T1241
Test name
Test status
Simulation time	151241422 ps
CPU time	5.05 seconds
Started	Apr 30 03:39:07 PM PDT 24
Finished	Apr 30 03:39:13 PM PDT 24
Peak memory	246756 kb
Host	smart-2a0b2706-7f9c-49c8-86c0-0e15efe63032
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246876409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.246876409
Directory	/workspace/16.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1120509682
Short name	T376
Test name
Test status
Simulation time	725590859 ps
CPU time	9.92 seconds
Started	Apr 30 03:39:14 PM PDT 24
Finished	Apr 30 03:39:24 PM PDT 24
Peak memory	243336 kb
Host	smart-107b98ef-a7dd-4bfd-aa1d-64c9b0f772a0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120509682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i ntg_err.1120509682
Directory	/workspace/16.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3071748320
Short name	T1323
Test name
Test status
Simulation time	106615040 ps
CPU time	2.06 seconds
Started	Apr 30 03:39:19 PM PDT 24
Finished	Apr 30 03:39:21 PM PDT 24
Peak memory	244828 kb
Host	smart-841ad2d9-95e3-46a4-9425-d4d97f07926d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071748320 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.3071748320
Directory	/workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.705117465
Short name	T315
Test name
Test status
Simulation time	73270859 ps
CPU time	1.65 seconds
Started	Apr 30 03:39:25 PM PDT 24
Finished	Apr 30 03:39:27 PM PDT 24
Peak memory	238960 kb
Host	smart-b480eeba-e6bd-4520-831a-0d1a01ceff16
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705117465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.705117465
Directory	/workspace/17.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.3786389848
Short name	T1325
Test name
Test status
Simulation time	144496169 ps
CPU time	1.28 seconds
Started	Apr 30 03:39:18 PM PDT 24
Finished	Apr 30 03:39:20 PM PDT 24
Peak memory	230884 kb
Host	smart-01cd959a-eb6b-4c16-ae96-b6617492d307
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786389848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.3786389848
Directory	/workspace/17.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.25822927
Short name	T1229
Test name
Test status
Simulation time	232851389 ps
CPU time	2.52 seconds
Started	Apr 30 03:39:22 PM PDT 24
Finished	Apr 30 03:39:25 PM PDT 24
Peak memory	239128 kb
Host	smart-84ba604b-171f-411e-bc00-7fef00c35681
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25822927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ct rl_same_csr_outstanding.25822927
Directory	/workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.68186228
Short name	T1326
Test name
Test status
Simulation time	1729880271 ps
CPU time	4.27 seconds
Started	Apr 30 03:39:14 PM PDT 24
Finished	Apr 30 03:39:18 PM PDT 24
Peak memory	245632 kb
Host	smart-862742f6-8c3d-4d90-93d6-642a28bd5f07
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68186228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.68186228
Directory	/workspace/17.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2126665707
Short name	T1290
Test name
Test status
Simulation time	204720434 ps
CPU time	3.09 seconds
Started	Apr 30 03:39:23 PM PDT 24
Finished	Apr 30 03:39:26 PM PDT 24
Peak memory	247272 kb
Host	smart-6a531362-d9f6-4d9f-bf48-0b6170db86ed
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126665707 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.2126665707
Directory	/workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.1390117473
Short name	T1276
Test name
Test status
Simulation time	588361253 ps
CPU time	2.47 seconds
Started	Apr 30 03:39:24 PM PDT 24
Finished	Apr 30 03:39:27 PM PDT 24
Peak memory	240040 kb
Host	smart-5548bf24-c329-4d79-a804-d91c22409ccc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390117473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.1390117473
Directory	/workspace/18.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2767180844
Short name	T1300
Test name
Test status
Simulation time	621629424 ps
CPU time	2.32 seconds
Started	Apr 30 03:39:19 PM PDT 24
Finished	Apr 30 03:39:22 PM PDT 24
Peak memory	229584 kb
Host	smart-d4567639-d564-4a6c-b8d6-abeda1b7056d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767180844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.2767180844
Directory	/workspace/18.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3796512661
Short name	T345
Test name
Test status
Simulation time	140542673 ps
CPU time	2.29 seconds
Started	Apr 30 03:39:24 PM PDT 24
Finished	Apr 30 03:39:27 PM PDT 24
Peak memory	238084 kb
Host	smart-98dd2c55-ed56-4620-ac74-46d855f89bf9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796512661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ ctrl_same_csr_outstanding.3796512661
Directory	/workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3910967692
Short name	T1215
Test name
Test status
Simulation time	90226159 ps
CPU time	3.84 seconds
Started	Apr 30 03:39:18 PM PDT 24
Finished	Apr 30 03:39:22 PM PDT 24
Peak memory	246872 kb
Host	smart-6435e367-f124-416c-b8d7-3653bd05abd1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910967692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.3910967692
Directory	/workspace/18.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.186021881
Short name	T378
Test name
Test status
Simulation time	10357894038 ps
CPU time	21.85 seconds
Started	Apr 30 03:39:17 PM PDT 24
Finished	Apr 30 03:39:39 PM PDT 24
Peak memory	244716 kb
Host	smart-27883f60-d3e1-4676-a8b9-d5a26d4e6d05
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186021881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_in tg_err.186021881
Directory	/workspace/18.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2651758586
Short name	T1239
Test name
Test status
Simulation time	135615422 ps
CPU time	2.07 seconds
Started	Apr 30 03:39:31 PM PDT 24
Finished	Apr 30 03:39:33 PM PDT 24
Peak memory	244076 kb
Host	smart-aa914c8e-482a-4825-91f2-aeb228e245ab
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651758586 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.2651758586
Directory	/workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1485287056
Short name	T1246
Test name
Test status
Simulation time	75944666 ps
CPU time	1.55 seconds
Started	Apr 30 03:39:33 PM PDT 24
Finished	Apr 30 03:39:35 PM PDT 24
Peak memory	240284 kb
Host	smart-7eef236f-66aa-422e-b8f6-62357e958c7a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485287056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.1485287056
Directory	/workspace/19.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1893716577
Short name	T1308
Test name
Test status
Simulation time	150265222 ps
CPU time	1.56 seconds
Started	Apr 30 03:39:26 PM PDT 24
Finished	Apr 30 03:39:28 PM PDT 24
Peak memory	229536 kb
Host	smart-e880faa0-0882-4037-b263-f41b5b215bb6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893716577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1893716577
Directory	/workspace/19.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1515792213
Short name	T276
Test name
Test status
Simulation time	70071758 ps
CPU time	2.28 seconds
Started	Apr 30 03:39:32 PM PDT 24
Finished	Apr 30 03:39:35 PM PDT 24
Peak memory	239180 kb
Host	smart-e9e1053f-0dc6-46ae-beaa-56c44df91d1f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515792213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ ctrl_same_csr_outstanding.1515792213
Directory	/workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1982790888
Short name	T1213
Test name
Test status
Simulation time	366095456 ps
CPU time	6.99 seconds
Started	Apr 30 03:39:27 PM PDT 24
Finished	Apr 30 03:39:35 PM PDT 24
Peak memory	239128 kb
Host	smart-8bd6f0ef-a56d-4712-b543-f14df078e795
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982790888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.1982790888
Directory	/workspace/19.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2095748526
Short name	T380
Test name
Test status
Simulation time	3461405801 ps
CPU time	21.65 seconds
Started	Apr 30 03:39:27 PM PDT 24
Finished	Apr 30 03:39:49 PM PDT 24
Peak memory	244172 kb
Host	smart-3660f9dd-8542-4aea-b19b-0ff5c689522f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095748526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i ntg_err.2095748526
Directory	/workspace/19.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.2774518185
Short name	T310
Test name
Test status
Simulation time	208751380 ps
CPU time	3.8 seconds
Started	Apr 30 03:37:49 PM PDT 24
Finished	Apr 30 03:37:53 PM PDT 24
Peak memory	238908 kb
Host	smart-2b216f9a-e398-4ad2-923c-6935dbf595ec
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774518185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia sing.2774518185
Directory	/workspace/2.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.734780946
Short name	T1257
Test name
Test status
Simulation time	152545728 ps
CPU time	3.87 seconds
Started	Apr 30 03:37:50 PM PDT 24
Finished	Apr 30 03:37:54 PM PDT 24
Peak memory	238332 kb
Host	smart-00fc690b-9b05-4b42-b9be-0b5bbcf9067e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734780946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_b ash.734780946
Directory	/workspace/2.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.3021173736
Short name	T307
Test name
Test status
Simulation time	105319976 ps
CPU time	2.35 seconds
Started	Apr 30 03:37:49 PM PDT 24
Finished	Apr 30 03:37:52 PM PDT 24
Peak memory	239872 kb
Host	smart-0484acc5-a865-42e0-9f8e-8b2148893a9f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021173736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r eset.3021173736
Directory	/workspace/2.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1180882681
Short name	T1254
Test name
Test status
Simulation time	207537239 ps
CPU time	4.03 seconds
Started	Apr 30 03:37:54 PM PDT 24
Finished	Apr 30 03:37:59 PM PDT 24
Peak memory	247296 kb
Host	smart-89628caf-8cb3-4c9c-90b9-4a34a929c176
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180882681 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.1180882681
Directory	/workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.4005576444
Short name	T344
Test name
Test status
Simulation time	160956812 ps
CPU time	1.89 seconds
Started	Apr 30 03:37:47 PM PDT 24
Finished	Apr 30 03:37:50 PM PDT 24
Peak memory	240280 kb
Host	smart-6b8e11d8-c9ae-47fd-8d5a-8af903103ac2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005576444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.4005576444
Directory	/workspace/2.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.4208094372
Short name	T1240
Test name
Test status
Simulation time	40729401 ps
CPU time	1.51 seconds
Started	Apr 30 03:37:45 PM PDT 24
Finished	Apr 30 03:37:47 PM PDT 24
Peak memory	230884 kb
Host	smart-47e7008e-6279-4b4b-bed8-45d2b15ca385
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208094372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.4208094372
Directory	/workspace/2.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2899274751
Short name	T1289
Test name
Test status
Simulation time	40598838 ps
CPU time	1.3 seconds
Started	Apr 30 03:37:53 PM PDT 24
Finished	Apr 30 03:37:54 PM PDT 24
Peak memory	229256 kb
Host	smart-f733f714-93b0-4fc1-9943-6b06e8530676
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899274751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr l_mem_partial_access.2899274751
Directory	/workspace/2.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2421291351
Short name	T1218
Test name
Test status
Simulation time	521311425 ps
CPU time	1.87 seconds
Started	Apr 30 03:37:44 PM PDT 24
Finished	Apr 30 03:37:46 PM PDT 24
Peak memory	230568 kb
Host	smart-3d476c6f-ad31-4e78-9abc-a4b2fb98e200
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421291351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk .2421291351
Directory	/workspace/2.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2237344946
Short name	T1234
Test name
Test status
Simulation time	262557616 ps
CPU time	2.34 seconds
Started	Apr 30 03:37:54 PM PDT 24
Finished	Apr 30 03:37:56 PM PDT 24
Peak memory	238996 kb
Host	smart-daf75ace-b17d-4cf7-b5e3-793520c1c557
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237344946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c trl_same_csr_outstanding.2237344946
Directory	/workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3715788898
Short name	T1203
Test name
Test status
Simulation time	79130361 ps
CPU time	4.6 seconds
Started	Apr 30 03:37:42 PM PDT 24
Finished	Apr 30 03:37:48 PM PDT 24
Peak memory	245900 kb
Host	smart-ed7bc752-bece-4277-9cf8-f09c9e1e0fa1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715788898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3715788898
Directory	/workspace/2.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2569101594
Short name	T1251
Test name
Test status
Simulation time	762219295 ps
CPU time	11.94 seconds
Started	Apr 30 03:37:45 PM PDT 24
Finished	Apr 30 03:37:58 PM PDT 24
Peak memory	243096 kb
Host	smart-333b5ddb-8e52-4d6d-a9c1-b220cb33d3c5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569101594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in tg_err.2569101594
Directory	/workspace/2.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.4002176505
Short name	T1272
Test name
Test status
Simulation time	55661119 ps
CPU time	1.45 seconds
Started	Apr 30 03:39:32 PM PDT 24
Finished	Apr 30 03:39:34 PM PDT 24
Peak memory	229640 kb
Host	smart-541c2af0-4c97-4e8a-a912-186e73834b6f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002176505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.4002176505
Directory	/workspace/20.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3416955406
Short name	T1291
Test name
Test status
Simulation time	155556452 ps
CPU time	1.49 seconds
Started	Apr 30 03:39:35 PM PDT 24
Finished	Apr 30 03:39:37 PM PDT 24
Peak memory	230812 kb
Host	smart-4881c5e9-ebb0-470c-8d76-fa8aabe18e63
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416955406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.3416955406
Directory	/workspace/21.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.3616380987
Short name	T1200
Test name
Test status
Simulation time	77494779 ps
CPU time	1.54 seconds
Started	Apr 30 03:39:31 PM PDT 24
Finished	Apr 30 03:39:33 PM PDT 24
Peak memory	229548 kb
Host	smart-88e68d00-a5df-458e-9324-ad1d9795e32d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616380987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.3616380987
Directory	/workspace/22.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3390961764
Short name	T1301
Test name
Test status
Simulation time	145079339 ps
CPU time	1.33 seconds
Started	Apr 30 03:39:40 PM PDT 24
Finished	Apr 30 03:39:42 PM PDT 24
Peak memory	229464 kb
Host	smart-bc8afb9b-7b47-4353-a6db-5ca400bc97f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390961764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3390961764
Directory	/workspace/23.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.608494886
Short name	T1244
Test name
Test status
Simulation time	144963319 ps
CPU time	1.44 seconds
Started	Apr 30 03:39:40 PM PDT 24
Finished	Apr 30 03:39:42 PM PDT 24
Peak memory	229752 kb
Host	smart-7c6d0e71-3ebb-42de-a934-77340a3db094
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608494886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.608494886
Directory	/workspace/24.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.3202586132
Short name	T1248
Test name
Test status
Simulation time	148584563 ps
CPU time	1.53 seconds
Started	Apr 30 03:39:35 PM PDT 24
Finished	Apr 30 03:39:37 PM PDT 24
Peak memory	230812 kb
Host	smart-243a122f-3f47-4993-a0aa-603658d4b065
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202586132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.3202586132
Directory	/workspace/25.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.1698081206
Short name	T1259
Test name
Test status
Simulation time	45132675 ps
CPU time	1.47 seconds
Started	Apr 30 03:39:36 PM PDT 24
Finished	Apr 30 03:39:39 PM PDT 24
Peak memory	230820 kb
Host	smart-1c8f4cab-72b0-4280-8851-e9616a96ce4f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698081206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.1698081206
Directory	/workspace/26.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2710205253
Short name	T1198
Test name
Test status
Simulation time	126178181 ps
CPU time	1.51 seconds
Started	Apr 30 03:39:36 PM PDT 24
Finished	Apr 30 03:39:38 PM PDT 24
Peak memory	229832 kb
Host	smart-467c0986-92a0-414c-bb49-3a2c412cf318
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710205253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.2710205253
Directory	/workspace/27.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.3349129363
Short name	T1316
Test name
Test status
Simulation time	555767169 ps
CPU time	1.69 seconds
Started	Apr 30 03:39:41 PM PDT 24
Finished	Apr 30 03:39:43 PM PDT 24
Peak memory	230920 kb
Host	smart-91a28087-fe15-4609-b021-1964c37ac457
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349129363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.3349129363
Directory	/workspace/28.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.3645464040
Short name	T1238
Test name
Test status
Simulation time	41136145 ps
CPU time	1.35 seconds
Started	Apr 30 03:39:38 PM PDT 24
Finished	Apr 30 03:39:40 PM PDT 24
Peak memory	230900 kb
Host	smart-d61668c5-9566-4ff9-8fb7-748314258709
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645464040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.3645464040
Directory	/workspace/29.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3025329405
Short name	T356
Test name
Test status
Simulation time	74956622 ps
CPU time	4.79 seconds
Started	Apr 30 03:37:58 PM PDT 24
Finished	Apr 30 03:38:03 PM PDT 24
Peak memory	230660 kb
Host	smart-1a7a0a01-08e4-4232-ac01-bcea8e2bdaf4
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025329405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia sing.3025329405
Directory	/workspace/3.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.522332359
Short name	T1279
Test name
Test status
Simulation time	431976048 ps
CPU time	5.45 seconds
Started	Apr 30 03:37:58 PM PDT 24
Finished	Apr 30 03:38:04 PM PDT 24
Peak memory	238940 kb
Host	smart-64e14e69-1d7c-4495-a24e-fe25a84e247a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522332359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_b ash.522332359
Directory	/workspace/3.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.4094111596
Short name	T1207
Test name
Test status
Simulation time	246040089 ps
CPU time	1.93 seconds
Started	Apr 30 03:37:59 PM PDT 24
Finished	Apr 30 03:38:01 PM PDT 24
Peak memory	238012 kb
Host	smart-c27a464c-71a1-4900-9fed-5c13626f25cd
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094111596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r eset.4094111596
Directory	/workspace/3.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2227714196
Short name	T1304
Test name
Test status
Simulation time	429732761 ps
CPU time	3.5 seconds
Started	Apr 30 03:38:05 PM PDT 24
Finished	Apr 30 03:38:09 PM PDT 24
Peak memory	247140 kb
Host	smart-f4f92e9f-5f89-4f3d-af2b-c0be0a4e1b37
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227714196 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.2227714196
Directory	/workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.1847819475
Short name	T1287
Test name
Test status
Simulation time	56629276 ps
CPU time	1.71 seconds
Started	Apr 30 03:37:59 PM PDT 24
Finished	Apr 30 03:38:01 PM PDT 24
Peak memory	239068 kb
Host	smart-6798228e-6d6a-4b9a-a073-951d70ec6a82
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847819475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.1847819475
Directory	/workspace/3.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.3361836957
Short name	T1258
Test name
Test status
Simulation time	535962460 ps
CPU time	1.65 seconds
Started	Apr 30 03:37:59 PM PDT 24
Finished	Apr 30 03:38:01 PM PDT 24
Peak memory	230796 kb
Host	smart-4b487431-3687-45a4-a92e-c38f12820aa2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361836957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.3361836957
Directory	/workspace/3.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1216747777
Short name	T1260
Test name
Test status
Simulation time	77632792 ps
CPU time	1.44 seconds
Started	Apr 30 03:38:02 PM PDT 24
Finished	Apr 30 03:38:03 PM PDT 24
Peak memory	229388 kb
Host	smart-9652744d-433e-486d-a715-6845a2837896
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216747777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr l_mem_partial_access.1216747777
Directory	/workspace/3.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.1989676274
Short name	T1312
Test name
Test status
Simulation time	69240868 ps
CPU time	1.34 seconds
Started	Apr 30 03:37:59 PM PDT 24
Finished	Apr 30 03:38:01 PM PDT 24
Peak memory	230804 kb
Host	smart-3309c32c-602d-4135-8e13-f7e93d672465
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989676274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk .1989676274
Directory	/workspace/3.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1271528238
Short name	T1273
Test name
Test status
Simulation time	45509715 ps
CPU time	1.91 seconds
Started	Apr 30 03:38:02 PM PDT 24
Finished	Apr 30 03:38:04 PM PDT 24
Peak memory	237948 kb
Host	smart-bed0f3cd-8ab8-4939-9b77-fadd9fb32e3a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271528238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c trl_same_csr_outstanding.1271528238
Directory	/workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.2899085797
Short name	T1211
Test name
Test status
Simulation time	109603653 ps
CPU time	3.96 seconds
Started	Apr 30 03:37:57 PM PDT 24
Finished	Apr 30 03:38:01 PM PDT 24
Peak memory	246796 kb
Host	smart-42805ae9-2cc3-4f59-b0b1-e8a712ffb06d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899085797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.2899085797
Directory	/workspace/3.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1704353724
Short name	T373
Test name
Test status
Simulation time	1598434834 ps
CPU time	11.48 seconds
Started	Apr 30 03:38:01 PM PDT 24
Finished	Apr 30 03:38:13 PM PDT 24
Peak memory	243540 kb
Host	smart-cfabd4ab-df58-4911-982e-2fb54aec257a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704353724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in tg_err.1704353724
Directory	/workspace/3.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.3710528097
Short name	T1321
Test name
Test status
Simulation time	40876159 ps
CPU time	1.54 seconds
Started	Apr 30 03:39:43 PM PDT 24
Finished	Apr 30 03:39:45 PM PDT 24
Peak memory	230784 kb
Host	smart-3230e49d-624e-47b4-b12b-0bd6bf166608
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710528097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.3710528097
Directory	/workspace/30.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.1389855238
Short name	T1214
Test name
Test status
Simulation time	69976884 ps
CPU time	1.36 seconds
Started	Apr 30 03:39:37 PM PDT 24
Finished	Apr 30 03:39:39 PM PDT 24
Peak memory	229860 kb
Host	smart-7137ec1e-efac-4ec2-bd7e-554929c27529
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389855238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.1389855238
Directory	/workspace/31.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.796983546
Short name	T1293
Test name
Test status
Simulation time	42541907 ps
CPU time	1.42 seconds
Started	Apr 30 03:39:36 PM PDT 24
Finished	Apr 30 03:39:38 PM PDT 24
Peak memory	229476 kb
Host	smart-969fd984-f8ce-407d-b733-050f131b5ace
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796983546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.796983546
Directory	/workspace/32.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.683372841
Short name	T1250
Test name
Test status
Simulation time	76597267 ps
CPU time	1.5 seconds
Started	Apr 30 03:39:36 PM PDT 24
Finished	Apr 30 03:39:38 PM PDT 24
Peak memory	229924 kb
Host	smart-e89a4ed1-0ad0-4508-98bd-b7a6eb7dc6c0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683372841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.683372841
Directory	/workspace/33.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.983491340
Short name	T1236
Test name
Test status
Simulation time	53073536 ps
CPU time	1.39 seconds
Started	Apr 30 03:39:37 PM PDT 24
Finished	Apr 30 03:39:39 PM PDT 24
Peak memory	230864 kb
Host	smart-283513cf-bce7-481a-9e18-56f7d907557e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983491340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.983491340
Directory	/workspace/34.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3737885067
Short name	T1298
Test name
Test status
Simulation time	147490592 ps
CPU time	1.58 seconds
Started	Apr 30 03:39:37 PM PDT 24
Finished	Apr 30 03:39:39 PM PDT 24
Peak memory	229548 kb
Host	smart-604e0f10-1d38-4547-8def-f4dc5fd5d2c0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737885067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3737885067
Directory	/workspace/35.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.566276522
Short name	T1313
Test name
Test status
Simulation time	39226524 ps
CPU time	1.47 seconds
Started	Apr 30 03:39:36 PM PDT 24
Finished	Apr 30 03:39:39 PM PDT 24
Peak memory	229824 kb
Host	smart-800c606f-05a5-472d-afff-56fc0052038d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566276522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.566276522
Directory	/workspace/36.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.938760820
Short name	T1297
Test name
Test status
Simulation time	536001439 ps
CPU time	1.62 seconds
Started	Apr 30 03:39:43 PM PDT 24
Finished	Apr 30 03:39:45 PM PDT 24
Peak memory	229496 kb
Host	smart-6be1dbf7-fa16-4ef7-be6e-ab4b6a81e5f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938760820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.938760820
Directory	/workspace/37.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.578437606
Short name	T1284
Test name
Test status
Simulation time	68380592 ps
CPU time	1.39 seconds
Started	Apr 30 03:39:37 PM PDT 24
Finished	Apr 30 03:39:39 PM PDT 24
Peak memory	230860 kb
Host	smart-8819eb07-4072-4333-86b1-3005450a68f9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578437606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.578437606
Directory	/workspace/38.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.27323053
Short name	T1220
Test name
Test status
Simulation time	40322107 ps
CPU time	1.38 seconds
Started	Apr 30 03:39:36 PM PDT 24
Finished	Apr 30 03:39:38 PM PDT 24
Peak memory	229528 kb
Host	smart-39da2725-a800-4906-8261-0daed053e854
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27323053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.27323053
Directory	/workspace/39.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3523042968
Short name	T316
Test name
Test status
Simulation time	1571651078 ps
CPU time	3.53 seconds
Started	Apr 30 03:38:13 PM PDT 24
Finished	Apr 30 03:38:17 PM PDT 24
Peak memory	239020 kb
Host	smart-f8d9f7ca-e714-4abe-9c07-1ab9ddfb8793
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523042968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia sing.3523042968
Directory	/workspace/4.otp_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1383422567
Short name	T1278
Test name
Test status
Simulation time	6750207431 ps
CPU time	12.31 seconds
Started	Apr 30 03:38:13 PM PDT 24
Finished	Apr 30 03:38:26 PM PDT 24
Peak memory	238036 kb
Host	smart-612986b2-83fd-4ad6-9342-ec90e40f897d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383422567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_ bash.1383422567
Directory	/workspace/4.otp_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3920678661
Short name	T1314
Test name
Test status
Simulation time	181120004 ps
CPU time	2.3 seconds
Started	Apr 30 03:38:08 PM PDT 24
Finished	Apr 30 03:38:10 PM PDT 24
Peak memory	237856 kb
Host	smart-9390be48-4463-4ab7-9dde-2602b8c2e619
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920678661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r eset.3920678661
Directory	/workspace/4.otp_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.2067610209
Short name	T1230
Test name
Test status
Simulation time	190822424 ps
CPU time	2.93 seconds
Started	Apr 30 03:38:19 PM PDT 24
Finished	Apr 30 03:38:23 PM PDT 24
Peak memory	247280 kb
Host	smart-9cc49d04-e819-487e-9a55-a0a984f61a5b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067610209 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.2067610209
Directory	/workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3155510716
Short name	T1281
Test name
Test status
Simulation time	579715441 ps
CPU time	1.78 seconds
Started	Apr 30 03:38:13 PM PDT 24
Finished	Apr 30 03:38:15 PM PDT 24
Peak memory	240260 kb
Host	smart-27624bd6-cad0-4158-bbc8-fc99704fb365
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155510716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.3155510716
Directory	/workspace/4.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1129084049
Short name	T1280
Test name
Test status
Simulation time	155403060 ps
CPU time	1.45 seconds
Started	Apr 30 03:38:10 PM PDT 24
Finished	Apr 30 03:38:12 PM PDT 24
Peak memory	229556 kb
Host	smart-fab420a3-cfab-4179-bb53-0080ed21d42f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129084049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.1129084049
Directory	/workspace/4.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.4115785116
Short name	T1255
Test name
Test status
Simulation time	563722156 ps
CPU time	1.6 seconds
Started	Apr 30 03:38:08 PM PDT 24
Finished	Apr 30 03:38:10 PM PDT 24
Peak memory	229688 kb
Host	smart-04614903-a334-4a32-b783-4268c16ccf02
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115785116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr l_mem_partial_access.4115785116
Directory	/workspace/4.otp_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.1218498614
Short name	T1299
Test name
Test status
Simulation time	78959644 ps
CPU time	1.33 seconds
Started	Apr 30 03:38:10 PM PDT 24
Finished	Apr 30 03:38:11 PM PDT 24
Peak memory	229560 kb
Host	smart-ce0a8398-50bc-4a74-815a-0c6a2e8097bf
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218498614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk .1218498614
Directory	/workspace/4.otp_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1338271094
Short name	T1318
Test name
Test status
Simulation time	174595934 ps
CPU time	2.22 seconds
Started	Apr 30 03:38:18 PM PDT 24
Finished	Apr 30 03:38:20 PM PDT 24
Peak memory	238192 kb
Host	smart-cba367d9-dbbc-4448-92ce-0175d16fd29e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338271094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c trl_same_csr_outstanding.1338271094
Directory	/workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1892423411
Short name	T1322
Test name
Test status
Simulation time	121705172 ps
CPU time	4.59 seconds
Started	Apr 30 03:38:08 PM PDT 24
Finished	Apr 30 03:38:13 PM PDT 24
Peak memory	246824 kb
Host	smart-a692ab8f-8115-4a70-9c07-b0262c24b557
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892423411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.1892423411
Directory	/workspace/4.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1994899399
Short name	T1252
Test name
Test status
Simulation time	1353451738 ps
CPU time	10.29 seconds
Started	Apr 30 03:38:09 PM PDT 24
Finished	Apr 30 03:38:20 PM PDT 24
Peak memory	243992 kb
Host	smart-61426ad4-2d43-432f-9ecc-1ad2cb64b81d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994899399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in tg_err.1994899399
Directory	/workspace/4.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2230089334
Short name	T1201
Test name
Test status
Simulation time	38888019 ps
CPU time	1.36 seconds
Started	Apr 30 03:39:38 PM PDT 24
Finished	Apr 30 03:39:41 PM PDT 24
Peak memory	230868 kb
Host	smart-d3b8b034-204b-40c9-91d6-04d209e9803a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230089334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2230089334
Directory	/workspace/40.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.4249510705
Short name	T1292
Test name
Test status
Simulation time	39299896 ps
CPU time	1.4 seconds
Started	Apr 30 03:39:36 PM PDT 24
Finished	Apr 30 03:39:38 PM PDT 24
Peak memory	229704 kb
Host	smart-618000f1-7190-4c96-9c7d-b0428a9cbd09
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249510705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.4249510705
Directory	/workspace/41.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.479112133
Short name	T1262
Test name
Test status
Simulation time	39285190 ps
CPU time	1.48 seconds
Started	Apr 30 03:39:44 PM PDT 24
Finished	Apr 30 03:39:46 PM PDT 24
Peak memory	229496 kb
Host	smart-c5e20992-563e-4127-98bd-819696cde249
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479112133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.479112133
Directory	/workspace/42.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.953097551
Short name	T1226
Test name
Test status
Simulation time	60855015 ps
CPU time	1.35 seconds
Started	Apr 30 03:39:42 PM PDT 24
Finished	Apr 30 03:39:44 PM PDT 24
Peak memory	230936 kb
Host	smart-be58ad48-dd2b-4236-8960-c9c78910541b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953097551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.953097551
Directory	/workspace/43.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.821602225
Short name	T1317
Test name
Test status
Simulation time	38893287 ps
CPU time	1.5 seconds
Started	Apr 30 03:39:45 PM PDT 24
Finished	Apr 30 03:39:47 PM PDT 24
Peak memory	230784 kb
Host	smart-6e6eeb57-be90-46f5-a292-6e2ed042f925
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821602225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.821602225
Directory	/workspace/44.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.1246747790
Short name	T1212
Test name
Test status
Simulation time	84174830 ps
CPU time	1.42 seconds
Started	Apr 30 03:39:43 PM PDT 24
Finished	Apr 30 03:39:45 PM PDT 24
Peak memory	229584 kb
Host	smart-91d22634-8367-4088-b66a-342b98079d52
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246747790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.1246747790
Directory	/workspace/45.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2391151112
Short name	T1247
Test name
Test status
Simulation time	43357335 ps
CPU time	1.37 seconds
Started	Apr 30 03:39:43 PM PDT 24
Finished	Apr 30 03:39:44 PM PDT 24
Peak memory	229596 kb
Host	smart-145d79d5-21c3-439c-80f2-3c3a950de107
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391151112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.2391151112
Directory	/workspace/46.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1155893425
Short name	T1199
Test name
Test status
Simulation time	41750476 ps
CPU time	1.4 seconds
Started	Apr 30 03:39:41 PM PDT 24
Finished	Apr 30 03:39:43 PM PDT 24
Peak memory	230792 kb
Host	smart-90cf52dc-92c3-413a-ac32-9148a2945b16
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155893425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.1155893425
Directory	/workspace/47.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.3811902261
Short name	T1225
Test name
Test status
Simulation time	41194278 ps
CPU time	1.39 seconds
Started	Apr 30 03:39:44 PM PDT 24
Finished	Apr 30 03:39:46 PM PDT 24
Peak memory	229544 kb
Host	smart-dc22afe2-123a-4d08-84e2-a3de133c7593
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811902261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.3811902261
Directory	/workspace/48.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3850481071
Short name	T1329
Test name
Test status
Simulation time	37780007 ps
CPU time	1.37 seconds
Started	Apr 30 03:39:51 PM PDT 24
Finished	Apr 30 03:39:52 PM PDT 24
Peak memory	229572 kb
Host	smart-31f31f53-a962-4575-88ca-9ea45a845a6c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850481071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3850481071
Directory	/workspace/49.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.519736846
Short name	T1327
Test name
Test status
Simulation time	1569946429 ps
CPU time	4.16 seconds
Started	Apr 30 03:38:24 PM PDT 24
Finished	Apr 30 03:38:28 PM PDT 24
Peak memory	247324 kb
Host	smart-5c6ba3bf-46ba-4f8e-b0b0-1a4fbb905687
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519736846 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.519736846
Directory	/workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.2678336430
Short name	T1232
Test name
Test status
Simulation time	83408738 ps
CPU time	1.63 seconds
Started	Apr 30 03:38:23 PM PDT 24
Finished	Apr 30 03:38:25 PM PDT 24
Peak memory	238972 kb
Host	smart-1780ee77-9bda-4ef1-8d30-3b86c5f65e03
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678336430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.2678336430
Directory	/workspace/5.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.1027363322
Short name	T1223
Test name
Test status
Simulation time	556903786 ps
CPU time	1.83 seconds
Started	Apr 30 03:38:19 PM PDT 24
Finished	Apr 30 03:38:21 PM PDT 24
Peak memory	229648 kb
Host	smart-1005d16e-66a9-44c8-b61d-e49931e683a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027363322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.1027363322
Directory	/workspace/5.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3159872394
Short name	T1285
Test name
Test status
Simulation time	255703536 ps
CPU time	2.68 seconds
Started	Apr 30 03:38:23 PM PDT 24
Finished	Apr 30 03:38:26 PM PDT 24
Peak memory	237972 kb
Host	smart-82bf4229-dab3-4e8e-ac89-fb7e037f10d5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159872394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c trl_same_csr_outstanding.3159872394
Directory	/workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.610034394
Short name	T1265
Test name
Test status
Simulation time	179268540 ps
CPU time	6.99 seconds
Started	Apr 30 03:38:19 PM PDT 24
Finished	Apr 30 03:38:26 PM PDT 24
Peak memory	247212 kb
Host	smart-1c788c8b-f264-4378-857b-ce87142051d6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610034394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.610034394
Directory	/workspace/5.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.855198442
Short name	T371
Test name
Test status
Simulation time	4784964969 ps
CPU time	23.43 seconds
Started	Apr 30 03:38:18 PM PDT 24
Finished	Apr 30 03:38:42 PM PDT 24
Peak memory	244292 kb
Host	smart-34d7c776-43da-45b6-a86e-13bd3dd0f2a2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855198442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_int g_err.855198442
Directory	/workspace/5.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1857645353
Short name	T1217
Test name
Test status
Simulation time	99928952 ps
CPU time	3.55 seconds
Started	Apr 30 03:38:29 PM PDT 24
Finished	Apr 30 03:38:33 PM PDT 24
Peak memory	247276 kb
Host	smart-1bfe38b4-43d4-415b-9c16-eb3917df9179
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857645353 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.1857645353
Directory	/workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.3947898572
Short name	T309
Test name
Test status
Simulation time	150127490 ps
CPU time	1.64 seconds
Started	Apr 30 03:38:21 PM PDT 24
Finished	Apr 30 03:38:23 PM PDT 24
Peak memory	239076 kb
Host	smart-e4220ddb-2a1d-4dd0-a3fa-03cec144c4d8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947898572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.3947898572
Directory	/workspace/6.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.4271301848
Short name	T1253
Test name
Test status
Simulation time	43749975 ps
CPU time	1.4 seconds
Started	Apr 30 03:38:22 PM PDT 24
Finished	Apr 30 03:38:23 PM PDT 24
Peak memory	229508 kb
Host	smart-09ed4690-8845-4fee-b25b-9c29aaf6734c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271301848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.4271301848
Directory	/workspace/6.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.588901754
Short name	T1306
Test name
Test status
Simulation time	256347921 ps
CPU time	2.44 seconds
Started	Apr 30 03:38:30 PM PDT 24
Finished	Apr 30 03:38:32 PM PDT 24
Peak memory	239040 kb
Host	smart-2e824332-6299-4545-a369-2a1d41b3cd3f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588901754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ct rl_same_csr_outstanding.588901754
Directory	/workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.2209397810
Short name	T1208
Test name
Test status
Simulation time	187093499 ps
CPU time	6.73 seconds
Started	Apr 30 03:38:23 PM PDT 24
Finished	Apr 30 03:38:30 PM PDT 24
Peak memory	246844 kb
Host	smart-3a60e116-19cc-479c-9b7c-33828a8a3a6a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209397810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.2209397810
Directory	/workspace/6.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1657712726
Short name	T1294
Test name
Test status
Simulation time	1263383292 ps
CPU time	10.96 seconds
Started	Apr 30 03:38:22 PM PDT 24
Finished	Apr 30 03:38:34 PM PDT 24
Peak memory	244000 kb
Host	smart-7a7be3f8-ac09-4b52-900b-301b0bc7c2f1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657712726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in tg_err.1657712726
Directory	/workspace/6.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3259590383
Short name	T1283
Test name
Test status
Simulation time	1653069913 ps
CPU time	2.9 seconds
Started	Apr 30 03:38:34 PM PDT 24
Finished	Apr 30 03:38:37 PM PDT 24
Peak memory	246460 kb
Host	smart-7b13cdfe-90e0-406b-8b07-b863d631de97
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259590383 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.3259590383
Directory	/workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3244144263
Short name	T306
Test name
Test status
Simulation time	673308066 ps
CPU time	2.03 seconds
Started	Apr 30 03:38:29 PM PDT 24
Finished	Apr 30 03:38:32 PM PDT 24
Peak memory	240140 kb
Host	smart-8d1ddb9d-43f0-4adb-860e-9314ed30bb52
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244144263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.3244144263
Directory	/workspace/7.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.258007936
Short name	T1204
Test name
Test status
Simulation time	42491358 ps
CPU time	1.47 seconds
Started	Apr 30 03:38:29 PM PDT 24
Finished	Apr 30 03:38:31 PM PDT 24
Peak memory	229612 kb
Host	smart-52cce199-3248-4717-b8ba-83d23e97fcb8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258007936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.258007936
Directory	/workspace/7.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.2377591815
Short name	T348
Test name
Test status
Simulation time	206108581 ps
CPU time	2.23 seconds
Started	Apr 30 03:38:28 PM PDT 24
Finished	Apr 30 03:38:31 PM PDT 24
Peak memory	239032 kb
Host	smart-94d3a56a-7f1c-4592-89fb-710f0e209db7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377591815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c trl_same_csr_outstanding.2377591815
Directory	/workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3932273646
Short name	T1274
Test name
Test status
Simulation time	669429777 ps
CPU time	7.46 seconds
Started	Apr 30 03:38:28 PM PDT 24
Finished	Apr 30 03:38:36 PM PDT 24
Peak memory	246876 kb
Host	smart-baa635b4-0da6-44c3-b71c-b9e9db7ffd1c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932273646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3932273646
Directory	/workspace/7.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.4098844039
Short name	T1266
Test name
Test status
Simulation time	10370408329 ps
CPU time	10.46 seconds
Started	Apr 30 03:38:28 PM PDT 24
Finished	Apr 30 03:38:39 PM PDT 24
Peak memory	244580 kb
Host	smart-aff240de-df1b-4d03-86e0-de79718514fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098844039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in tg_err.4098844039
Directory	/workspace/7.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.430371377
Short name	T397
Test name
Test status
Simulation time	110949685 ps
CPU time	2.92 seconds
Started	Apr 30 03:38:55 PM PDT 24
Finished	Apr 30 03:38:59 PM PDT 24
Peak memory	247152 kb
Host	smart-542342f0-cf01-4892-a382-ef6c1a564cd8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430371377 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.430371377
Directory	/workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3224837995
Short name	T1295
Test name
Test status
Simulation time	70210543 ps
CPU time	1.53 seconds
Started	Apr 30 03:38:55 PM PDT 24
Finished	Apr 30 03:38:57 PM PDT 24
Peak memory	239932 kb
Host	smart-4debeb51-f3d6-467c-aee7-172174ef5527
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224837995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.3224837995
Directory	/workspace/8.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.3762663160
Short name	T1216
Test name
Test status
Simulation time	69378278 ps
CPU time	1.38 seconds
Started	Apr 30 03:38:33 PM PDT 24
Finished	Apr 30 03:38:35 PM PDT 24
Peak memory	229424 kb
Host	smart-36698020-f87c-4a06-961b-3a3c863b07e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762663160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.3762663160
Directory	/workspace/8.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3955878390
Short name	T1305
Test name
Test status
Simulation time	691363388 ps
CPU time	1.93 seconds
Started	Apr 30 03:38:56 PM PDT 24
Finished	Apr 30 03:38:58 PM PDT 24
Peak memory	239012 kb
Host	smart-47fbd3bd-1534-450a-8630-56c407b42357
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955878390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c trl_same_csr_outstanding.3955878390
Directory	/workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3663708727
Short name	T1237
Test name
Test status
Simulation time	85597480 ps
CPU time	4.45 seconds
Started	Apr 30 03:38:30 PM PDT 24
Finished	Apr 30 03:38:35 PM PDT 24
Peak memory	246760 kb
Host	smart-00f5e4aa-994e-410e-8855-245f65482cec
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663708727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.3663708727
Directory	/workspace/8.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.4184260817
Short name	T1264
Test name
Test status
Simulation time	18993445698 ps
CPU time	20.17 seconds
Started	Apr 30 03:38:33 PM PDT 24
Finished	Apr 30 03:38:54 PM PDT 24
Peak memory	244792 kb
Host	smart-33b26dde-e9cf-4f3a-a623-06711fdcc24c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184260817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in tg_err.4184260817
Directory	/workspace/8.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3959051993
Short name	T1271
Test name
Test status
Simulation time	82965510 ps
CPU time	2.35 seconds
Started	Apr 30 03:38:42 PM PDT 24
Finished	Apr 30 03:38:45 PM PDT 24
Peak memory	246520 kb
Host	smart-ce2d8ca0-44e8-4699-976a-e7d1fa402689
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959051993 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.3959051993
Directory	/workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1627071817
Short name	T305
Test name
Test status
Simulation time	45919720 ps
CPU time	1.74 seconds
Started	Apr 30 03:38:55 PM PDT 24
Finished	Apr 30 03:38:57 PM PDT 24
Peak memory	240448 kb
Host	smart-7924fb12-9b39-4147-8d15-a92b8db84e01
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627071817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1627071817
Directory	/workspace/9.otp_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1609813961
Short name	T1233
Test name
Test status
Simulation time	561809557 ps
CPU time	1.81 seconds
Started	Apr 30 03:38:56 PM PDT 24
Finished	Apr 30 03:38:58 PM PDT 24
Peak memory	229488 kb
Host	smart-9d4addc4-1c86-4a18-9eb3-399fbeb67e60
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609813961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.1609813961
Directory	/workspace/9.otp_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.2830268419
Short name	T277
Test name
Test status
Simulation time	133957370 ps
CPU time	2.24 seconds
Started	Apr 30 03:38:41 PM PDT 24
Finished	Apr 30 03:38:43 PM PDT 24
Peak memory	238936 kb
Host	smart-006993d0-cee0-4b89-8503-6719228694bf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830268419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c trl_same_csr_outstanding.2830268419
Directory	/workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2985848544
Short name	T1286
Test name
Test status
Simulation time	163242781 ps
CPU time	6.5 seconds
Started	Apr 30 03:38:55 PM PDT 24
Finished	Apr 30 03:39:02 PM PDT 24
Peak memory	246964 kb
Host	smart-a0736f24-786e-4eee-aa12-e76caec2b028
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985848544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.2985848544
Directory	/workspace/9.otp_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.4079999242
Short name	T270
Test name
Test status
Simulation time	1449731214 ps
CPU time	19.06 seconds
Started	Apr 30 03:38:55 PM PDT 24
Finished	Apr 30 03:39:14 PM PDT 24
Peak memory	244352 kb
Host	smart-b1c17a63-8739-44a1-a9a7-397c05fa0651
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079999242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in tg_err.4079999242
Directory	/workspace/9.otp_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.otp_ctrl_alert_test.2868876036
Short name	T925
Test name
Test status
Simulation time	50951213 ps
CPU time	1.65 seconds
Started	Apr 30 03:39:57 PM PDT 24
Finished	Apr 30 03:39:59 PM PDT 24
Peak memory	239980 kb
Host	smart-f25610ab-dddd-4873-9b2b-388b3ee053c5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868876036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.2868876036
Directory	/workspace/0.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.otp_ctrl_background_chks.1798292679
Short name	T942
Test name
Test status
Simulation time	948000418 ps
CPU time	16.97 seconds
Started	Apr 30 03:39:51 PM PDT 24
Finished	Apr 30 03:40:08 PM PDT 24
Peak memory	241424 kb
Host	smart-8323ba32-c583-4fd0-9681-e437e3c90f6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798292679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.1798292679
Directory	/workspace/0.otp_ctrl_background_chks/latest

Test location	/workspace/coverage/default/0.otp_ctrl_check_fail.2877966048
Short name	T686
Test name
Test status
Simulation time	168116093 ps
CPU time	4.46 seconds
Started	Apr 30 03:39:52 PM PDT 24
Finished	Apr 30 03:39:57 PM PDT 24
Peak memory	241336 kb
Host	smart-bc9c6574-f36a-451c-a744-c1e3f75fbe07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877966048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.2877966048
Directory	/workspace/0.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/0.otp_ctrl_dai_errs.1820415910
Short name	T189
Test name
Test status
Simulation time	439856322 ps
CPU time	11.13 seconds
Started	Apr 30 03:39:52 PM PDT 24
Finished	Apr 30 03:40:04 PM PDT 24
Peak memory	241296 kb
Host	smart-45a7738a-8dbb-4772-87e2-5522dc3ee327
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820415910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.1820415910
Directory	/workspace/0.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/0.otp_ctrl_dai_lock.1201662975
Short name	T799
Test name
Test status
Simulation time	983584479 ps
CPU time	19.67 seconds
Started	Apr 30 03:39:51 PM PDT 24
Finished	Apr 30 03:40:11 PM PDT 24
Peak memory	241436 kb
Host	smart-1a414b33-4278-43c9-81e0-823b89929c31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201662975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.1201662975
Directory	/workspace/0.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/0.otp_ctrl_init_fail.4065620352
Short name	T139
Test name
Test status
Simulation time	133776246 ps
CPU time	3.33 seconds
Started	Apr 30 03:39:48 PM PDT 24
Finished	Apr 30 03:39:52 PM PDT 24
Peak memory	241672 kb
Host	smart-5541abfc-3af6-4bab-b44a-99a6336bddd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065620352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.4065620352
Directory	/workspace/0.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/0.otp_ctrl_low_freq_read.3659190626
Short name	T320
Test name
Test status
Simulation time	5899285537 ps
CPU time	13.43 seconds
Started	Apr 30 03:39:46 PM PDT 24
Finished	Apr 30 03:39:59 PM PDT 24
Peak memory	240864 kb
Host	smart-016176a3-f43c-4e78-8955-6d5ff4912499
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3659190626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.3659190626
Directory	/workspace/0.otp_ctrl_low_freq_read/latest

Test location	/workspace/coverage/default/0.otp_ctrl_macro_errs.546100124
Short name	T582
Test name
Test status
Simulation time	3518622515 ps
CPU time	33.19 seconds
Started	Apr 30 03:39:50 PM PDT 24
Finished	Apr 30 03:40:23 PM PDT 24
Peak memory	248148 kb
Host	smart-4ce5aed0-a8b6-4bd8-9384-5753435c758c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=546100124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.546100124
Directory	/workspace/0.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/0.otp_ctrl_parallel_key_req.1358169866
Short name	T103
Test name
Test status
Simulation time	2248987361 ps
CPU time	15.24 seconds
Started	Apr 30 03:39:57 PM PDT 24
Finished	Apr 30 03:40:13 PM PDT 24
Peak memory	241296 kb
Host	smart-228c1434-1a1c-422b-850e-d0c47a0f1660
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1358169866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.1358169866
Directory	/workspace/0.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.3336797739
Short name	T913
Test name
Test status
Simulation time	2940305903 ps
CPU time	11.01 seconds
Started	Apr 30 03:39:53 PM PDT 24
Finished	Apr 30 03:40:05 PM PDT 24
Peak memory	241784 kb
Host	smart-c9c16131-99e8-461f-a433-74fd080810c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3336797739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.3336797739
Directory	/workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/0.otp_ctrl_parallel_lc_req.2143907124
Short name	T1055
Test name
Test status
Simulation time	973879034 ps
CPU time	19.47 seconds
Started	Apr 30 03:39:46 PM PDT 24
Finished	Apr 30 03:40:06 PM PDT 24
Peak memory	247984 kb
Host	smart-3b5d8904-d877-4418-9474-d1695b9fb28f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2143907124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.2143907124
Directory	/workspace/0.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/0.otp_ctrl_partition_walk.1310071679
Short name	T150
Test name
Test status
Simulation time	643261704 ps
CPU time	19.6 seconds
Started	Apr 30 03:39:48 PM PDT 24
Finished	Apr 30 03:40:08 PM PDT 24
Peak memory	241188 kb
Host	smart-7fee23b8-893a-42d3-8a1a-337840b1bcf2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1310071679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.1310071679
Directory	/workspace/0.otp_ctrl_partition_walk/latest

Test location	/workspace/coverage/default/0.otp_ctrl_regwen.3553751746
Short name	T859
Test name
Test status
Simulation time	225600733 ps
CPU time	5.36 seconds
Started	Apr 30 03:39:53 PM PDT 24
Finished	Apr 30 03:39:59 PM PDT 24
Peak memory	241548 kb
Host	smart-1315a693-f345-4c3c-941a-f89eead452e9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3553751746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.3553751746
Directory	/workspace/0.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/0.otp_ctrl_sec_cm.1185678686
Short name	T238
Test name
Test status
Simulation time	10696742537 ps
CPU time	194.99 seconds
Started	Apr 30 03:39:57 PM PDT 24
Finished	Apr 30 03:43:12 PM PDT 24
Peak memory	269868 kb
Host	smart-5e593370-bf32-47a2-81d4-d5bfae1313cd
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185678686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.1185678686
Directory	/workspace/0.otp_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/0.otp_ctrl_smoke.51884175
Short name	T759
Test name
Test status
Simulation time	607342639 ps
CPU time	4.02 seconds
Started	Apr 30 03:39:55 PM PDT 24
Finished	Apr 30 03:39:59 PM PDT 24
Peak memory	241260 kb
Host	smart-9f3aa39a-fb3b-4e2c-942c-4f8d3264e520
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51884175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.51884175
Directory	/workspace/0.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.otp_ctrl_stress_all.3594143178
Short name	T807
Test name
Test status
Simulation time	13083124094 ps
CPU time	197.17 seconds
Started	Apr 30 03:39:52 PM PDT 24
Finished	Apr 30 03:43:10 PM PDT 24
Peak memory	307452 kb
Host	smart-86d8257e-e7a6-4e4d-9891-ac67cfb84e12
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594143178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all. 3594143178
Directory	/workspace/0.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.otp_ctrl_test_access.1784218361
Short name	T102
Test name
Test status
Simulation time	1029823833 ps
CPU time	33.84 seconds
Started	Apr 30 03:39:52 PM PDT 24
Finished	Apr 30 03:40:26 PM PDT 24
Peak memory	241520 kb
Host	smart-29a1a41d-1823-4220-9f2f-f85c52ade1fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1784218361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.1784218361
Directory	/workspace/0.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/0.otp_ctrl_wake_up.1291157274
Short name	T682
Test name
Test status
Simulation time	52437971 ps
CPU time	1.66 seconds
Started	Apr 30 03:39:46 PM PDT 24
Finished	Apr 30 03:39:48 PM PDT 24
Peak memory	239804 kb
Host	smart-1dba5fdf-1081-4c61-85bd-a52db50fde57
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1291157274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.1291157274
Directory	/workspace/0.otp_ctrl_wake_up/latest

Test location	/workspace/coverage/default/1.otp_ctrl_alert_test.2542865528
Short name	T1107
Test name
Test status
Simulation time	111480784 ps
CPU time	1.66 seconds
Started	Apr 30 03:40:06 PM PDT 24
Finished	Apr 30 03:40:08 PM PDT 24
Peak memory	239904 kb
Host	smart-051ebe39-2a69-442e-9ca5-0f72944f00ef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542865528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.2542865528
Directory	/workspace/1.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.otp_ctrl_background_chks.2375999299
Short name	T936
Test name
Test status
Simulation time	1025041618 ps
CPU time	13.74 seconds
Started	Apr 30 03:39:55 PM PDT 24
Finished	Apr 30 03:40:09 PM PDT 24
Peak memory	241464 kb
Host	smart-5df4a42a-dbc9-4918-8006-68b055004b86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2375999299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.2375999299
Directory	/workspace/1.otp_ctrl_background_chks/latest

Test location	/workspace/coverage/default/1.otp_ctrl_check_fail.1255347351
Short name	T1187
Test name
Test status
Simulation time	2096671005 ps
CPU time	12.05 seconds
Started	Apr 30 03:40:04 PM PDT 24
Finished	Apr 30 03:40:16 PM PDT 24
Peak memory	243016 kb
Host	smart-2b518a59-570f-4751-9701-56b2ffc58bef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1255347351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1255347351
Directory	/workspace/1.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/1.otp_ctrl_dai_errs.3143653864
Short name	T860
Test name
Test status
Simulation time	4485918554 ps
CPU time	50.13 seconds
Started	Apr 30 03:40:00 PM PDT 24
Finished	Apr 30 03:40:51 PM PDT 24
Peak memory	254388 kb
Host	smart-66d7e6f0-ede9-4a78-b670-06e982ae00eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143653864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.3143653864
Directory	/workspace/1.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/1.otp_ctrl_dai_lock.1446128663
Short name	T623
Test name
Test status
Simulation time	5936933445 ps
CPU time	39.03 seconds
Started	Apr 30 03:40:01 PM PDT 24
Finished	Apr 30 03:40:41 PM PDT 24
Peak memory	241676 kb
Host	smart-0fc8a667-88f6-4881-8d19-bea54c979afa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1446128663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.1446128663
Directory	/workspace/1.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/1.otp_ctrl_macro_errs.3084342171
Short name	T1063
Test name
Test status
Simulation time	948112041 ps
CPU time	21.2 seconds
Started	Apr 30 03:40:01 PM PDT 24
Finished	Apr 30 03:40:23 PM PDT 24
Peak memory	241352 kb
Host	smart-df774b1a-9a1b-444a-8b69-b9bdc18a07bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3084342171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.3084342171
Directory	/workspace/1.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/1.otp_ctrl_parallel_key_req.3825261053
Short name	T904
Test name
Test status
Simulation time	2024437730 ps
CPU time	47.47 seconds
Started	Apr 30 03:40:00 PM PDT 24
Finished	Apr 30 03:40:48 PM PDT 24
Peak memory	241724 kb
Host	smart-213b902e-2604-4cfb-add5-53bc62e1cb6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3825261053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.3825261053
Directory	/workspace/1.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.2867363238
Short name	T451
Test name
Test status
Simulation time	973848372 ps
CPU time	18.98 seconds
Started	Apr 30 03:40:01 PM PDT 24
Finished	Apr 30 03:40:21 PM PDT 24
Peak memory	241532 kb
Host	smart-4740dd6c-ddad-4586-bea8-80fa00e741c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867363238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.2867363238
Directory	/workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/1.otp_ctrl_parallel_lc_req.2190798836
Short name	T1181
Test name
Test status
Simulation time	12171030965 ps
CPU time	30.5 seconds
Started	Apr 30 03:39:56 PM PDT 24
Finished	Apr 30 03:40:27 PM PDT 24
Peak memory	241352 kb
Host	smart-0ec0b5cc-5058-4cf0-a8c8-e25f21de254f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2190798836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.2190798836
Directory	/workspace/1.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/1.otp_ctrl_regwen.1239855318
Short name	T964
Test name
Test status
Simulation time	369039611 ps
CPU time	5.39 seconds
Started	Apr 30 03:40:03 PM PDT 24
Finished	Apr 30 03:40:09 PM PDT 24
Peak memory	241832 kb
Host	smart-b70db61d-9d76-4e54-a4a3-c5d0b47c933b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1239855318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.1239855318
Directory	/workspace/1.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/1.otp_ctrl_sec_cm.1618098018
Short name	T22
Test name
Test status
Simulation time	10471653986 ps
CPU time	195.45 seconds
Started	Apr 30 03:40:06 PM PDT 24
Finished	Apr 30 03:43:22 PM PDT 24
Peak memory	270108 kb
Host	smart-82559800-362e-46fc-99a4-d94f97523c84
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618098018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.1618098018
Directory	/workspace/1.otp_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.otp_ctrl_smoke.860245898
Short name	T289
Test name
Test status
Simulation time	532818426 ps
CPU time	7.99 seconds
Started	Apr 30 03:39:57 PM PDT 24
Finished	Apr 30 03:40:06 PM PDT 24
Peak memory	241604 kb
Host	smart-0700359e-fca8-44b2-835d-99ecfb8a13e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=860245898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.860245898
Directory	/workspace/1.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.1277143552
Short name	T409
Test name
Test status
Simulation time	148657124060 ps
CPU time	1185.72 seconds
Started	Apr 30 03:40:04 PM PDT 24
Finished	Apr 30 03:59:50 PM PDT 24
Peak memory	366988 kb
Host	smart-182783ce-cae7-46eb-80a9-4a638853061d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277143552 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.1277143552
Directory	/workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.otp_ctrl_test_access.2705405879
Short name	T401
Test name
Test status
Simulation time	968231004 ps
CPU time	18.81 seconds
Started	Apr 30 03:40:01 PM PDT 24
Finished	Apr 30 03:40:21 PM PDT 24
Peak memory	241612 kb
Host	smart-2a47c7ae-8e0b-404e-8bea-b9074add59ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2705405879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.2705405879
Directory	/workspace/1.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/10.otp_ctrl_alert_test.1702213715
Short name	T1192
Test name
Test status
Simulation time	173990225 ps
CPU time	1.6 seconds
Started	Apr 30 03:41:25 PM PDT 24
Finished	Apr 30 03:41:27 PM PDT 24
Peak memory	239984 kb
Host	smart-3304af94-d1ff-4387-aa0a-8a977aee385a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702213715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.1702213715
Directory	/workspace/10.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.otp_ctrl_dai_errs.2982774033
Short name	T1048
Test name
Test status
Simulation time	464807985 ps
CPU time	9.52 seconds
Started	Apr 30 03:41:26 PM PDT 24
Finished	Apr 30 03:41:36 PM PDT 24
Peak memory	241288 kb
Host	smart-374fc8bb-37e1-4af9-9bb0-c1d5c5c8f146
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2982774033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.2982774033
Directory	/workspace/10.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/10.otp_ctrl_dai_lock.1090292132
Short name	T661
Test name
Test status
Simulation time	9839817086 ps
CPU time	35.67 seconds
Started	Apr 30 03:41:21 PM PDT 24
Finished	Apr 30 03:41:57 PM PDT 24
Peak memory	242248 kb
Host	smart-6c923bd1-f620-42b9-9fd9-54da2b5f90fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090292132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.1090292132
Directory	/workspace/10.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/10.otp_ctrl_init_fail.2606688624
Short name	T525
Test name
Test status
Simulation time	374244608 ps
CPU time	4.51 seconds
Started	Apr 30 03:41:22 PM PDT 24
Finished	Apr 30 03:41:27 PM PDT 24
Peak memory	241396 kb
Host	smart-1363e2ea-0945-4512-913f-43d301a7bfeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606688624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.2606688624
Directory	/workspace/10.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/10.otp_ctrl_parallel_key_req.3153322701
Short name	T1135
Test name
Test status
Simulation time	5028633724 ps
CPU time	37.54 seconds
Started	Apr 30 03:41:25 PM PDT 24
Finished	Apr 30 03:42:03 PM PDT 24
Peak memory	248112 kb
Host	smart-a46eac58-eb13-4fef-b0c1-5a90194f59db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153322701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.3153322701
Directory	/workspace/10.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/10.otp_ctrl_parallel_lc_req.3682247213
Short name	T333
Test name
Test status
Simulation time	308453049 ps
CPU time	4.7 seconds
Started	Apr 30 03:41:21 PM PDT 24
Finished	Apr 30 03:41:26 PM PDT 24
Peak memory	241236 kb
Host	smart-2abce67c-b620-4037-b362-eb33e5aff644
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3682247213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.3682247213
Directory	/workspace/10.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/10.otp_ctrl_regwen.4198716268
Short name	T839
Test name
Test status
Simulation time	426511817 ps
CPU time	5.33 seconds
Started	Apr 30 03:41:26 PM PDT 24
Finished	Apr 30 03:41:31 PM PDT 24
Peak memory	247912 kb
Host	smart-c0816bb9-8bcf-497e-97bd-c322b8372fdc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4198716268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.4198716268
Directory	/workspace/10.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/10.otp_ctrl_smoke.2162647064
Short name	T1067
Test name
Test status
Simulation time	408236510 ps
CPU time	6.44 seconds
Started	Apr 30 03:41:21 PM PDT 24
Finished	Apr 30 03:41:28 PM PDT 24
Peak memory	241348 kb
Host	smart-dd37a301-cb07-4d28-9fbd-335bc36cc43a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2162647064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.2162647064
Directory	/workspace/10.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.otp_ctrl_test_access.3628808841
Short name	T792
Test name
Test status
Simulation time	20230430961 ps
CPU time	37.46 seconds
Started	Apr 30 03:41:25 PM PDT 24
Finished	Apr 30 03:42:02 PM PDT 24
Peak memory	242328 kb
Host	smart-8960a66b-d801-4809-a5e8-b044bc2f2c9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628808841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.3628808841
Directory	/workspace/10.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/100.otp_ctrl_init_fail.3350833027
Short name	T992
Test name
Test status
Simulation time	2460498313 ps
CPU time	5.7 seconds
Started	Apr 30 03:46:54 PM PDT 24
Finished	Apr 30 03:47:00 PM PDT 24
Peak memory	241628 kb
Host	smart-29424223-45b9-4e8f-bfd1-754a54a11ad4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350833027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.3350833027
Directory	/workspace/100.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.3389874741
Short name	T958
Test name
Test status
Simulation time	1357856830 ps
CPU time	11.86 seconds
Started	Apr 30 03:46:58 PM PDT 24
Finished	Apr 30 03:47:10 PM PDT 24
Peak memory	241348 kb
Host	smart-bf4e226c-74bb-47d3-a30a-648907ee1796
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3389874741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.3389874741
Directory	/workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.667618746
Short name	T249
Test name
Test status
Simulation time	1795135683 ps
CPU time	18.12 seconds
Started	Apr 30 03:47:00 PM PDT 24
Finished	Apr 30 03:47:19 PM PDT 24
Peak memory	241624 kb
Host	smart-e0dd4880-a744-4247-bfa8-7cf28bdff355
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=667618746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.667618746
Directory	/workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/102.otp_ctrl_init_fail.1095805474
Short name	T350
Test name
Test status
Simulation time	278964135 ps
CPU time	4.15 seconds
Started	Apr 30 03:47:07 PM PDT 24
Finished	Apr 30 03:47:11 PM PDT 24
Peak memory	241432 kb
Host	smart-c1638cc6-8d99-4bd9-8482-c77fa5483e95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095805474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.1095805474
Directory	/workspace/102.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.2341943360
Short name	T469
Test name
Test status
Simulation time	156654003 ps
CPU time	3.86 seconds
Started	Apr 30 03:47:06 PM PDT 24
Finished	Apr 30 03:47:10 PM PDT 24
Peak memory	241184 kb
Host	smart-14acf2ea-a642-4425-a131-bf82b39c622b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2341943360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.2341943360
Directory	/workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/103.otp_ctrl_init_fail.694409160
Short name	T985
Test name
Test status
Simulation time	1619359088 ps
CPU time	4.65 seconds
Started	Apr 30 03:47:07 PM PDT 24
Finished	Apr 30 03:47:13 PM PDT 24
Peak memory	241324 kb
Host	smart-6082e285-03d9-4051-8abd-619863ca97df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=694409160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.694409160
Directory	/workspace/103.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.1209003428
Short name	T752
Test name
Test status
Simulation time	331377865 ps
CPU time	3.72 seconds
Started	Apr 30 03:47:00 PM PDT 24
Finished	Apr 30 03:47:04 PM PDT 24
Peak memory	246672 kb
Host	smart-07933c9f-1672-4341-ba20-d00ad71fdfb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1209003428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1209003428
Directory	/workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.447774858
Short name	T553
Test name
Test status
Simulation time	149250101 ps
CPU time	5.09 seconds
Started	Apr 30 03:47:09 PM PDT 24
Finished	Apr 30 03:47:15 PM PDT 24
Peak memory	241672 kb
Host	smart-c4d17d37-7556-4f0b-b247-3f4ca31da936
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=447774858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.447774858
Directory	/workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/105.otp_ctrl_init_fail.2191981416
Short name	T665
Test name
Test status
Simulation time	333390175 ps
CPU time	4.22 seconds
Started	Apr 30 03:47:07 PM PDT 24
Finished	Apr 30 03:47:11 PM PDT 24
Peak memory	241664 kb
Host	smart-0863dd0a-58eb-442f-a417-d5b65591be6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2191981416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.2191981416
Directory	/workspace/105.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/106.otp_ctrl_init_fail.1895948470
Short name	T653
Test name
Test status
Simulation time	307785651 ps
CPU time	4.26 seconds
Started	Apr 30 03:47:08 PM PDT 24
Finished	Apr 30 03:47:12 PM PDT 24
Peak memory	241344 kb
Host	smart-c78f1e76-d9ed-4075-8c97-17c6cf78c85a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1895948470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1895948470
Directory	/workspace/106.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.3152032573
Short name	T1193
Test name
Test status
Simulation time	415171594 ps
CPU time	3.9 seconds
Started	Apr 30 03:47:06 PM PDT 24
Finished	Apr 30 03:47:11 PM PDT 24
Peak memory	241640 kb
Host	smart-ce699ee2-57d1-4824-b8eb-eed8d75a4ff5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152032573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.3152032573
Directory	/workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/107.otp_ctrl_init_fail.429004599
Short name	T1096
Test name
Test status
Simulation time	223288092 ps
CPU time	4.21 seconds
Started	Apr 30 03:47:08 PM PDT 24
Finished	Apr 30 03:47:13 PM PDT 24
Peak memory	241412 kb
Host	smart-aa0409b5-e16f-4b0b-ac62-b75940f5d0eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=429004599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.429004599
Directory	/workspace/107.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.3353835903
Short name	T869
Test name
Test status
Simulation time	1363247230 ps
CPU time	12.52 seconds
Started	Apr 30 03:47:07 PM PDT 24
Finished	Apr 30 03:47:20 PM PDT 24
Peak memory	241680 kb
Host	smart-7857a908-0478-44da-aade-5d7c8d758613
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3353835903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.3353835903
Directory	/workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/108.otp_ctrl_init_fail.2164782983
Short name	T595
Test name
Test status
Simulation time	188952166 ps
CPU time	4.49 seconds
Started	Apr 30 03:47:09 PM PDT 24
Finished	Apr 30 03:47:14 PM PDT 24
Peak memory	241780 kb
Host	smart-3637bfb5-72d9-4ee1-8f46-aead58ade0ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2164782983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.2164782983
Directory	/workspace/108.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.2971323548
Short name	T902
Test name
Test status
Simulation time	901115873 ps
CPU time	18.94 seconds
Started	Apr 30 03:47:08 PM PDT 24
Finished	Apr 30 03:47:27 PM PDT 24
Peak memory	241476 kb
Host	smart-5b8f74ed-07fb-4ca6-8df0-fe3b0d419c9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2971323548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.2971323548
Directory	/workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/109.otp_ctrl_init_fail.2899128702
Short name	T85
Test name
Test status
Simulation time	1849656297 ps
CPU time	6.08 seconds
Started	Apr 30 03:47:07 PM PDT 24
Finished	Apr 30 03:47:14 PM PDT 24
Peak memory	241524 kb
Host	smart-378b96bb-2af1-466a-bb6a-d1f1b4cc0727
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899128702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.2899128702
Directory	/workspace/109.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.1543862809
Short name	T287
Test name
Test status
Simulation time	1340840104 ps
CPU time	3.91 seconds
Started	Apr 30 03:47:08 PM PDT 24
Finished	Apr 30 03:47:13 PM PDT 24
Peak memory	241740 kb
Host	smart-74f7a9ab-720d-417d-a92b-b34e505561fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1543862809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.1543862809
Directory	/workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/11.otp_ctrl_alert_test.484818853
Short name	T724
Test name
Test status
Simulation time	891834010 ps
CPU time	1.77 seconds
Started	Apr 30 03:41:31 PM PDT 24
Finished	Apr 30 03:41:33 PM PDT 24
Peak memory	240060 kb
Host	smart-c901dc4a-5908-41f2-bcc2-fe98516d3472
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484818853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.484818853
Directory	/workspace/11.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.otp_ctrl_check_fail.2952419744
Short name	T136
Test name
Test status
Simulation time	4799307926 ps
CPU time	39.99 seconds
Started	Apr 30 03:41:30 PM PDT 24
Finished	Apr 30 03:42:10 PM PDT 24
Peak memory	248160 kb
Host	smart-04b1e9f6-cf56-47cb-af36-b9e77445b50b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2952419744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2952419744
Directory	/workspace/11.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/11.otp_ctrl_dai_errs.684451681
Short name	T425
Test name
Test status
Simulation time	776617416 ps
CPU time	22.83 seconds
Started	Apr 30 03:41:32 PM PDT 24
Finished	Apr 30 03:41:55 PM PDT 24
Peak memory	241280 kb
Host	smart-55498454-918d-43df-b419-9a91966615f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=684451681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.684451681
Directory	/workspace/11.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/11.otp_ctrl_dai_lock.1587481465
Short name	T158
Test name
Test status
Simulation time	167811011 ps
CPU time	5.08 seconds
Started	Apr 30 03:41:30 PM PDT 24
Finished	Apr 30 03:41:36 PM PDT 24
Peak memory	241264 kb
Host	smart-2615958a-dbce-4c47-b94a-9fea411e91f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1587481465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.1587481465
Directory	/workspace/11.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/11.otp_ctrl_init_fail.3418826827
Short name	T24
Test name
Test status
Simulation time	2476311777 ps
CPU time	5.7 seconds
Started	Apr 30 03:41:25 PM PDT 24
Finished	Apr 30 03:41:32 PM PDT 24
Peak memory	241876 kb
Host	smart-144fc286-f012-4c4d-9136-86e14de77fd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3418826827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.3418826827
Directory	/workspace/11.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/11.otp_ctrl_macro_errs.1369755429
Short name	T938
Test name
Test status
Simulation time	1906941013 ps
CPU time	20.82 seconds
Started	Apr 30 03:41:31 PM PDT 24
Finished	Apr 30 03:41:52 PM PDT 24
Peak memory	243000 kb
Host	smart-77dd6903-221f-40ec-8caa-97b2d9ed4011
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1369755429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.1369755429
Directory	/workspace/11.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/11.otp_ctrl_parallel_key_req.682122568
Short name	T779
Test name
Test status
Simulation time	2990575944 ps
CPU time	37.7 seconds
Started	Apr 30 03:41:32 PM PDT 24
Finished	Apr 30 03:42:10 PM PDT 24
Peak memory	241456 kb
Host	smart-4afe8eaa-103c-4eba-89c7-074346529b06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=682122568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.682122568
Directory	/workspace/11.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.3841371348
Short name	T476
Test name
Test status
Simulation time	2732022777 ps
CPU time	6.36 seconds
Started	Apr 30 03:41:27 PM PDT 24
Finished	Apr 30 03:41:34 PM PDT 24
Peak memory	241240 kb
Host	smart-02060bfe-a90e-4513-91d8-392bb4b72e69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3841371348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.3841371348
Directory	/workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/11.otp_ctrl_parallel_lc_req.1726367550
Short name	T7
Test name
Test status
Simulation time	619160337 ps
CPU time	7.95 seconds
Started	Apr 30 03:41:27 PM PDT 24
Finished	Apr 30 03:41:35 PM PDT 24
Peak memory	247836 kb
Host	smart-1eeeda16-5567-4a88-a9f4-e50ec99dd67e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1726367550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.1726367550
Directory	/workspace/11.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/11.otp_ctrl_regwen.1620091536
Short name	T852
Test name
Test status
Simulation time	279325833 ps
CPU time	5.46 seconds
Started	Apr 30 03:41:34 PM PDT 24
Finished	Apr 30 03:41:40 PM PDT 24
Peak memory	241396 kb
Host	smart-9a7aa376-5540-4f88-a759-df165f31c1b4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1620091536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.1620091536
Directory	/workspace/11.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/11.otp_ctrl_smoke.3315920784
Short name	T1115
Test name
Test status
Simulation time	467291985 ps
CPU time	6.31 seconds
Started	Apr 30 03:41:24 PM PDT 24
Finished	Apr 30 03:41:31 PM PDT 24
Peak memory	241144 kb
Host	smart-66b46985-453e-4d00-b36d-fdbd8d56ce68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3315920784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.3315920784
Directory	/workspace/11.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.otp_ctrl_stress_all.1253124540
Short name	T532
Test name
Test status
Simulation time	18870301311 ps
CPU time	221.51 seconds
Started	Apr 30 03:41:30 PM PDT 24
Finished	Apr 30 03:45:12 PM PDT 24
Peak memory	256276 kb
Host	smart-e1ca169f-1ec1-4076-a59d-925a312bd4fe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253124540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all .1253124540
Directory	/workspace/11.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.1718143609
Short name	T1006
Test name
Test status
Simulation time	80032993901 ps
CPU time	2009.61 seconds
Started	Apr 30 03:41:30 PM PDT 24
Finished	Apr 30 04:15:00 PM PDT 24
Peak memory	322224 kb
Host	smart-fa7b3029-0b7a-4d0a-82cd-28312823d612
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718143609 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.1718143609
Directory	/workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.otp_ctrl_test_access.1666759892
Short name	T551
Test name
Test status
Simulation time	421725682 ps
CPU time	5.28 seconds
Started	Apr 30 03:41:30 PM PDT 24
Finished	Apr 30 03:41:36 PM PDT 24
Peak memory	241208 kb
Host	smart-7fb8e207-87fb-442e-beda-ab784710c1e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666759892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.1666759892
Directory	/workspace/11.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/110.otp_ctrl_init_fail.2022000055
Short name	T950
Test name
Test status
Simulation time	99487436 ps
CPU time	3.96 seconds
Started	Apr 30 03:47:07 PM PDT 24
Finished	Apr 30 03:47:12 PM PDT 24
Peak memory	241404 kb
Host	smart-f672617c-2e32-4d5d-8f39-743d2446a52e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2022000055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2022000055
Directory	/workspace/110.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.464644460
Short name	T576
Test name
Test status
Simulation time	926210655 ps
CPU time	14.67 seconds
Started	Apr 30 03:47:07 PM PDT 24
Finished	Apr 30 03:47:23 PM PDT 24
Peak memory	241220 kb
Host	smart-a7ecd4cb-4f6c-4411-ba5b-e783980048a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=464644460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.464644460
Directory	/workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/111.otp_ctrl_init_fail.672045748
Short name	T654
Test name
Test status
Simulation time	214121840 ps
CPU time	4.1 seconds
Started	Apr 30 03:47:07 PM PDT 24
Finished	Apr 30 03:47:12 PM PDT 24
Peak memory	241380 kb
Host	smart-0adc6227-8312-4774-857f-406cbe9d0df5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=672045748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.672045748
Directory	/workspace/111.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.3715852992
Short name	T1172
Test name
Test status
Simulation time	551519241 ps
CPU time	7.25 seconds
Started	Apr 30 03:47:10 PM PDT 24
Finished	Apr 30 03:47:17 PM PDT 24
Peak memory	241264 kb
Host	smart-84118bdf-aa26-4717-a5c9-bed39e29af75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3715852992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.3715852992
Directory	/workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/112.otp_ctrl_init_fail.2105264658
Short name	T720
Test name
Test status
Simulation time	2401600616 ps
CPU time	6.66 seconds
Started	Apr 30 03:47:12 PM PDT 24
Finished	Apr 30 03:47:19 PM PDT 24
Peak memory	241620 kb
Host	smart-8eeacf54-92f4-41bb-95fd-285aa116ba18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2105264658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.2105264658
Directory	/workspace/112.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.3003371695
Short name	T718
Test name
Test status
Simulation time	620835217 ps
CPU time	10.44 seconds
Started	Apr 30 03:47:13 PM PDT 24
Finished	Apr 30 03:47:24 PM PDT 24
Peak memory	241228 kb
Host	smart-1ef43950-8ea3-4733-8716-78a7d4388bab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003371695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3003371695
Directory	/workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/113.otp_ctrl_init_fail.4051803619
Short name	T813
Test name
Test status
Simulation time	1898211364 ps
CPU time	4.37 seconds
Started	Apr 30 03:47:12 PM PDT 24
Finished	Apr 30 03:47:17 PM PDT 24
Peak memory	241764 kb
Host	smart-81ac3090-56e8-4b18-9669-d7bf6dad80ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4051803619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.4051803619
Directory	/workspace/113.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.945022450
Short name	T1005
Test name
Test status
Simulation time	333224008 ps
CPU time	12.95 seconds
Started	Apr 30 03:47:14 PM PDT 24
Finished	Apr 30 03:47:28 PM PDT 24
Peak memory	241064 kb
Host	smart-7743027e-dbfa-4dcd-8f3e-34f9bdf60426
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945022450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.945022450
Directory	/workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/114.otp_ctrl_init_fail.872243903
Short name	T1056
Test name
Test status
Simulation time	223506105 ps
CPU time	3.63 seconds
Started	Apr 30 03:47:15 PM PDT 24
Finished	Apr 30 03:47:19 PM PDT 24
Peak memory	241280 kb
Host	smart-2747c650-e33a-4d19-8fc1-4a160ab774a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872243903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.872243903
Directory	/workspace/114.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.944500843
Short name	T620
Test name
Test status
Simulation time	114543654 ps
CPU time	4.55 seconds
Started	Apr 30 03:47:13 PM PDT 24
Finished	Apr 30 03:47:18 PM PDT 24
Peak memory	241268 kb
Host	smart-23600cce-f410-40f9-94dc-52fa5aca0904
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=944500843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.944500843
Directory	/workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/115.otp_ctrl_init_fail.1460618037
Short name	T831
Test name
Test status
Simulation time	140700681 ps
CPU time	4.69 seconds
Started	Apr 30 03:47:12 PM PDT 24
Finished	Apr 30 03:47:17 PM PDT 24
Peak memory	241292 kb
Host	smart-2228f14d-c28d-4577-bdea-1ae5af7da2f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1460618037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.1460618037
Directory	/workspace/115.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.1798727003
Short name	T732
Test name
Test status
Simulation time	174310680 ps
CPU time	4.55 seconds
Started	Apr 30 03:47:13 PM PDT 24
Finished	Apr 30 03:47:18 PM PDT 24
Peak memory	241152 kb
Host	smart-fc7d3b13-eef5-47fa-b573-863168648d0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798727003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.1798727003
Directory	/workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/116.otp_ctrl_init_fail.1164176929
Short name	T639
Test name
Test status
Simulation time	157086184 ps
CPU time	4.66 seconds
Started	Apr 30 03:47:15 PM PDT 24
Finished	Apr 30 03:47:20 PM PDT 24
Peak memory	241680 kb
Host	smart-213dbb99-b1f3-462b-a999-16b4e0d5dee7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1164176929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.1164176929
Directory	/workspace/116.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.4204770620
Short name	T901
Test name
Test status
Simulation time	208430477 ps
CPU time	5.93 seconds
Started	Apr 30 03:47:21 PM PDT 24
Finished	Apr 30 03:47:27 PM PDT 24
Peak memory	241332 kb
Host	smart-4d46bb0f-9efc-4ee7-9703-8d247ce27bd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4204770620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.4204770620
Directory	/workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/117.otp_ctrl_init_fail.3230215778
Short name	T652
Test name
Test status
Simulation time	123879980 ps
CPU time	3.12 seconds
Started	Apr 30 03:47:22 PM PDT 24
Finished	Apr 30 03:47:25 PM PDT 24
Peak memory	241432 kb
Host	smart-118b18f2-db03-440d-b281-5d4b94f2e6a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3230215778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.3230215778
Directory	/workspace/117.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.3521317336
Short name	T885
Test name
Test status
Simulation time	93766583 ps
CPU time	2.67 seconds
Started	Apr 30 03:47:22 PM PDT 24
Finished	Apr 30 03:47:25 PM PDT 24
Peak memory	241888 kb
Host	smart-94f484dd-abd3-4651-87eb-efbdf6ca0c56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521317336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3521317336
Directory	/workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/118.otp_ctrl_init_fail.3317598064
Short name	T89
Test name
Test status
Simulation time	2606115601 ps
CPU time	5.09 seconds
Started	Apr 30 03:47:24 PM PDT 24
Finished	Apr 30 03:47:30 PM PDT 24
Peak memory	241732 kb
Host	smart-54cbf3e9-6d0f-4f16-b1f3-e84df9dd7c7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317598064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.3317598064
Directory	/workspace/118.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.3396941676
Short name	T974
Test name
Test status
Simulation time	350126314 ps
CPU time	9.79 seconds
Started	Apr 30 03:47:22 PM PDT 24
Finished	Apr 30 03:47:32 PM PDT 24
Peak memory	241436 kb
Host	smart-213e8364-5da2-4b0a-8eed-b15f8907d607
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3396941676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.3396941676
Directory	/workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/119.otp_ctrl_init_fail.407867123
Short name	T331
Test name
Test status
Simulation time	130155286 ps
CPU time	3.55 seconds
Started	Apr 30 03:47:21 PM PDT 24
Finished	Apr 30 03:47:25 PM PDT 24
Peak memory	241664 kb
Host	smart-d53a934c-5008-4ad9-8722-b5a0fb1b1614
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407867123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.407867123
Directory	/workspace/119.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.1233489125
Short name	T577
Test name
Test status
Simulation time	362778168 ps
CPU time	5.82 seconds
Started	Apr 30 03:47:22 PM PDT 24
Finished	Apr 30 03:47:28 PM PDT 24
Peak memory	241640 kb
Host	smart-332a29c1-1d3c-4135-a569-9f6077e26371
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233489125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.1233489125
Directory	/workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/12.otp_ctrl_alert_test.1782912310
Short name	T351
Test name
Test status
Simulation time	777588258 ps
CPU time	2.32 seconds
Started	Apr 30 03:41:40 PM PDT 24
Finished	Apr 30 03:41:43 PM PDT 24
Peak memory	240204 kb
Host	smart-1aa10ea8-3cc1-4faf-8095-0ce5dc2c3f62
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782912310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.1782912310
Directory	/workspace/12.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.otp_ctrl_dai_errs.1388186938
Short name	T549
Test name
Test status
Simulation time	26545260873 ps
CPU time	52.77 seconds
Started	Apr 30 03:41:36 PM PDT 24
Finished	Apr 30 03:42:29 PM PDT 24
Peak memory	257948 kb
Host	smart-bfdf77b6-e1b7-4684-a58b-4b2c215278f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1388186938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.1388186938
Directory	/workspace/12.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/12.otp_ctrl_dai_lock.2973478596
Short name	T435
Test name
Test status
Simulation time	306703186 ps
CPU time	7.6 seconds
Started	Apr 30 03:41:36 PM PDT 24
Finished	Apr 30 03:41:44 PM PDT 24
Peak memory	241388 kb
Host	smart-b4994db7-2555-49f2-914c-d009f5c43748
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2973478596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.2973478596
Directory	/workspace/12.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/12.otp_ctrl_init_fail.736445015
Short name	T444
Test name
Test status
Simulation time	2038433980 ps
CPU time	5.07 seconds
Started	Apr 30 03:41:33 PM PDT 24
Finished	Apr 30 03:41:39 PM PDT 24
Peak memory	241796 kb
Host	smart-df013d5f-3980-4ae2-aa0d-2b1b45fa4e46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736445015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.736445015
Directory	/workspace/12.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/12.otp_ctrl_macro_errs.3926756754
Short name	T1082
Test name
Test status
Simulation time	3322667075 ps
CPU time	22.98 seconds
Started	Apr 30 03:41:35 PM PDT 24
Finished	Apr 30 03:41:59 PM PDT 24
Peak memory	245964 kb
Host	smart-d0b90444-febb-4fe1-930c-42d1702320d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926756754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.3926756754
Directory	/workspace/12.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/12.otp_ctrl_parallel_key_req.617531796
Short name	T827
Test name
Test status
Simulation time	1521055891 ps
CPU time	21.19 seconds
Started	Apr 30 03:41:40 PM PDT 24
Finished	Apr 30 03:42:02 PM PDT 24
Peak memory	241684 kb
Host	smart-b2808e35-a00f-4609-b1ea-cc6ec25ea862
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=617531796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.617531796
Directory	/workspace/12.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.436279794
Short name	T464
Test name
Test status
Simulation time	428711729 ps
CPU time	5.96 seconds
Started	Apr 30 03:41:32 PM PDT 24
Finished	Apr 30 03:41:38 PM PDT 24
Peak memory	245816 kb
Host	smart-c897ed2e-9da0-47db-b88e-595ce38808e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=436279794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.436279794
Directory	/workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/12.otp_ctrl_parallel_lc_req.2185714639
Short name	T182
Test name
Test status
Simulation time	871908186 ps
CPU time	23.73 seconds
Started	Apr 30 03:41:37 PM PDT 24
Finished	Apr 30 03:42:01 PM PDT 24
Peak memory	241208 kb
Host	smart-48f10109-fcbf-4f30-aa4d-ec6339cfd2c8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2185714639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.2185714639
Directory	/workspace/12.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/12.otp_ctrl_smoke.1940913874
Short name	T443
Test name
Test status
Simulation time	1162390798 ps
CPU time	8.6 seconds
Started	Apr 30 03:41:30 PM PDT 24
Finished	Apr 30 03:41:39 PM PDT 24
Peak memory	241556 kb
Host	smart-1834612b-1759-410a-bf08-fd9920a48b84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1940913874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.1940913874
Directory	/workspace/12.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.1613453656
Short name	T334
Test name
Test status
Simulation time	149868721873 ps
CPU time	1159.68 seconds
Started	Apr 30 03:41:42 PM PDT 24
Finished	Apr 30 04:01:03 PM PDT 24
Peak memory	250660 kb
Host	smart-04c2212a-2cd5-4713-8424-44d8ea5952eb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613453656 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.1613453656
Directory	/workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.otp_ctrl_test_access.2470649047
Short name	T674
Test name
Test status
Simulation time	2962215115 ps
CPU time	17.93 seconds
Started	Apr 30 03:41:41 PM PDT 24
Finished	Apr 30 03:41:59 PM PDT 24
Peak memory	242136 kb
Host	smart-3430a45a-7628-460e-b38a-d20aae00fef8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2470649047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.2470649047
Directory	/workspace/12.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/120.otp_ctrl_init_fail.3966490552
Short name	T1125
Test name
Test status
Simulation time	127339074 ps
CPU time	3.65 seconds
Started	Apr 30 03:47:21 PM PDT 24
Finished	Apr 30 03:47:25 PM PDT 24
Peak memory	241352 kb
Host	smart-bdba064a-4a62-46ca-aad1-8afaf5dfa09e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966490552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.3966490552
Directory	/workspace/120.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.2019291851
Short name	T247
Test name
Test status
Simulation time	503415075 ps
CPU time	8.14 seconds
Started	Apr 30 03:47:24 PM PDT 24
Finished	Apr 30 03:47:32 PM PDT 24
Peak memory	241724 kb
Host	smart-249dd664-3794-43dc-b4af-e0fd72e92665
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2019291851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.2019291851
Directory	/workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.3990971354
Short name	T509
Test name
Test status
Simulation time	104241824 ps
CPU time	2.92 seconds
Started	Apr 30 03:47:24 PM PDT 24
Finished	Apr 30 03:47:27 PM PDT 24
Peak memory	241352 kb
Host	smart-6bfaf238-e936-4839-b8a7-b8a233c5a218
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3990971354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.3990971354
Directory	/workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/122.otp_ctrl_init_fail.2422773670
Short name	T741
Test name
Test status
Simulation time	242509556 ps
CPU time	5.16 seconds
Started	Apr 30 03:47:23 PM PDT 24
Finished	Apr 30 03:47:28 PM PDT 24
Peak memory	241452 kb
Host	smart-7043d50d-b60c-461a-93f9-274fd7c5df2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2422773670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.2422773670
Directory	/workspace/122.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.1382345710
Short name	T1108
Test name
Test status
Simulation time	1423980749 ps
CPU time	15.75 seconds
Started	Apr 30 03:47:23 PM PDT 24
Finished	Apr 30 03:47:39 PM PDT 24
Peak memory	241332 kb
Host	smart-131e373b-3869-46a1-84ae-7ea3e24bacb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382345710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.1382345710
Directory	/workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.3757079251
Short name	T399
Test name
Test status
Simulation time	282989167 ps
CPU time	14.21 seconds
Started	Apr 30 03:47:22 PM PDT 24
Finished	Apr 30 03:47:37 PM PDT 24
Peak memory	241112 kb
Host	smart-7a60bec4-b9a8-4857-a767-6397878afa4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3757079251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.3757079251
Directory	/workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.1840767287
Short name	T93
Test name
Test status
Simulation time	334551585 ps
CPU time	15.7 seconds
Started	Apr 30 03:47:20 PM PDT 24
Finished	Apr 30 03:47:37 PM PDT 24
Peak memory	241560 kb
Host	smart-2ba76f82-ec7f-42da-b114-0859088c444a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1840767287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.1840767287
Directory	/workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/125.otp_ctrl_init_fail.1433609260
Short name	T1149
Test name
Test status
Simulation time	148616021 ps
CPU time	3.65 seconds
Started	Apr 30 03:47:24 PM PDT 24
Finished	Apr 30 03:47:28 PM PDT 24
Peak memory	241668 kb
Host	smart-cddbfa59-9fb5-47b9-8e6b-c92c0d359c90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1433609260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.1433609260
Directory	/workspace/125.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.40851835
Short name	T879
Test name
Test status
Simulation time	446026802 ps
CPU time	7.53 seconds
Started	Apr 30 03:47:19 PM PDT 24
Finished	Apr 30 03:47:27 PM PDT 24
Peak memory	241792 kb
Host	smart-9bf37d62-7d51-4336-b3c8-bee138466d52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40851835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.40851835
Directory	/workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/126.otp_ctrl_init_fail.3481467430
Short name	T1064
Test name
Test status
Simulation time	457077011 ps
CPU time	4.69 seconds
Started	Apr 30 03:47:21 PM PDT 24
Finished	Apr 30 03:47:26 PM PDT 24
Peak memory	241672 kb
Host	smart-feb12b91-c32c-4de1-b340-2b3815776287
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3481467430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3481467430
Directory	/workspace/126.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.2132366992
Short name	T1070
Test name
Test status
Simulation time	234528680 ps
CPU time	5.6 seconds
Started	Apr 30 03:47:28 PM PDT 24
Finished	Apr 30 03:47:34 PM PDT 24
Peak memory	241432 kb
Host	smart-a4a131e4-712d-402e-8403-0ddb280a4748
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132366992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.2132366992
Directory	/workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/127.otp_ctrl_init_fail.2919793712
Short name	T1050
Test name
Test status
Simulation time	179681638 ps
CPU time	5.11 seconds
Started	Apr 30 03:47:28 PM PDT 24
Finished	Apr 30 03:47:34 PM PDT 24
Peak memory	241396 kb
Host	smart-a57384d4-230a-4b64-8f69-4befd57fc82d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2919793712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.2919793712
Directory	/workspace/127.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.2402353341
Short name	T804
Test name
Test status
Simulation time	213349205 ps
CPU time	3.94 seconds
Started	Apr 30 03:47:29 PM PDT 24
Finished	Apr 30 03:47:33 PM PDT 24
Peak memory	241372 kb
Host	smart-93b0dd5b-10f2-4557-86bd-a96bb74c373f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2402353341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.2402353341
Directory	/workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/128.otp_ctrl_init_fail.746055290
Short name	T1103
Test name
Test status
Simulation time	2568134537 ps
CPU time	7.35 seconds
Started	Apr 30 03:47:26 PM PDT 24
Finished	Apr 30 03:47:34 PM PDT 24
Peak memory	241444 kb
Host	smart-5e809418-418b-4ad3-8293-3f1d0721a43c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=746055290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.746055290
Directory	/workspace/128.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.3947526766
Short name	T571
Test name
Test status
Simulation time	140025515 ps
CPU time	6.45 seconds
Started	Apr 30 03:47:28 PM PDT 24
Finished	Apr 30 03:47:36 PM PDT 24
Peak memory	241736 kb
Host	smart-99ad33e4-90d1-4e33-b741-b08f6f2518ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3947526766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.3947526766
Directory	/workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/129.otp_ctrl_init_fail.2527832328
Short name	T996
Test name
Test status
Simulation time	1846750787 ps
CPU time	7.18 seconds
Started	Apr 30 03:47:29 PM PDT 24
Finished	Apr 30 03:47:37 PM PDT 24
Peak memory	241328 kb
Host	smart-4db6d6cb-116f-4ca4-b69f-bd25614751cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527832328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.2527832328
Directory	/workspace/129.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.4003602777
Short name	T282
Test name
Test status
Simulation time	328191982 ps
CPU time	4.66 seconds
Started	Apr 30 03:47:29 PM PDT 24
Finished	Apr 30 03:47:35 PM PDT 24
Peak memory	241356 kb
Host	smart-b3385e6d-e684-4de6-b46d-f56e92b18d0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003602777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.4003602777
Directory	/workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/13.otp_ctrl_alert_test.3181226114
Short name	T335
Test name
Test status
Simulation time	77602062 ps
CPU time	1.59 seconds
Started	Apr 30 03:41:45 PM PDT 24
Finished	Apr 30 03:41:47 PM PDT 24
Peak memory	240196 kb
Host	smart-32378c99-7112-4836-89ee-e169643145fb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181226114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.3181226114
Directory	/workspace/13.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.otp_ctrl_check_fail.3494180936
Short name	T28
Test name
Test status
Simulation time	1436515629 ps
CPU time	22.84 seconds
Started	Apr 30 03:41:47 PM PDT 24
Finished	Apr 30 03:42:10 PM PDT 24
Peak memory	248036 kb
Host	smart-8ad3fd2f-f70e-40bd-835c-c66490123f63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494180936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.3494180936
Directory	/workspace/13.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/13.otp_ctrl_dai_errs.409519245
Short name	T749
Test name
Test status
Simulation time	2163947809 ps
CPU time	34.81 seconds
Started	Apr 30 03:41:44 PM PDT 24
Finished	Apr 30 03:42:20 PM PDT 24
Peak memory	242144 kb
Host	smart-d7ad02d8-e3ae-4bc9-9ea0-03a21118961e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=409519245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.409519245
Directory	/workspace/13.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/13.otp_ctrl_dai_lock.3573955675
Short name	T404
Test name
Test status
Simulation time	1399338303 ps
CPU time	17.8 seconds
Started	Apr 30 03:41:45 PM PDT 24
Finished	Apr 30 03:42:03 PM PDT 24
Peak memory	241344 kb
Host	smart-805d6eed-98c6-4936-b76a-58091fe444bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3573955675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.3573955675
Directory	/workspace/13.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/13.otp_ctrl_init_fail.2766808277
Short name	T116
Test name
Test status
Simulation time	153321765 ps
CPU time	3.39 seconds
Started	Apr 30 03:41:46 PM PDT 24
Finished	Apr 30 03:41:50 PM PDT 24
Peak memory	241280 kb
Host	smart-da201fba-9b9a-4510-872c-ee0f87fea369
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2766808277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.2766808277
Directory	/workspace/13.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/13.otp_ctrl_macro_errs.2354415408
Short name	T1013
Test name
Test status
Simulation time	407803459 ps
CPU time	9.61 seconds
Started	Apr 30 03:41:47 PM PDT 24
Finished	Apr 30 03:41:57 PM PDT 24
Peak memory	241820 kb
Host	smart-d56392a4-c9b0-4b9a-9f70-84141dce79de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354415408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.2354415408
Directory	/workspace/13.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/13.otp_ctrl_parallel_key_req.922025767
Short name	T928
Test name
Test status
Simulation time	2628958070 ps
CPU time	29.81 seconds
Started	Apr 30 03:41:45 PM PDT 24
Finished	Apr 30 03:42:16 PM PDT 24
Peak memory	242028 kb
Host	smart-e7a89348-3f5d-4bb0-8dc0-7def5f4aa2f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=922025767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.922025767
Directory	/workspace/13.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.32672530
Short name	T244
Test name
Test status
Simulation time	2045187790 ps
CPU time	27.59 seconds
Started	Apr 30 03:41:48 PM PDT 24
Finished	Apr 30 03:42:16 PM PDT 24
Peak memory	241224 kb
Host	smart-bc3fb7ad-11e5-4aea-a40d-5fe95ee6c4a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32672530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.32672530
Directory	/workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/13.otp_ctrl_parallel_lc_req.2942827077
Short name	T1017
Test name
Test status
Simulation time	1287676716 ps
CPU time	17.36 seconds
Started	Apr 30 03:41:47 PM PDT 24
Finished	Apr 30 03:42:05 PM PDT 24
Peak memory	247876 kb
Host	smart-cec10bc7-7b8f-428c-8498-3bc1ca411e78
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2942827077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.2942827077
Directory	/workspace/13.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/13.otp_ctrl_regwen.3935508077
Short name	T387
Test name
Test status
Simulation time	743724991 ps
CPU time	7.12 seconds
Started	Apr 30 03:41:45 PM PDT 24
Finished	Apr 30 03:41:53 PM PDT 24
Peak memory	241352 kb
Host	smart-474ac4e8-2186-4822-9789-df8439809c12
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3935508077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.3935508077
Directory	/workspace/13.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/13.otp_ctrl_smoke.2793813431
Short name	T365
Test name
Test status
Simulation time	784463177 ps
CPU time	6.68 seconds
Started	Apr 30 03:41:42 PM PDT 24
Finished	Apr 30 03:41:49 PM PDT 24
Peak memory	241340 kb
Host	smart-943d4a58-7a42-4856-a264-cbd9eb1ecc7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2793813431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.2793813431
Directory	/workspace/13.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.otp_ctrl_test_access.1487293510
Short name	T670
Test name
Test status
Simulation time	283681153 ps
CPU time	6.81 seconds
Started	Apr 30 03:41:46 PM PDT 24
Finished	Apr 30 03:41:54 PM PDT 24
Peak memory	241328 kb
Host	smart-aff49192-ac78-4eb6-83af-3346a8a1f116
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1487293510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.1487293510
Directory	/workspace/13.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/130.otp_ctrl_init_fail.599780767
Short name	T47
Test name
Test status
Simulation time	325841099 ps
CPU time	3.83 seconds
Started	Apr 30 03:47:29 PM PDT 24
Finished	Apr 30 03:47:33 PM PDT 24
Peak memory	241304 kb
Host	smart-80f2e2ec-f508-4462-8f3e-0672a2f9fa24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=599780767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.599780767
Directory	/workspace/130.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.1128431205
Short name	T909
Test name
Test status
Simulation time	232618246 ps
CPU time	6.04 seconds
Started	Apr 30 03:47:30 PM PDT 24
Finished	Apr 30 03:47:37 PM PDT 24
Peak memory	241328 kb
Host	smart-474e9a24-4d21-4ff2-9447-e6162a57bf57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1128431205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.1128431205
Directory	/workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/131.otp_ctrl_init_fail.163186665
Short name	T721
Test name
Test status
Simulation time	163418326 ps
CPU time	4.27 seconds
Started	Apr 30 03:47:27 PM PDT 24
Finished	Apr 30 03:47:32 PM PDT 24
Peak memory	241412 kb
Host	smart-46a0fc73-53b9-4948-a5f8-652bfffefefd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=163186665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.163186665
Directory	/workspace/131.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.685539390
Short name	T967
Test name
Test status
Simulation time	1578225486 ps
CPU time	19.08 seconds
Started	Apr 30 03:47:27 PM PDT 24
Finished	Apr 30 03:47:46 PM PDT 24
Peak memory	241352 kb
Host	smart-543c03a9-cff3-4c77-92a2-5e621bc5b4d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=685539390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.685539390
Directory	/workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/132.otp_ctrl_init_fail.3501133211
Short name	T1088
Test name
Test status
Simulation time	208347201 ps
CPU time	3.7 seconds
Started	Apr 30 03:47:30 PM PDT 24
Finished	Apr 30 03:47:34 PM PDT 24
Peak memory	241572 kb
Host	smart-38f62359-14d9-492c-8c10-e8e735a4d9ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501133211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.3501133211
Directory	/workspace/132.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.1007349435
Short name	T952
Test name
Test status
Simulation time	2279196992 ps
CPU time	8.74 seconds
Started	Apr 30 03:47:27 PM PDT 24
Finished	Apr 30 03:47:36 PM PDT 24
Peak memory	241344 kb
Host	smart-b7655ae0-189d-4ff5-8fae-65b2e5a5ca84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1007349435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.1007349435
Directory	/workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/133.otp_ctrl_init_fail.573306106
Short name	T1023
Test name
Test status
Simulation time	1754732140 ps
CPU time	4.43 seconds
Started	Apr 30 03:47:27 PM PDT 24
Finished	Apr 30 03:47:32 PM PDT 24
Peak memory	241732 kb
Host	smart-ba699a0a-4439-416a-866d-7d31ee01e802
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=573306106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.573306106
Directory	/workspace/133.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.3336592765
Short name	T966
Test name
Test status
Simulation time	398968444 ps
CPU time	5 seconds
Started	Apr 30 03:47:29 PM PDT 24
Finished	Apr 30 03:47:34 PM PDT 24
Peak memory	241356 kb
Host	smart-449d912c-ffe5-4652-98c9-b3db387a3cd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3336592765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.3336592765
Directory	/workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/134.otp_ctrl_init_fail.3040109549
Short name	T40
Test name
Test status
Simulation time	2369275671 ps
CPU time	5.36 seconds
Started	Apr 30 03:47:35 PM PDT 24
Finished	Apr 30 03:47:41 PM PDT 24
Peak memory	241452 kb
Host	smart-af159e69-a2fd-41f0-9610-56d22af18f82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040109549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.3040109549
Directory	/workspace/134.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.826571579
Short name	T982
Test name
Test status
Simulation time	133936747 ps
CPU time	2.99 seconds
Started	Apr 30 03:47:36 PM PDT 24
Finished	Apr 30 03:47:39 PM PDT 24
Peak memory	241184 kb
Host	smart-5ca01225-9dd8-4c9c-bae2-dd67b9529a54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826571579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.826571579
Directory	/workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/135.otp_ctrl_init_fail.1874880881
Short name	T49
Test name
Test status
Simulation time	2252269416 ps
CPU time	4.91 seconds
Started	Apr 30 03:47:34 PM PDT 24
Finished	Apr 30 03:47:39 PM PDT 24
Peak memory	241560 kb
Host	smart-6dc8fab5-251a-45aa-8ee7-458b87e889df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1874880881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.1874880881
Directory	/workspace/135.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.3821932125
Short name	T504
Test name
Test status
Simulation time	292874590 ps
CPU time	10.44 seconds
Started	Apr 30 03:47:35 PM PDT 24
Finished	Apr 30 03:47:46 PM PDT 24
Peak memory	241368 kb
Host	smart-f53c297b-748d-4203-aa1d-9a5e05dfd2a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3821932125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.3821932125
Directory	/workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.2830229890
Short name	T111
Test name
Test status
Simulation time	229666588 ps
CPU time	4.92 seconds
Started	Apr 30 03:47:35 PM PDT 24
Finished	Apr 30 03:47:40 PM PDT 24
Peak memory	241368 kb
Host	smart-37aff98b-338d-42dd-99ea-6d445949f660
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2830229890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.2830229890
Directory	/workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/137.otp_ctrl_init_fail.3835879281
Short name	T704
Test name
Test status
Simulation time	658543460 ps
CPU time	5.08 seconds
Started	Apr 30 03:47:38 PM PDT 24
Finished	Apr 30 03:47:43 PM PDT 24
Peak memory	241400 kb
Host	smart-60b0b732-1dc6-4666-9c89-c2c5f378fbf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3835879281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.3835879281
Directory	/workspace/137.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.2158366997
Short name	T267
Test name
Test status
Simulation time	472254759 ps
CPU time	7.13 seconds
Started	Apr 30 03:47:34 PM PDT 24
Finished	Apr 30 03:47:42 PM PDT 24
Peak memory	248044 kb
Host	smart-a59e61fa-c773-4f0c-b33d-7fdce99a0a1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2158366997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.2158366997
Directory	/workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/138.otp_ctrl_init_fail.1654438122
Short name	T634
Test name
Test status
Simulation time	2813185752 ps
CPU time	6.47 seconds
Started	Apr 30 03:47:34 PM PDT 24
Finished	Apr 30 03:47:41 PM PDT 24
Peak memory	241500 kb
Host	smart-96f38b1b-2ac7-4877-9d92-883a4bb01bbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654438122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.1654438122
Directory	/workspace/138.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.673344326
Short name	T262
Test name
Test status
Simulation time	167358249 ps
CPU time	4.62 seconds
Started	Apr 30 03:47:45 PM PDT 24
Finished	Apr 30 03:47:50 PM PDT 24
Peak memory	241240 kb
Host	smart-3ca64eed-46b4-45d9-ad11-640859889dc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=673344326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.673344326
Directory	/workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/139.otp_ctrl_init_fail.2232636992
Short name	T55
Test name
Test status
Simulation time	515085515 ps
CPU time	3.59 seconds
Started	Apr 30 03:47:42 PM PDT 24
Finished	Apr 30 03:47:46 PM PDT 24
Peak memory	241688 kb
Host	smart-10347d9b-2869-47d6-83d1-0a7b906ae638
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2232636992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2232636992
Directory	/workspace/139.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.3550698994
Short name	T487
Test name
Test status
Simulation time	509644577 ps
CPU time	7.35 seconds
Started	Apr 30 03:47:40 PM PDT 24
Finished	Apr 30 03:47:48 PM PDT 24
Peak memory	241228 kb
Host	smart-d37fd1c4-0562-43ce-bea6-880b0ef8af6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550698994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.3550698994
Directory	/workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/14.otp_ctrl_alert_test.984527880
Short name	T1155
Test name
Test status
Simulation time	999305810 ps
CPU time	2.93 seconds
Started	Apr 30 03:41:58 PM PDT 24
Finished	Apr 30 03:42:01 PM PDT 24
Peak memory	239788 kb
Host	smart-37725ff1-b698-4e37-a444-3a8eb2116d6e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984527880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.984527880
Directory	/workspace/14.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.otp_ctrl_check_fail.165955349
Short name	T434
Test name
Test status
Simulation time	145161156 ps
CPU time	4.04 seconds
Started	Apr 30 03:41:51 PM PDT 24
Finished	Apr 30 03:41:56 PM PDT 24
Peak memory	241428 kb
Host	smart-1e72eec9-eaa7-4f83-89ff-5e337a5ba463
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165955349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.165955349
Directory	/workspace/14.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/14.otp_ctrl_dai_errs.2988838804
Short name	T243
Test name
Test status
Simulation time	1901479659 ps
CPU time	29.34 seconds
Started	Apr 30 03:41:53 PM PDT 24
Finished	Apr 30 03:42:23 PM PDT 24
Peak memory	241784 kb
Host	smart-0d6fded7-9276-48be-b1b5-94821b05d27f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2988838804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.2988838804
Directory	/workspace/14.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/14.otp_ctrl_dai_lock.422072673
Short name	T746
Test name
Test status
Simulation time	781442922 ps
CPU time	8.9 seconds
Started	Apr 30 03:41:53 PM PDT 24
Finished	Apr 30 03:42:03 PM PDT 24
Peak memory	241340 kb
Host	smart-d9a94d8a-5aeb-4312-b681-8413137fcbc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=422072673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.422072673
Directory	/workspace/14.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/14.otp_ctrl_init_fail.1418265718
Short name	T681
Test name
Test status
Simulation time	103686829 ps
CPU time	3.37 seconds
Started	Apr 30 03:41:52 PM PDT 24
Finished	Apr 30 03:41:56 PM PDT 24
Peak memory	241408 kb
Host	smart-2311348c-8ec6-46fd-bf01-1c96bd4bf182
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1418265718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.1418265718
Directory	/workspace/14.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/14.otp_ctrl_macro_errs.1359983433
Short name	T716
Test name
Test status
Simulation time	531816318 ps
CPU time	9.63 seconds
Started	Apr 30 03:41:54 PM PDT 24
Finished	Apr 30 03:42:04 PM PDT 24
Peak memory	241704 kb
Host	smart-f364b647-2a26-4231-8d3c-49c5e56aacfe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1359983433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1359983433
Directory	/workspace/14.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/14.otp_ctrl_parallel_key_req.3139809437
Short name	T592
Test name
Test status
Simulation time	259338347 ps
CPU time	8.92 seconds
Started	Apr 30 03:41:52 PM PDT 24
Finished	Apr 30 03:42:02 PM PDT 24
Peak memory	241328 kb
Host	smart-c49a3a71-8557-4293-8ead-8dfe0ffdc60e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3139809437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.3139809437
Directory	/workspace/14.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/14.otp_ctrl_parallel_lc_req.3771266781
Short name	T5
Test name
Test status
Simulation time	561335011 ps
CPU time	9.75 seconds
Started	Apr 30 03:41:54 PM PDT 24
Finished	Apr 30 03:42:04 PM PDT 24
Peak memory	241408 kb
Host	smart-fad99153-e976-4d9f-8bf1-f7f68ab19781
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3771266781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.3771266781
Directory	/workspace/14.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/14.otp_ctrl_regwen.997005777
Short name	T151
Test name
Test status
Simulation time	370962931 ps
CPU time	10.21 seconds
Started	Apr 30 03:41:52 PM PDT 24
Finished	Apr 30 03:42:02 PM PDT 24
Peak memory	241352 kb
Host	smart-c4758e42-220f-46dc-897b-5209072c89e1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=997005777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.997005777
Directory	/workspace/14.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/14.otp_ctrl_smoke.1584756686
Short name	T453
Test name
Test status
Simulation time	1025810100 ps
CPU time	9.53 seconds
Started	Apr 30 03:41:45 PM PDT 24
Finished	Apr 30 03:41:56 PM PDT 24
Peak memory	241384 kb
Host	smart-e961bc1d-b075-4a8e-b000-d1c78cee2a6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584756686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.1584756686
Directory	/workspace/14.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.otp_ctrl_test_access.2705471311
Short name	T905
Test name
Test status
Simulation time	2363023361 ps
CPU time	13.71 seconds
Started	Apr 30 03:41:53 PM PDT 24
Finished	Apr 30 03:42:07 PM PDT 24
Peak memory	241484 kb
Host	smart-b45d4380-028b-4599-a879-7bf88fd6b712
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2705471311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.2705471311
Directory	/workspace/14.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.97626241
Short name	T622
Test name
Test status
Simulation time	276691692 ps
CPU time	7.11 seconds
Started	Apr 30 03:47:41 PM PDT 24
Finished	Apr 30 03:47:49 PM PDT 24
Peak memory	241276 kb
Host	smart-fc6b0528-244e-4acd-843d-84b710c89ef5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97626241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.97626241
Directory	/workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/141.otp_ctrl_init_fail.1205906173
Short name	T891
Test name
Test status
Simulation time	435032585 ps
CPU time	4.34 seconds
Started	Apr 30 03:47:41 PM PDT 24
Finished	Apr 30 03:47:46 PM PDT 24
Peak memory	241580 kb
Host	smart-a1bbc171-35d2-4392-b62c-30b4cf255ef5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1205906173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.1205906173
Directory	/workspace/141.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.2502372064
Short name	T516
Test name
Test status
Simulation time	1553948691 ps
CPU time	18.34 seconds
Started	Apr 30 03:47:42 PM PDT 24
Finished	Apr 30 03:48:01 PM PDT 24
Peak memory	241396 kb
Host	smart-7b964ea3-cf36-46da-a9fc-3aafd8b269c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2502372064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.2502372064
Directory	/workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/142.otp_ctrl_init_fail.2758879906
Short name	T470
Test name
Test status
Simulation time	300646279 ps
CPU time	4.15 seconds
Started	Apr 30 03:47:43 PM PDT 24
Finished	Apr 30 03:47:47 PM PDT 24
Peak memory	241316 kb
Host	smart-e15a1563-fdf9-4c3f-8f60-aea3362f6e73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758879906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.2758879906
Directory	/workspace/142.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.506740979
Short name	T710
Test name
Test status
Simulation time	753364350 ps
CPU time	8.35 seconds
Started	Apr 30 03:47:44 PM PDT 24
Finished	Apr 30 03:47:53 PM PDT 24
Peak memory	241636 kb
Host	smart-3c173f4c-f846-4ce5-b33d-da4910aca5be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=506740979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.506740979
Directory	/workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/143.otp_ctrl_init_fail.291203933
Short name	T700
Test name
Test status
Simulation time	263211745 ps
CPU time	3.44 seconds
Started	Apr 30 03:47:41 PM PDT 24
Finished	Apr 30 03:47:45 PM PDT 24
Peak memory	241832 kb
Host	smart-5960689f-a7c0-46a5-98ec-d9c902f30afa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=291203933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.291203933
Directory	/workspace/143.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.1891090316
Short name	T766
Test name
Test status
Simulation time	573002813 ps
CPU time	9.77 seconds
Started	Apr 30 03:47:44 PM PDT 24
Finished	Apr 30 03:47:54 PM PDT 24
Peak memory	241392 kb
Host	smart-56584baf-a4a4-4f7a-80b9-2f8727e38e2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1891090316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.1891090316
Directory	/workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/144.otp_ctrl_init_fail.1563392540
Short name	T458
Test name
Test status
Simulation time	1689138260 ps
CPU time	5.32 seconds
Started	Apr 30 03:47:41 PM PDT 24
Finished	Apr 30 03:47:47 PM PDT 24
Peak memory	241708 kb
Host	smart-1fffe06e-28d5-44e8-a2e5-b6840fe63fc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1563392540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.1563392540
Directory	/workspace/144.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.3570414675
Short name	T332
Test name
Test status
Simulation time	321960839 ps
CPU time	4.68 seconds
Started	Apr 30 03:47:43 PM PDT 24
Finished	Apr 30 03:47:48 PM PDT 24
Peak memory	241364 kb
Host	smart-d75493cf-6e56-4a8d-9886-d7391762ea3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570414675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.3570414675
Directory	/workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/145.otp_ctrl_init_fail.2758102537
Short name	T857
Test name
Test status
Simulation time	3104361893 ps
CPU time	4.98 seconds
Started	Apr 30 03:47:40 PM PDT 24
Finished	Apr 30 03:47:46 PM PDT 24
Peak memory	241884 kb
Host	smart-fe9c9e12-3537-46f3-a1b5-0008e301994d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758102537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.2758102537
Directory	/workspace/145.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.3000695145
Short name	T78
Test name
Test status
Simulation time	216809796 ps
CPU time	10.93 seconds
Started	Apr 30 03:47:49 PM PDT 24
Finished	Apr 30 03:48:00 PM PDT 24
Peak memory	241660 kb
Host	smart-0f7db677-0a8e-482d-929d-60677cd0786f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3000695145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.3000695145
Directory	/workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/146.otp_ctrl_init_fail.528808281
Short name	T498
Test name
Test status
Simulation time	1628856209 ps
CPU time	5.21 seconds
Started	Apr 30 03:47:52 PM PDT 24
Finished	Apr 30 03:47:58 PM PDT 24
Peak memory	241528 kb
Host	smart-588032be-c8fc-4ffb-bd0d-8d01bacee50b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=528808281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.528808281
Directory	/workspace/146.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.3736179650
Short name	T705
Test name
Test status
Simulation time	184149160 ps
CPU time	5.62 seconds
Started	Apr 30 03:47:52 PM PDT 24
Finished	Apr 30 03:47:58 PM PDT 24
Peak memory	241240 kb
Host	smart-0224e3f0-a150-45c1-b612-d1e060b406f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3736179650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.3736179650
Directory	/workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/147.otp_ctrl_init_fail.4229184321
Short name	T141
Test name
Test status
Simulation time	432715700 ps
CPU time	4.41 seconds
Started	Apr 30 03:47:49 PM PDT 24
Finished	Apr 30 03:47:54 PM PDT 24
Peak memory	241312 kb
Host	smart-489694ca-0ad6-4112-9a93-fdbe46d8d56e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4229184321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.4229184321
Directory	/workspace/147.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.2368942288
Short name	T221
Test name
Test status
Simulation time	152678536 ps
CPU time	4.15 seconds
Started	Apr 30 03:47:49 PM PDT 24
Finished	Apr 30 03:47:54 PM PDT 24
Peak memory	241340 kb
Host	smart-ccf05425-0e6f-4c0c-a264-4bb1d1c8ebfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2368942288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.2368942288
Directory	/workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/148.otp_ctrl_init_fail.620045143
Short name	T805
Test name
Test status
Simulation time	246664284 ps
CPU time	4.91 seconds
Started	Apr 30 03:47:48 PM PDT 24
Finished	Apr 30 03:47:54 PM PDT 24
Peak memory	241396 kb
Host	smart-031179fe-2194-430e-851f-bd5b2fe16d47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620045143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.620045143
Directory	/workspace/148.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.332064519
Short name	T1153
Test name
Test status
Simulation time	118983669 ps
CPU time	3.2 seconds
Started	Apr 30 03:47:50 PM PDT 24
Finished	Apr 30 03:47:54 PM PDT 24
Peak memory	247900 kb
Host	smart-dd14eaa7-ecec-49fb-bc4b-a4f4b21fa682
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=332064519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.332064519
Directory	/workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/149.otp_ctrl_init_fail.3233996217
Short name	T806
Test name
Test status
Simulation time	193674624 ps
CPU time	4.8 seconds
Started	Apr 30 03:47:49 PM PDT 24
Finished	Apr 30 03:47:54 PM PDT 24
Peak memory	241316 kb
Host	smart-b183228f-da23-448a-bb77-e9262f35831e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3233996217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.3233996217
Directory	/workspace/149.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.389222841
Short name	T261
Test name
Test status
Simulation time	685427370 ps
CPU time	5.73 seconds
Started	Apr 30 03:47:49 PM PDT 24
Finished	Apr 30 03:47:55 PM PDT 24
Peak memory	241664 kb
Host	smart-a3f30fa4-749c-4293-98c6-31de9ce53cf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=389222841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.389222841
Directory	/workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/15.otp_ctrl_alert_test.3162934497
Short name	T1141
Test name
Test status
Simulation time	181975230 ps
CPU time	1.63 seconds
Started	Apr 30 03:42:00 PM PDT 24
Finished	Apr 30 03:42:02 PM PDT 24
Peak memory	240160 kb
Host	smart-5859bf66-8714-4c9d-ba1f-71cb9e36c5c0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162934497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.3162934497
Directory	/workspace/15.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.otp_ctrl_check_fail.1356901940
Short name	T773
Test name
Test status
Simulation time	1271897813 ps
CPU time	26.26 seconds
Started	Apr 30 03:41:57 PM PDT 24
Finished	Apr 30 03:42:23 PM PDT 24
Peak memory	241476 kb
Host	smart-79a8c659-3377-4779-9e27-6ddf00da5cdf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356901940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.1356901940
Directory	/workspace/15.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/15.otp_ctrl_dai_errs.3446094010
Short name	T1137
Test name
Test status
Simulation time	5332807514 ps
CPU time	39.01 seconds
Started	Apr 30 03:41:57 PM PDT 24
Finished	Apr 30 03:42:36 PM PDT 24
Peak memory	250080 kb
Host	smart-1e0fea2f-d6f7-410a-b9ef-70e4b16736d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446094010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.3446094010
Directory	/workspace/15.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/15.otp_ctrl_dai_lock.3008014256
Short name	T441
Test name
Test status
Simulation time	5077200334 ps
CPU time	11.37 seconds
Started	Apr 30 03:41:58 PM PDT 24
Finished	Apr 30 03:42:10 PM PDT 24
Peak memory	242144 kb
Host	smart-2d1db22b-a8e1-41b3-af1a-75b5750738a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008014256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.3008014256
Directory	/workspace/15.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/15.otp_ctrl_init_fail.1867261411
Short name	T1133
Test name
Test status
Simulation time	1758265005 ps
CPU time	4.4 seconds
Started	Apr 30 03:41:55 PM PDT 24
Finished	Apr 30 03:42:00 PM PDT 24
Peak memory	241436 kb
Host	smart-4a037f93-f481-469e-8c15-cca803a99282
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1867261411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.1867261411
Directory	/workspace/15.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/15.otp_ctrl_macro_errs.3311181111
Short name	T850
Test name
Test status
Simulation time	29424991051 ps
CPU time	31.66 seconds
Started	Apr 30 03:42:01 PM PDT 24
Finished	Apr 30 03:42:33 PM PDT 24
Peak memory	256364 kb
Host	smart-d856e0fc-48a2-4827-a91d-44738ac82e40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3311181111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.3311181111
Directory	/workspace/15.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/15.otp_ctrl_parallel_key_req.3973106916
Short name	T866
Test name
Test status
Simulation time	1142855160 ps
CPU time	22.8 seconds
Started	Apr 30 03:42:07 PM PDT 24
Finished	Apr 30 03:42:30 PM PDT 24
Peak memory	241360 kb
Host	smart-2aa5b2f9-e855-42bc-bb76-d4da164a194f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3973106916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.3973106916
Directory	/workspace/15.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.1117609046
Short name	T419
Test name
Test status
Simulation time	179353733 ps
CPU time	3.74 seconds
Started	Apr 30 03:41:57 PM PDT 24
Finished	Apr 30 03:42:02 PM PDT 24
Peak memory	241220 kb
Host	smart-14596736-9f89-435e-988d-626ff4b32d73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1117609046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.1117609046
Directory	/workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/15.otp_ctrl_regwen.1156157799
Short name	T386
Test name
Test status
Simulation time	710348459 ps
CPU time	12.34 seconds
Started	Apr 30 03:42:02 PM PDT 24
Finished	Apr 30 03:42:15 PM PDT 24
Peak memory	247908 kb
Host	smart-5501b7ac-f4ff-4048-acc8-ba43ff15bbdd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1156157799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.1156157799
Directory	/workspace/15.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/15.otp_ctrl_smoke.2217873558
Short name	T1065
Test name
Test status
Simulation time	645417019 ps
CPU time	8.46 seconds
Started	Apr 30 03:41:56 PM PDT 24
Finished	Apr 30 03:42:05 PM PDT 24
Peak memory	241604 kb
Host	smart-7d9f31a2-d430-483b-a326-a2e647b96736
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217873558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.2217873558
Directory	/workspace/15.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.otp_ctrl_stress_all.3556651893
Short name	T642
Test name
Test status
Simulation time	1309703675 ps
CPU time	31.63 seconds
Started	Apr 30 03:42:01 PM PDT 24
Finished	Apr 30 03:42:33 PM PDT 24
Peak memory	241296 kb
Host	smart-27e0d460-18e5-4495-bf0c-133a78011456
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556651893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all .3556651893
Directory	/workspace/15.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.3331821826
Short name	T1078
Test name
Test status
Simulation time	1627479830612 ps
CPU time	3700.66 seconds
Started	Apr 30 03:42:00 PM PDT 24
Finished	Apr 30 04:43:42 PM PDT 24
Peak memory	513972 kb
Host	smart-5d5ff131-03d6-42e7-9398-b5fe07a801e2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331821826 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.3331821826
Directory	/workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.otp_ctrl_test_access.1303121198
Short name	T239
Test name
Test status
Simulation time	553764981 ps
CPU time	9.47 seconds
Started	Apr 30 03:42:07 PM PDT 24
Finished	Apr 30 03:42:17 PM PDT 24
Peak memory	241232 kb
Host	smart-eb0e3915-01be-4549-91ed-7a4ca1f78e7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1303121198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.1303121198
Directory	/workspace/15.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.4190461887
Short name	T240
Test name
Test status
Simulation time	878311260 ps
CPU time	25.7 seconds
Started	Apr 30 03:47:48 PM PDT 24
Finished	Apr 30 03:48:14 PM PDT 24
Peak memory	241316 kb
Host	smart-c7a4222e-ca03-438e-93a2-59e2c423e58b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4190461887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.4190461887
Directory	/workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/151.otp_ctrl_init_fail.3992252376
Short name	T987
Test name
Test status
Simulation time	164494989 ps
CPU time	3.99 seconds
Started	Apr 30 03:47:51 PM PDT 24
Finished	Apr 30 03:47:55 PM PDT 24
Peak memory	241368 kb
Host	smart-51d68068-230c-478c-9a59-b1d13b62c214
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3992252376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.3992252376
Directory	/workspace/151.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.426643170
Short name	T734
Test name
Test status
Simulation time	690659517 ps
CPU time	11.72 seconds
Started	Apr 30 03:47:50 PM PDT 24
Finished	Apr 30 03:48:02 PM PDT 24
Peak memory	241344 kb
Host	smart-cec1967d-1e88-4aab-b7eb-96c3e9cb336e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426643170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.426643170
Directory	/workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/152.otp_ctrl_init_fail.66412184
Short name	T561
Test name
Test status
Simulation time	2514638809 ps
CPU time	5.3 seconds
Started	Apr 30 03:47:56 PM PDT 24
Finished	Apr 30 03:48:02 PM PDT 24
Peak memory	241880 kb
Host	smart-f40e3cdf-597d-4ceb-8dc7-e4acc88ff0a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66412184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.66412184
Directory	/workspace/152.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.1158394927
Short name	T1098
Test name
Test status
Simulation time	112006524 ps
CPU time	3.42 seconds
Started	Apr 30 03:47:56 PM PDT 24
Finished	Apr 30 03:48:00 PM PDT 24
Peak memory	241724 kb
Host	smart-9acc0a04-4899-4045-b070-f6182c9836d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1158394927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.1158394927
Directory	/workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/153.otp_ctrl_init_fail.4269616746
Short name	T984
Test name
Test status
Simulation time	547819116 ps
CPU time	5.3 seconds
Started	Apr 30 03:47:57 PM PDT 24
Finished	Apr 30 03:48:02 PM PDT 24
Peak memory	241784 kb
Host	smart-8463097e-f836-4039-a3b1-983ed5cb5bd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4269616746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.4269616746
Directory	/workspace/153.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.2258672516
Short name	T575
Test name
Test status
Simulation time	12489004519 ps
CPU time	34.09 seconds
Started	Apr 30 03:47:57 PM PDT 24
Finished	Apr 30 03:48:32 PM PDT 24
Peak memory	241520 kb
Host	smart-28bb2a02-7d28-4ff9-8702-9e7cf23bbf3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258672516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.2258672516
Directory	/workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/154.otp_ctrl_init_fail.826397464
Short name	T809
Test name
Test status
Simulation time	276031166 ps
CPU time	3.96 seconds
Started	Apr 30 03:47:54 PM PDT 24
Finished	Apr 30 03:47:59 PM PDT 24
Peak memory	241480 kb
Host	smart-806f76cd-9abc-42d1-8a82-de75ae79216f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826397464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.826397464
Directory	/workspace/154.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.446841853
Short name	T1190
Test name
Test status
Simulation time	239542123 ps
CPU time	3.91 seconds
Started	Apr 30 03:47:55 PM PDT 24
Finished	Apr 30 03:48:00 PM PDT 24
Peak memory	241324 kb
Host	smart-5ca87a00-0339-4b9b-a46e-966a0fcf80eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=446841853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.446841853
Directory	/workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/155.otp_ctrl_init_fail.2923919450
Short name	T1177
Test name
Test status
Simulation time	402915957 ps
CPU time	4.3 seconds
Started	Apr 30 03:47:56 PM PDT 24
Finished	Apr 30 03:48:01 PM PDT 24
Peak memory	241312 kb
Host	smart-29b21ab8-89f3-4e18-a5d0-04349300c0c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923919450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.2923919450
Directory	/workspace/155.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.1419596115
Short name	T934
Test name
Test status
Simulation time	437729937 ps
CPU time	11.15 seconds
Started	Apr 30 03:47:57 PM PDT 24
Finished	Apr 30 03:48:08 PM PDT 24
Peak memory	241844 kb
Host	smart-c90447d2-37c6-4f79-93ca-cae41a0abeae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1419596115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.1419596115
Directory	/workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/156.otp_ctrl_init_fail.1695685728
Short name	T59
Test name
Test status
Simulation time	655884533 ps
CPU time	4.33 seconds
Started	Apr 30 03:47:55 PM PDT 24
Finished	Apr 30 03:48:00 PM PDT 24
Peak memory	241688 kb
Host	smart-1e4d5d6d-8c27-4100-82d2-733268e4a91e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1695685728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.1695685728
Directory	/workspace/156.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.3057622927
Short name	T1057
Test name
Test status
Simulation time	2395407539 ps
CPU time	7.49 seconds
Started	Apr 30 03:47:56 PM PDT 24
Finished	Apr 30 03:48:04 PM PDT 24
Peak memory	241396 kb
Host	smart-a7976a02-d421-4912-959c-b863dc53c672
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057622927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.3057622927
Directory	/workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/157.otp_ctrl_init_fail.3557113698
Short name	T201
Test name
Test status
Simulation time	2032765313 ps
CPU time	3.92 seconds
Started	Apr 30 03:47:57 PM PDT 24
Finished	Apr 30 03:48:02 PM PDT 24
Peak memory	241624 kb
Host	smart-7df7308e-d27b-4bf9-85a3-61f6d2abbaa7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3557113698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.3557113698
Directory	/workspace/157.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.2719067665
Short name	T997
Test name
Test status
Simulation time	186197071 ps
CPU time	6.04 seconds
Started	Apr 30 03:47:56 PM PDT 24
Finished	Apr 30 03:48:03 PM PDT 24
Peak memory	241308 kb
Host	smart-5a88d1d6-7570-40f9-9c65-accb2b593c7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2719067665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.2719067665
Directory	/workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.123546084
Short name	T610
Test name
Test status
Simulation time	128975337 ps
CPU time	3.66 seconds
Started	Apr 30 03:47:57 PM PDT 24
Finished	Apr 30 03:48:01 PM PDT 24
Peak memory	241276 kb
Host	smart-c54870ef-1617-47fb-8038-1d2cebe10dd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123546084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.123546084
Directory	/workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/159.otp_ctrl_init_fail.1097514568
Short name	T82
Test name
Test status
Simulation time	435101822 ps
CPU time	3.75 seconds
Started	Apr 30 03:47:57 PM PDT 24
Finished	Apr 30 03:48:01 PM PDT 24
Peak memory	241716 kb
Host	smart-85fe68ea-d8ef-428a-8eda-244532b9d657
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1097514568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1097514568
Directory	/workspace/159.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.1421597427
Short name	T494
Test name
Test status
Simulation time	244298104 ps
CPU time	4.04 seconds
Started	Apr 30 03:47:55 PM PDT 24
Finished	Apr 30 03:48:00 PM PDT 24
Peak memory	241124 kb
Host	smart-0e0eb72b-373f-4529-a169-fc191d9ca350
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1421597427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1421597427
Directory	/workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/16.otp_ctrl_check_fail.2588587221
Short name	T969
Test name
Test status
Simulation time	630192098 ps
CPU time	5.04 seconds
Started	Apr 30 03:42:09 PM PDT 24
Finished	Apr 30 03:42:15 PM PDT 24
Peak memory	247852 kb
Host	smart-5672937b-852b-46dd-a693-0f883f30f980
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588587221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.2588587221
Directory	/workspace/16.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/16.otp_ctrl_dai_errs.3999155095
Short name	T367
Test name
Test status
Simulation time	1363173752 ps
CPU time	25.57 seconds
Started	Apr 30 03:42:07 PM PDT 24
Finished	Apr 30 03:42:33 PM PDT 24
Peak memory	241760 kb
Host	smart-ca4e90fb-3d99-4b2c-b20a-a8db19d00dab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3999155095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.3999155095
Directory	/workspace/16.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/16.otp_ctrl_dai_lock.620500635
Short name	T1077
Test name
Test status
Simulation time	5981178479 ps
CPU time	10.4 seconds
Started	Apr 30 03:42:09 PM PDT 24
Finished	Apr 30 03:42:20 PM PDT 24
Peak memory	242168 kb
Host	smart-70199724-f671-491a-b2da-d122d099ddec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620500635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.620500635
Directory	/workspace/16.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/16.otp_ctrl_init_fail.2329466887
Short name	T560
Test name
Test status
Simulation time	218749989 ps
CPU time	3.72 seconds
Started	Apr 30 03:42:01 PM PDT 24
Finished	Apr 30 03:42:05 PM PDT 24
Peak memory	241376 kb
Host	smart-de02c1bf-f747-4d39-8db7-df4e595543ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2329466887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2329466887
Directory	/workspace/16.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/16.otp_ctrl_macro_errs.1830690291
Short name	T800
Test name
Test status
Simulation time	1705606532 ps
CPU time	19.59 seconds
Started	Apr 30 03:42:09 PM PDT 24
Finished	Apr 30 03:42:29 PM PDT 24
Peak memory	247088 kb
Host	smart-e28c6fdf-3ff1-4559-ba6e-54e41742101e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1830690291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.1830690291
Directory	/workspace/16.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/16.otp_ctrl_parallel_key_req.3069715627
Short name	T830
Test name
Test status
Simulation time	1028483257 ps
CPU time	11.93 seconds
Started	Apr 30 03:42:05 PM PDT 24
Finished	Apr 30 03:42:18 PM PDT 24
Peak memory	241432 kb
Host	smart-0a0076f7-53eb-4d09-8697-c13267990bc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069715627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.3069715627
Directory	/workspace/16.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.2141548930
Short name	T630
Test name
Test status
Simulation time	1831498866 ps
CPU time	17.19 seconds
Started	Apr 30 03:42:06 PM PDT 24
Finished	Apr 30 03:42:24 PM PDT 24
Peak memory	241796 kb
Host	smart-9eb1e5c8-8afe-40e5-85e6-3c429fc5c922
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2141548930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.2141548930
Directory	/workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/16.otp_ctrl_parallel_lc_req.3900710212
Short name	T482
Test name
Test status
Simulation time	942877575 ps
CPU time	15.33 seconds
Started	Apr 30 03:42:07 PM PDT 24
Finished	Apr 30 03:42:23 PM PDT 24
Peak memory	241360 kb
Host	smart-3064771c-35a9-41fb-bfc6-51f8a3f3afb9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3900710212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.3900710212
Directory	/workspace/16.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/16.otp_ctrl_regwen.772915907
Short name	T495
Test name
Test status
Simulation time	2167818436 ps
CPU time	5.89 seconds
Started	Apr 30 03:42:07 PM PDT 24
Finished	Apr 30 03:42:13 PM PDT 24
Peak memory	241384 kb
Host	smart-5d388004-d594-4cc3-90f5-b705c7e406f0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=772915907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.772915907
Directory	/workspace/16.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/16.otp_ctrl_smoke.355325938
Short name	T113
Test name
Test status
Simulation time	2687834733 ps
CPU time	7.22 seconds
Started	Apr 30 03:42:01 PM PDT 24
Finished	Apr 30 03:42:09 PM PDT 24
Peak memory	241292 kb
Host	smart-144a3a4a-65f8-493c-a0a3-34b8f9caa948
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=355325938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.355325938
Directory	/workspace/16.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.423231900
Short name	T1031
Test name
Test status
Simulation time	384416274868 ps
CPU time	1316.66 seconds
Started	Apr 30 03:42:12 PM PDT 24
Finished	Apr 30 04:04:09 PM PDT 24
Peak memory	276168 kb
Host	smart-30c5c0cc-8bb5-488e-9b4f-12be006b25fa
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423231900 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.423231900
Directory	/workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.otp_ctrl_test_access.1063100319
Short name	T1106
Test name
Test status
Simulation time	1167789645 ps
CPU time	13.72 seconds
Started	Apr 30 03:42:12 PM PDT 24
Finished	Apr 30 03:42:27 PM PDT 24
Peak memory	241300 kb
Host	smart-0dbbae37-60c9-4262-a828-431a28efa6dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063100319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.1063100319
Directory	/workspace/16.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/160.otp_ctrl_init_fail.872494370
Short name	T507
Test name
Test status
Simulation time	357578501 ps
CPU time	3.49 seconds
Started	Apr 30 03:47:56 PM PDT 24
Finished	Apr 30 03:48:00 PM PDT 24
Peak memory	241700 kb
Host	smart-f8b77262-1f2a-4c64-af12-24981507ec93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872494370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.872494370
Directory	/workspace/160.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.3161743673
Short name	T615
Test name
Test status
Simulation time	197903783 ps
CPU time	3.64 seconds
Started	Apr 30 03:47:57 PM PDT 24
Finished	Apr 30 03:48:01 PM PDT 24
Peak memory	241144 kb
Host	smart-0941e295-2393-4bcd-81cd-072cbc4c5345
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3161743673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3161743673
Directory	/workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/161.otp_ctrl_init_fail.607785520
Short name	T137
Test name
Test status
Simulation time	321620864 ps
CPU time	4.04 seconds
Started	Apr 30 03:47:59 PM PDT 24
Finished	Apr 30 03:48:03 PM PDT 24
Peak memory	241744 kb
Host	smart-bfcb04a3-5a5b-4f97-b45e-0fa4c52c061c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=607785520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.607785520
Directory	/workspace/161.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.457029053
Short name	T265
Test name
Test status
Simulation time	1551181766 ps
CPU time	10.52 seconds
Started	Apr 30 03:48:02 PM PDT 24
Finished	Apr 30 03:48:13 PM PDT 24
Peak memory	247228 kb
Host	smart-21f42edf-fee7-471c-9bde-f5fceadea85f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=457029053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.457029053
Directory	/workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/162.otp_ctrl_init_fail.1093650970
Short name	T1104
Test name
Test status
Simulation time	140827036 ps
CPU time	4.23 seconds
Started	Apr 30 03:48:01 PM PDT 24
Finished	Apr 30 03:48:05 PM PDT 24
Peak memory	241384 kb
Host	smart-5651934f-af35-42dc-8283-f002ca237c30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1093650970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.1093650970
Directory	/workspace/162.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.3779961445
Short name	T998
Test name
Test status
Simulation time	329921767 ps
CPU time	9.15 seconds
Started	Apr 30 03:48:04 PM PDT 24
Finished	Apr 30 03:48:14 PM PDT 24
Peak memory	241748 kb
Host	smart-a30ac791-eb99-42c0-9dec-5a416badd65b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779961445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.3779961445
Directory	/workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/163.otp_ctrl_init_fail.3077016717
Short name	T614
Test name
Test status
Simulation time	1873633449 ps
CPU time	4.31 seconds
Started	Apr 30 03:48:05 PM PDT 24
Finished	Apr 30 03:48:10 PM PDT 24
Peak memory	241740 kb
Host	smart-55aafb26-d8d3-4ebb-a00f-109d38d7f767
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3077016717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.3077016717
Directory	/workspace/163.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.592110739
Short name	T557
Test name
Test status
Simulation time	954508667 ps
CPU time	15.15 seconds
Started	Apr 30 03:48:00 PM PDT 24
Finished	Apr 30 03:48:16 PM PDT 24
Peak memory	241204 kb
Host	smart-045d1026-474b-434b-a502-004eaf2e5e73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592110739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.592110739
Directory	/workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/164.otp_ctrl_init_fail.2736678215
Short name	T895
Test name
Test status
Simulation time	280509576 ps
CPU time	4.09 seconds
Started	Apr 30 03:48:02 PM PDT 24
Finished	Apr 30 03:48:06 PM PDT 24
Peak memory	241744 kb
Host	smart-7764b51b-c227-4380-a554-48400fa8b1d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2736678215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.2736678215
Directory	/workspace/164.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.4182559702
Short name	T637
Test name
Test status
Simulation time	2605631031 ps
CPU time	8.93 seconds
Started	Apr 30 03:48:02 PM PDT 24
Finished	Apr 30 03:48:11 PM PDT 24
Peak memory	241452 kb
Host	smart-4c708ffb-530f-499d-a1c6-b75758134216
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4182559702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.4182559702
Directory	/workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/165.otp_ctrl_init_fail.1217420624
Short name	T1173
Test name
Test status
Simulation time	488195064 ps
CPU time	3.55 seconds
Started	Apr 30 03:48:02 PM PDT 24
Finished	Apr 30 03:48:06 PM PDT 24
Peak memory	241592 kb
Host	smart-ac78ee36-2934-4588-9e6a-7a016f4743f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217420624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.1217420624
Directory	/workspace/165.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.3008884302
Short name	T248
Test name
Test status
Simulation time	819181068 ps
CPU time	9.66 seconds
Started	Apr 30 03:48:03 PM PDT 24
Finished	Apr 30 03:48:13 PM PDT 24
Peak memory	241244 kb
Host	smart-349a8136-eeca-4100-a7c0-363fd179858d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008884302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3008884302
Directory	/workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/166.otp_ctrl_init_fail.1705188552
Short name	T607
Test name
Test status
Simulation time	220513132 ps
CPU time	4.33 seconds
Started	Apr 30 03:48:01 PM PDT 24
Finished	Apr 30 03:48:06 PM PDT 24
Peak memory	241356 kb
Host	smart-d40ee1c2-1640-48a3-a517-35f3d02b03b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705188552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.1705188552
Directory	/workspace/166.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.2521092560
Short name	T1140
Test name
Test status
Simulation time	169192860 ps
CPU time	4.08 seconds
Started	Apr 30 03:48:05 PM PDT 24
Finished	Apr 30 03:48:09 PM PDT 24
Peak memory	241268 kb
Host	smart-cd851cba-0ea2-44c5-94f8-7f262bc0d197
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2521092560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.2521092560
Directory	/workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/167.otp_ctrl_init_fail.3164945957
Short name	T466
Test name
Test status
Simulation time	2213234067 ps
CPU time	6.42 seconds
Started	Apr 30 03:48:05 PM PDT 24
Finished	Apr 30 03:48:12 PM PDT 24
Peak memory	241436 kb
Host	smart-44b0314d-49dc-4a38-b430-c711ecf4853d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3164945957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.3164945957
Directory	/workspace/167.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/168.otp_ctrl_init_fail.353872510
Short name	T616
Test name
Test status
Simulation time	162912324 ps
CPU time	4.1 seconds
Started	Apr 30 03:48:01 PM PDT 24
Finished	Apr 30 03:48:06 PM PDT 24
Peak memory	241688 kb
Host	smart-01a32207-63a8-4d44-95a4-3ba117b781ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=353872510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.353872510
Directory	/workspace/168.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.2508807180
Short name	T468
Test name
Test status
Simulation time	451084244 ps
CPU time	11.73 seconds
Started	Apr 30 03:48:10 PM PDT 24
Finished	Apr 30 03:48:23 PM PDT 24
Peak memory	248012 kb
Host	smart-1ac2c5bd-990a-4c98-b1dc-a2536b110933
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2508807180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.2508807180
Directory	/workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/169.otp_ctrl_init_fail.902418947
Short name	T1116
Test name
Test status
Simulation time	89509445 ps
CPU time	3.06 seconds
Started	Apr 30 03:48:09 PM PDT 24
Finished	Apr 30 03:48:12 PM PDT 24
Peak memory	241308 kb
Host	smart-4d585c9b-2151-4886-af08-11d0c7605e1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=902418947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.902418947
Directory	/workspace/169.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.1291095559
Short name	T742
Test name
Test status
Simulation time	529654971 ps
CPU time	15.73 seconds
Started	Apr 30 03:48:11 PM PDT 24
Finished	Apr 30 03:48:27 PM PDT 24
Peak memory	241336 kb
Host	smart-cf52d767-e2f5-4317-a3ef-ebe7f433c481
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291095559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.1291095559
Directory	/workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/17.otp_ctrl_alert_test.565100135
Short name	T877
Test name
Test status
Simulation time	57068074 ps
CPU time	1.7 seconds
Started	Apr 30 03:42:17 PM PDT 24
Finished	Apr 30 03:42:20 PM PDT 24
Peak memory	240200 kb
Host	smart-92ddb5fe-7e5f-4127-9050-1aa3c6298df8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565100135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.565100135
Directory	/workspace/17.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.otp_ctrl_check_fail.3881488487
Short name	T979
Test name
Test status
Simulation time	1328533133 ps
CPU time	27.65 seconds
Started	Apr 30 03:42:13 PM PDT 24
Finished	Apr 30 03:42:41 PM PDT 24
Peak memory	247972 kb
Host	smart-57ff467f-7d80-4cbf-a053-faf7fb1a7e39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881488487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.3881488487
Directory	/workspace/17.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/17.otp_ctrl_dai_errs.1510521977
Short name	T602
Test name
Test status
Simulation time	850783114 ps
CPU time	30.99 seconds
Started	Apr 30 03:42:12 PM PDT 24
Finished	Apr 30 03:42:43 PM PDT 24
Peak memory	241460 kb
Host	smart-b7941e39-5a2c-4f37-9e82-b3fd9a89726f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1510521977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.1510521977
Directory	/workspace/17.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/17.otp_ctrl_dai_lock.217606739
Short name	T960
Test name
Test status
Simulation time	7797039339 ps
CPU time	18.35 seconds
Started	Apr 30 03:42:12 PM PDT 24
Finished	Apr 30 03:42:31 PM PDT 24
Peak memory	241716 kb
Host	smart-f2414f3c-0a78-4cdb-ae5c-4f32aaf1ece9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=217606739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.217606739
Directory	/workspace/17.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/17.otp_ctrl_macro_errs.1642966754
Short name	T1045
Test name
Test status
Simulation time	993909068 ps
CPU time	12.38 seconds
Started	Apr 30 03:42:13 PM PDT 24
Finished	Apr 30 03:42:26 PM PDT 24
Peak memory	247984 kb
Host	smart-632f4fb2-245c-4159-8544-7ae3a7379be6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1642966754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.1642966754
Directory	/workspace/17.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/17.otp_ctrl_parallel_key_req.2410289146
Short name	T626
Test name
Test status
Simulation time	138164057 ps
CPU time	3.84 seconds
Started	Apr 30 03:42:20 PM PDT 24
Finished	Apr 30 03:42:24 PM PDT 24
Peak memory	241440 kb
Host	smart-2255be9c-943c-4bb7-8453-cb2b265fccfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2410289146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.2410289146
Directory	/workspace/17.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.4094012798
Short name	T440
Test name
Test status
Simulation time	260859938 ps
CPU time	3 seconds
Started	Apr 30 03:42:12 PM PDT 24
Finished	Apr 30 03:42:15 PM PDT 24
Peak memory	241260 kb
Host	smart-106a8825-a159-4c8d-8675-8c8e50bce1ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094012798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.4094012798
Directory	/workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/17.otp_ctrl_regwen.4117497734
Short name	T391
Test name
Test status
Simulation time	503900334 ps
CPU time	6.26 seconds
Started	Apr 30 03:42:23 PM PDT 24
Finished	Apr 30 03:42:29 PM PDT 24
Peak memory	241608 kb
Host	smart-4a328687-a8e4-45e5-99c2-9883d5ad152a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4117497734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.4117497734
Directory	/workspace/17.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/17.otp_ctrl_smoke.574018283
Short name	T568
Test name
Test status
Simulation time	4381222836 ps
CPU time	8.28 seconds
Started	Apr 30 03:42:11 PM PDT 24
Finished	Apr 30 03:42:19 PM PDT 24
Peak memory	241676 kb
Host	smart-9c67869e-aa52-465a-b7ca-4279ba2bcd74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574018283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.574018283
Directory	/workspace/17.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.otp_ctrl_test_access.138957361
Short name	T195
Test name
Test status
Simulation time	947872587 ps
CPU time	14.17 seconds
Started	Apr 30 03:42:20 PM PDT 24
Finished	Apr 30 03:42:34 PM PDT 24
Peak memory	241248 kb
Host	smart-f46c716c-2333-4eb2-8009-a49cecc97625
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=138957361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.138957361
Directory	/workspace/17.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/170.otp_ctrl_init_fail.3687477178
Short name	T627
Test name
Test status
Simulation time	110969054 ps
CPU time	4.08 seconds
Started	Apr 30 03:48:09 PM PDT 24
Finished	Apr 30 03:48:13 PM PDT 24
Peak memory	241672 kb
Host	smart-1855358a-a720-4b23-940d-8609475096ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3687477178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.3687477178
Directory	/workspace/170.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.2869112406
Short name	T1166
Test name
Test status
Simulation time	230307588 ps
CPU time	12.36 seconds
Started	Apr 30 03:48:11 PM PDT 24
Finished	Apr 30 03:48:24 PM PDT 24
Peak memory	241164 kb
Host	smart-684eb33b-dde1-435e-aeb7-15a0758a4d37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2869112406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.2869112406
Directory	/workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.584981010
Short name	T224
Test name
Test status
Simulation time	166060685 ps
CPU time	5.25 seconds
Started	Apr 30 03:48:08 PM PDT 24
Finished	Apr 30 03:48:14 PM PDT 24
Peak memory	241756 kb
Host	smart-08bcc879-74d5-46f0-828f-c206a8887b97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=584981010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.584981010
Directory	/workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/172.otp_ctrl_init_fail.3647567304
Short name	T640
Test name
Test status
Simulation time	217108567 ps
CPU time	4.74 seconds
Started	Apr 30 03:48:09 PM PDT 24
Finished	Apr 30 03:48:14 PM PDT 24
Peak memory	241380 kb
Host	smart-850c1613-4106-4f69-8bea-602ab2f56bd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3647567304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.3647567304
Directory	/workspace/172.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.2346005320
Short name	T646
Test name
Test status
Simulation time	177051927 ps
CPU time	9.34 seconds
Started	Apr 30 03:48:08 PM PDT 24
Finished	Apr 30 03:48:18 PM PDT 24
Peak memory	241300 kb
Host	smart-fd8c420e-8b88-4eb5-90ca-24074c429089
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346005320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.2346005320
Directory	/workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/173.otp_ctrl_init_fail.3744892761
Short name	T203
Test name
Test status
Simulation time	190055714 ps
CPU time	3.53 seconds
Started	Apr 30 03:48:08 PM PDT 24
Finished	Apr 30 03:48:11 PM PDT 24
Peak memory	241304 kb
Host	smart-deda22f1-20a6-461b-afe2-0681ffa2369e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744892761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.3744892761
Directory	/workspace/173.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.3621911065
Short name	T488
Test name
Test status
Simulation time	278755314 ps
CPU time	7.08 seconds
Started	Apr 30 03:48:09 PM PDT 24
Finished	Apr 30 03:48:17 PM PDT 24
Peak memory	241664 kb
Host	smart-7b6d28d8-1230-4a4c-8231-d1d1f090ac0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3621911065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.3621911065
Directory	/workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/174.otp_ctrl_init_fail.362420277
Short name	T863
Test name
Test status
Simulation time	87364680 ps
CPU time	3.52 seconds
Started	Apr 30 03:48:08 PM PDT 24
Finished	Apr 30 03:48:12 PM PDT 24
Peak memory	241392 kb
Host	smart-cae0c660-5ab6-4ef8-9c8b-cdf6346e04d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=362420277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.362420277
Directory	/workspace/174.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.3729686532
Short name	T748
Test name
Test status
Simulation time	188453390 ps
CPU time	5.09 seconds
Started	Apr 30 03:48:08 PM PDT 24
Finished	Apr 30 03:48:14 PM PDT 24
Peak memory	241724 kb
Host	smart-48c172c5-9bbc-45e6-9a58-d855907c0649
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3729686532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.3729686532
Directory	/workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/175.otp_ctrl_init_fail.1654258386
Short name	T605
Test name
Test status
Simulation time	336873262 ps
CPU time	4.73 seconds
Started	Apr 30 03:48:08 PM PDT 24
Finished	Apr 30 03:48:13 PM PDT 24
Peak memory	241276 kb
Host	smart-d738604a-7f03-4b61-a213-e32e4f21a8ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654258386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.1654258386
Directory	/workspace/175.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.804315184
Short name	T951
Test name
Test status
Simulation time	137194250 ps
CPU time	3.88 seconds
Started	Apr 30 03:48:11 PM PDT 24
Finished	Apr 30 03:48:15 PM PDT 24
Peak memory	241300 kb
Host	smart-9732b9df-0828-47ed-be7f-30bfa6fc6cb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=804315184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.804315184
Directory	/workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/176.otp_ctrl_init_fail.3345951148
Short name	T618
Test name
Test status
Simulation time	721194642 ps
CPU time	5.33 seconds
Started	Apr 30 03:48:14 PM PDT 24
Finished	Apr 30 03:48:20 PM PDT 24
Peak memory	241444 kb
Host	smart-58fea084-7394-430e-8e7e-0206000f02fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3345951148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3345951148
Directory	/workspace/176.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.3067773155
Short name	T448
Test name
Test status
Simulation time	1454650510 ps
CPU time	4.74 seconds
Started	Apr 30 03:48:15 PM PDT 24
Finished	Apr 30 03:48:20 PM PDT 24
Peak memory	241588 kb
Host	smart-32bb0e4c-efdf-4bf9-a5ec-dba5b1b1f4b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3067773155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.3067773155
Directory	/workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/177.otp_ctrl_init_fail.258539348
Short name	T484
Test name
Test status
Simulation time	1487084721 ps
CPU time	4.24 seconds
Started	Apr 30 03:48:14 PM PDT 24
Finished	Apr 30 03:48:19 PM PDT 24
Peak memory	241300 kb
Host	smart-123a13a7-b280-489f-a08a-8484219a4f7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=258539348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.258539348
Directory	/workspace/177.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.3376452062
Short name	T959
Test name
Test status
Simulation time	216470406 ps
CPU time	5.14 seconds
Started	Apr 30 03:48:15 PM PDT 24
Finished	Apr 30 03:48:21 PM PDT 24
Peak memory	241340 kb
Host	smart-3dadf739-0511-47f2-b026-728bd69371a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376452062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.3376452062
Directory	/workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.394865448
Short name	T216
Test name
Test status
Simulation time	246226575 ps
CPU time	5.53 seconds
Started	Apr 30 03:48:16 PM PDT 24
Finished	Apr 30 03:48:23 PM PDT 24
Peak memory	241304 kb
Host	smart-58cf75f4-56f7-486a-b229-375d74b3ea96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394865448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.394865448
Directory	/workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/179.otp_ctrl_init_fail.654994656
Short name	T1052
Test name
Test status
Simulation time	348560234 ps
CPU time	4.14 seconds
Started	Apr 30 03:48:16 PM PDT 24
Finished	Apr 30 03:48:21 PM PDT 24
Peak memory	241392 kb
Host	smart-f0902695-4229-426e-9e9f-cddc74992129
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=654994656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.654994656
Directory	/workspace/179.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.1920534556
Short name	T907
Test name
Test status
Simulation time	1750562418 ps
CPU time	5.15 seconds
Started	Apr 30 03:48:14 PM PDT 24
Finished	Apr 30 03:48:20 PM PDT 24
Peak memory	241236 kb
Host	smart-104afc52-7385-4b7d-90a4-a8f27458b038
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1920534556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.1920534556
Directory	/workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/18.otp_ctrl_alert_test.2205908417
Short name	T867
Test name
Test status
Simulation time	99800224 ps
CPU time	1.85 seconds
Started	Apr 30 03:42:22 PM PDT 24
Finished	Apr 30 03:42:25 PM PDT 24
Peak memory	240196 kb
Host	smart-b49d11af-1f69-4498-8084-a77caab9586d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205908417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.2205908417
Directory	/workspace/18.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.otp_ctrl_check_fail.1011251614
Short name	T29
Test name
Test status
Simulation time	725585673 ps
CPU time	25.59 seconds
Started	Apr 30 03:42:21 PM PDT 24
Finished	Apr 30 03:42:47 PM PDT 24
Peak memory	248064 kb
Host	smart-77506fad-a1b6-48d1-8ab4-4ba905525a02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1011251614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.1011251614
Directory	/workspace/18.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/18.otp_ctrl_dai_errs.3843932879
Short name	T207
Test name
Test status
Simulation time	259261551 ps
CPU time	15.06 seconds
Started	Apr 30 03:42:25 PM PDT 24
Finished	Apr 30 03:42:40 PM PDT 24
Peak memory	241164 kb
Host	smart-798cf031-fcf6-48d9-8571-e13197f0cf44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843932879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.3843932879
Directory	/workspace/18.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/18.otp_ctrl_dai_lock.3849250212
Short name	T415
Test name
Test status
Simulation time	741863080 ps
CPU time	12.95 seconds
Started	Apr 30 03:42:27 PM PDT 24
Finished	Apr 30 03:42:40 PM PDT 24
Peak memory	247968 kb
Host	smart-d1f5dec6-35e7-4a23-ac88-52c44eec3d54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849250212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.3849250212
Directory	/workspace/18.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/18.otp_ctrl_init_fail.2137224963
Short name	T695
Test name
Test status
Simulation time	1860217666 ps
CPU time	4.29 seconds
Started	Apr 30 03:42:17 PM PDT 24
Finished	Apr 30 03:42:22 PM PDT 24
Peak memory	241680 kb
Host	smart-d075aa0f-118c-44e4-bc75-cace0eedd93c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137224963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.2137224963
Directory	/workspace/18.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/18.otp_ctrl_macro_errs.1643135514
Short name	T337
Test name
Test status
Simulation time	1451940998 ps
CPU time	22.58 seconds
Started	Apr 30 03:42:21 PM PDT 24
Finished	Apr 30 03:42:44 PM PDT 24
Peak memory	242776 kb
Host	smart-29cc1d21-6461-4d9a-a505-e2dff0787d8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1643135514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.1643135514
Directory	/workspace/18.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/18.otp_ctrl_parallel_key_req.2169732995
Short name	T656
Test name
Test status
Simulation time	722611699 ps
CPU time	8.67 seconds
Started	Apr 30 03:42:22 PM PDT 24
Finished	Apr 30 03:42:31 PM PDT 24
Peak memory	241280 kb
Host	smart-4eaa3d60-1f6a-4021-a0a7-f812140987b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2169732995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.2169732995
Directory	/workspace/18.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.3783475179
Short name	T542
Test name
Test status
Simulation time	408120471 ps
CPU time	4.79 seconds
Started	Apr 30 03:42:18 PM PDT 24
Finished	Apr 30 03:42:24 PM PDT 24
Peak memory	241216 kb
Host	smart-6aa1ef55-0480-457b-9aaf-ff2869beb467
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3783475179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.3783475179
Directory	/workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/18.otp_ctrl_parallel_lc_req.3235109253
Short name	T599
Test name
Test status
Simulation time	145659575 ps
CPU time	3.46 seconds
Started	Apr 30 03:42:19 PM PDT 24
Finished	Apr 30 03:42:23 PM PDT 24
Peak memory	241052 kb
Host	smart-ec0b5352-064c-463b-9ac1-9313ef25bb48
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3235109253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.3235109253
Directory	/workspace/18.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/18.otp_ctrl_regwen.2775506416
Short name	T394
Test name
Test status
Simulation time	424515311 ps
CPU time	5.5 seconds
Started	Apr 30 03:42:23 PM PDT 24
Finished	Apr 30 03:42:28 PM PDT 24
Peak memory	241432 kb
Host	smart-6ea4c291-1189-40d7-bec4-9e29f810040f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2775506416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.2775506416
Directory	/workspace/18.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/18.otp_ctrl_smoke.629532278
Short name	T836
Test name
Test status
Simulation time	1885655305 ps
CPU time	11.25 seconds
Started	Apr 30 03:42:17 PM PDT 24
Finished	Apr 30 03:42:29 PM PDT 24
Peak memory	241324 kb
Host	smart-9b67037f-f343-4d01-9b10-68e6260b540d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=629532278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.629532278
Directory	/workspace/18.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.otp_ctrl_stress_all.3662845747
Short name	T259
Test name
Test status
Simulation time	8262207567 ps
CPU time	214.02 seconds
Started	Apr 30 03:42:32 PM PDT 24
Finished	Apr 30 03:46:06 PM PDT 24
Peak memory	280928 kb
Host	smart-15068b75-6e7c-4b37-9390-40b212380165
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662845747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all .3662845747
Directory	/workspace/18.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.74134365
Short name	T209
Test name
Test status
Simulation time	169938994403 ps
CPU time	2817.37 seconds
Started	Apr 30 03:42:21 PM PDT 24
Finished	Apr 30 04:29:20 PM PDT 24
Peak memory	658388 kb
Host	smart-f1f79f50-8062-474f-bb36-3d531161e9d2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74134365 -assert nopos tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.74134365
Directory	/workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.otp_ctrl_test_access.1441774502
Short name	T100
Test name
Test status
Simulation time	3155827631 ps
CPU time	7.47 seconds
Started	Apr 30 03:42:27 PM PDT 24
Finished	Apr 30 03:42:35 PM PDT 24
Peak memory	247988 kb
Host	smart-1c908321-0c36-4d5f-8300-6e67d1ecb4ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441774502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.1441774502
Directory	/workspace/18.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/180.otp_ctrl_init_fail.3155168281
Short name	T1046
Test name
Test status
Simulation time	1684035594 ps
CPU time	5.57 seconds
Started	Apr 30 03:48:14 PM PDT 24
Finished	Apr 30 03:48:20 PM PDT 24
Peak memory	241368 kb
Host	smart-79aded77-a2a1-4f95-9017-83d140a6ca6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3155168281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3155168281
Directory	/workspace/180.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.666429041
Short name	T756
Test name
Test status
Simulation time	340017232 ps
CPU time	4.07 seconds
Started	Apr 30 03:48:15 PM PDT 24
Finished	Apr 30 03:48:20 PM PDT 24
Peak memory	241296 kb
Host	smart-b61d446e-bfe4-4b86-b265-600ae1c5f6bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=666429041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.666429041
Directory	/workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.3068423924
Short name	T223
Test name
Test status
Simulation time	3430779815 ps
CPU time	17.72 seconds
Started	Apr 30 03:48:15 PM PDT 24
Finished	Apr 30 03:48:33 PM PDT 24
Peak memory	241448 kb
Host	smart-eed6a802-a188-496c-b862-12d3070cbe16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068423924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.3068423924
Directory	/workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/182.otp_ctrl_init_fail.300670817
Short name	T197
Test name
Test status
Simulation time	267316034 ps
CPU time	3.3 seconds
Started	Apr 30 03:48:15 PM PDT 24
Finished	Apr 30 03:48:19 PM PDT 24
Peak memory	241800 kb
Host	smart-6c9f1f46-7ed8-4856-b7fa-9d53bcb77dc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=300670817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.300670817
Directory	/workspace/182.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.2190736095
Short name	T263
Test name
Test status
Simulation time	510271025 ps
CPU time	13.61 seconds
Started	Apr 30 03:48:16 PM PDT 24
Finished	Apr 30 03:48:30 PM PDT 24
Peak memory	241244 kb
Host	smart-e76f0de4-5ba0-4afc-afb0-6a982813784a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190736095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.2190736095
Directory	/workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/183.otp_ctrl_init_fail.2164758098
Short name	T750
Test name
Test status
Simulation time	205122651 ps
CPU time	4.23 seconds
Started	Apr 30 03:48:17 PM PDT 24
Finished	Apr 30 03:48:22 PM PDT 24
Peak memory	241220 kb
Host	smart-582a8641-c5ea-42f4-a35f-15fa5d113d59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2164758098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.2164758098
Directory	/workspace/183.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.2626583511
Short name	T919
Test name
Test status
Simulation time	282552171 ps
CPU time	7.69 seconds
Started	Apr 30 03:48:14 PM PDT 24
Finished	Apr 30 03:48:23 PM PDT 24
Peak memory	241184 kb
Host	smart-b1d0ca8d-4738-4251-b54f-d099cfaad20e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2626583511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.2626583511
Directory	/workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/184.otp_ctrl_init_fail.2028257700
Short name	T874
Test name
Test status
Simulation time	1705051324 ps
CPU time	4.39 seconds
Started	Apr 30 03:48:17 PM PDT 24
Finished	Apr 30 03:48:22 PM PDT 24
Peak memory	241324 kb
Host	smart-783f3627-262c-47dd-987b-7780d5614bb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028257700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.2028257700
Directory	/workspace/184.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.2531131155
Short name	T1097
Test name
Test status
Simulation time	224428175 ps
CPU time	5.16 seconds
Started	Apr 30 03:48:16 PM PDT 24
Finished	Apr 30 03:48:22 PM PDT 24
Peak memory	241720 kb
Host	smart-1172b383-52df-4536-af08-7db4181b50b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2531131155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.2531131155
Directory	/workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/185.otp_ctrl_init_fail.1247442095
Short name	T71
Test name
Test status
Simulation time	296053213 ps
CPU time	3.53 seconds
Started	Apr 30 03:48:18 PM PDT 24
Finished	Apr 30 03:48:22 PM PDT 24
Peak memory	241456 kb
Host	smart-30adfac3-8b9f-46d1-9637-0db85f3f8a2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1247442095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.1247442095
Directory	/workspace/185.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.3073390574
Short name	T728
Test name
Test status
Simulation time	1967643308 ps
CPU time	13.37 seconds
Started	Apr 30 03:48:24 PM PDT 24
Finished	Apr 30 03:48:38 PM PDT 24
Peak memory	241576 kb
Host	smart-33149096-baa1-4a57-a69e-055a6b29085a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3073390574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3073390574
Directory	/workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/186.otp_ctrl_init_fail.3869005934
Short name	T31
Test name
Test status
Simulation time	647662505 ps
CPU time	4.95 seconds
Started	Apr 30 03:48:22 PM PDT 24
Finished	Apr 30 03:48:28 PM PDT 24
Peak memory	241804 kb
Host	smart-409749cd-ea61-49ed-b096-06c6dd6a8b80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3869005934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.3869005934
Directory	/workspace/186.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/187.otp_ctrl_init_fail.1643188632
Short name	T177
Test name
Test status
Simulation time	201096997 ps
CPU time	3.88 seconds
Started	Apr 30 03:48:22 PM PDT 24
Finished	Apr 30 03:48:26 PM PDT 24
Peak memory	241832 kb
Host	smart-fdd80187-5ba1-4f4e-a0c2-752cbd7c4178
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1643188632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1643188632
Directory	/workspace/187.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.3694575721
Short name	T588
Test name
Test status
Simulation time	138153898 ps
CPU time	5.76 seconds
Started	Apr 30 03:48:22 PM PDT 24
Finished	Apr 30 03:48:28 PM PDT 24
Peak memory	241304 kb
Host	smart-67734982-5685-4019-af47-31c4eea81b08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3694575721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.3694575721
Directory	/workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/188.otp_ctrl_init_fail.213090083
Short name	T170
Test name
Test status
Simulation time	501758243 ps
CPU time	3.99 seconds
Started	Apr 30 03:48:23 PM PDT 24
Finished	Apr 30 03:48:28 PM PDT 24
Peak memory	241720 kb
Host	smart-a70b8b3b-4704-43bb-bf66-19b8b117c249
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=213090083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.213090083
Directory	/workspace/188.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.901361748
Short name	T703
Test name
Test status
Simulation time	229199972 ps
CPU time	12.18 seconds
Started	Apr 30 03:48:20 PM PDT 24
Finished	Apr 30 03:48:33 PM PDT 24
Peak memory	241228 kb
Host	smart-d25c8ddc-e604-4c42-bdc3-4dce00a1610f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=901361748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.901361748
Directory	/workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/189.otp_ctrl_init_fail.3841226364
Short name	T808
Test name
Test status
Simulation time	175652483 ps
CPU time	4.82 seconds
Started	Apr 30 03:48:25 PM PDT 24
Finished	Apr 30 03:48:30 PM PDT 24
Peak memory	241372 kb
Host	smart-2d9abbc8-42d1-4d51-97ac-c321fa23c86d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3841226364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.3841226364
Directory	/workspace/189.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.2608879374
Short name	T1018
Test name
Test status
Simulation time	520388893 ps
CPU time	3.65 seconds
Started	Apr 30 03:48:24 PM PDT 24
Finished	Apr 30 03:48:28 PM PDT 24
Peak memory	247916 kb
Host	smart-90fd9884-8a3f-478b-8d03-dbddc6f8e090
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608879374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.2608879374
Directory	/workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/19.otp_ctrl_alert_test.2827875965
Short name	T428
Test name
Test status
Simulation time	94907807 ps
CPU time	1.79 seconds
Started	Apr 30 03:42:34 PM PDT 24
Finished	Apr 30 03:42:36 PM PDT 24
Peak memory	240084 kb
Host	smart-cda027e4-fe37-4e0a-8b66-12a632ee94bf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827875965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.2827875965
Directory	/workspace/19.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.otp_ctrl_check_fail.686668372
Short name	T114
Test name
Test status
Simulation time	580398657 ps
CPU time	12.04 seconds
Started	Apr 30 03:42:26 PM PDT 24
Finished	Apr 30 03:42:38 PM PDT 24
Peak memory	248008 kb
Host	smart-0e02eeb6-32e2-4d38-ad3d-d61c48734daa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=686668372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.686668372
Directory	/workspace/19.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/19.otp_ctrl_dai_errs.3404321267
Short name	T496
Test name
Test status
Simulation time	13382204900 ps
CPU time	36.62 seconds
Started	Apr 30 03:42:29 PM PDT 24
Finished	Apr 30 03:43:06 PM PDT 24
Peak memory	244484 kb
Host	smart-0287cde2-d141-48f5-8fc8-7dc8e9f6466c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404321267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.3404321267
Directory	/workspace/19.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/19.otp_ctrl_dai_lock.3704984981
Short name	T457
Test name
Test status
Simulation time	850975492 ps
CPU time	8.17 seconds
Started	Apr 30 03:42:28 PM PDT 24
Finished	Apr 30 03:42:36 PM PDT 24
Peak memory	241312 kb
Host	smart-2715141f-6013-4d36-aa34-7bfd803ecbd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3704984981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.3704984981
Directory	/workspace/19.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/19.otp_ctrl_init_fail.1817353406
Short name	T1188
Test name
Test status
Simulation time	151607196 ps
CPU time	3.97 seconds
Started	Apr 30 03:42:26 PM PDT 24
Finished	Apr 30 03:42:31 PM PDT 24
Peak memory	241496 kb
Host	smart-121e6813-a79a-47af-84e0-9e3bb35a95b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1817353406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.1817353406
Directory	/workspace/19.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/19.otp_ctrl_macro_errs.2664781872
Short name	T368
Test name
Test status
Simulation time	1134562137 ps
CPU time	13.57 seconds
Started	Apr 30 03:42:50 PM PDT 24
Finished	Apr 30 03:43:05 PM PDT 24
Peak memory	241420 kb
Host	smart-09a59f29-1cc2-483d-8581-8ff4a81058fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2664781872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.2664781872
Directory	/workspace/19.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/19.otp_ctrl_parallel_key_req.1382971207
Short name	T862
Test name
Test status
Simulation time	2812445876 ps
CPU time	33.99 seconds
Started	Apr 30 03:42:28 PM PDT 24
Finished	Apr 30 03:43:02 PM PDT 24
Peak memory	242312 kb
Host	smart-e4667b96-1f47-47b3-b4ae-71ad0040112b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382971207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.1382971207
Directory	/workspace/19.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.2614375366
Short name	T843
Test name
Test status
Simulation time	474797636 ps
CPU time	4.7 seconds
Started	Apr 30 03:42:27 PM PDT 24
Finished	Apr 30 03:42:32 PM PDT 24
Peak memory	241696 kb
Host	smart-3c0e6552-5e72-455c-9c5d-f0eb179c3552
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2614375366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.2614375366
Directory	/workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/19.otp_ctrl_parallel_lc_req.2360524
Short name	T400
Test name
Test status
Simulation time	1011999828 ps
CPU time	14.91 seconds
Started	Apr 30 03:42:27 PM PDT 24
Finished	Apr 30 03:42:43 PM PDT 24
Peak memory	241412 kb
Host	smart-677eada7-7764-401b-8fce-457f9ea01d0b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2360524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2360524
Directory	/workspace/19.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/19.otp_ctrl_regwen.2336184829
Short name	T1159
Test name
Test status
Simulation time	330107335 ps
CPU time	4.79 seconds
Started	Apr 30 03:42:33 PM PDT 24
Finished	Apr 30 03:42:39 PM PDT 24
Peak memory	241340 kb
Host	smart-d8a0a1f2-62c9-48d1-b5ed-6e45d7aa9277
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2336184829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.2336184829
Directory	/workspace/19.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/19.otp_ctrl_smoke.1107713256
Short name	T322
Test name
Test status
Simulation time	614703579 ps
CPU time	7.48 seconds
Started	Apr 30 03:42:50 PM PDT 24
Finished	Apr 30 03:42:58 PM PDT 24
Peak memory	247632 kb
Host	smart-5b6f8487-53e1-409c-836e-aa9647d4238a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107713256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.1107713256
Directory	/workspace/19.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.3486827256
Short name	T940
Test name
Test status
Simulation time	198524496778 ps
CPU time	1007.61 seconds
Started	Apr 30 03:42:37 PM PDT 24
Finished	Apr 30 03:59:25 PM PDT 24
Peak memory	276804 kb
Host	smart-59b8cd78-3911-4fb6-a6f0-e3a20f228dfd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486827256 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.3486827256
Directory	/workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.otp_ctrl_test_access.2847003436
Short name	T402
Test name
Test status
Simulation time	8986336300 ps
CPU time	22.17 seconds
Started	Apr 30 03:42:32 PM PDT 24
Finished	Apr 30 03:42:54 PM PDT 24
Peak memory	242468 kb
Host	smart-8881f850-6677-40a6-b25b-3ca3bf8dc487
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847003436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.2847003436
Directory	/workspace/19.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/190.otp_ctrl_init_fail.2258932410
Short name	T820
Test name
Test status
Simulation time	148155539 ps
CPU time	4.05 seconds
Started	Apr 30 03:48:21 PM PDT 24
Finished	Apr 30 03:48:26 PM PDT 24
Peak memory	241680 kb
Host	smart-7f28f8ed-8ef1-42f4-8c69-ba6bff923048
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258932410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.2258932410
Directory	/workspace/190.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.3663854352
Short name	T1093
Test name
Test status
Simulation time	1188054483 ps
CPU time	29.99 seconds
Started	Apr 30 03:48:21 PM PDT 24
Finished	Apr 30 03:48:51 PM PDT 24
Peak memory	241356 kb
Host	smart-7878ce59-feb6-47bc-baa2-ca6fd6bcd543
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3663854352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3663854352
Directory	/workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/191.otp_ctrl_init_fail.83848454
Short name	T1124
Test name
Test status
Simulation time	398586932 ps
CPU time	4.35 seconds
Started	Apr 30 03:48:22 PM PDT 24
Finished	Apr 30 03:48:27 PM PDT 24
Peak memory	241652 kb
Host	smart-5027903c-3ad0-4caf-a75f-4dfc905c5c7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83848454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.83848454
Directory	/workspace/191.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.67239198
Short name	T513
Test name
Test status
Simulation time	183460335 ps
CPU time	7.3 seconds
Started	Apr 30 03:48:20 PM PDT 24
Finished	Apr 30 03:48:28 PM PDT 24
Peak memory	241688 kb
Host	smart-925a36b3-6e53-4b71-96da-5ac5e895a117
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67239198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.67239198
Directory	/workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/192.otp_ctrl_init_fail.2004378823
Short name	T1170
Test name
Test status
Simulation time	152815588 ps
CPU time	4 seconds
Started	Apr 30 03:48:21 PM PDT 24
Finished	Apr 30 03:48:26 PM PDT 24
Peak memory	241668 kb
Host	smart-a8b58055-055c-4799-8853-413ee0a35ee8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2004378823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2004378823
Directory	/workspace/192.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.3598741511
Short name	T937
Test name
Test status
Simulation time	237573952 ps
CPU time	5.95 seconds
Started	Apr 30 03:48:21 PM PDT 24
Finished	Apr 30 03:48:28 PM PDT 24
Peak memory	241732 kb
Host	smart-cd0a0f61-3b7a-499a-b09b-31aed47319b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3598741511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.3598741511
Directory	/workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/193.otp_ctrl_init_fail.1670403443
Short name	T166
Test name
Test status
Simulation time	438355284 ps
CPU time	3.34 seconds
Started	Apr 30 03:48:20 PM PDT 24
Finished	Apr 30 03:48:24 PM PDT 24
Peak memory	241784 kb
Host	smart-92e7056b-f32a-4a8b-8a50-58f55b4a3cd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1670403443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.1670403443
Directory	/workspace/193.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.1657918969
Short name	T241
Test name
Test status
Simulation time	1931590215 ps
CPU time	14.2 seconds
Started	Apr 30 03:48:29 PM PDT 24
Finished	Apr 30 03:48:44 PM PDT 24
Peak memory	241540 kb
Host	smart-b836b02f-472f-4a69-a355-3d95e1907f2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657918969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.1657918969
Directory	/workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/194.otp_ctrl_init_fail.945123707
Short name	T30
Test name
Test status
Simulation time	284517549 ps
CPU time	4.29 seconds
Started	Apr 30 03:48:26 PM PDT 24
Finished	Apr 30 03:48:31 PM PDT 24
Peak memory	241348 kb
Host	smart-95882a51-cb75-451d-a2e4-5ddafe2720f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945123707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.945123707
Directory	/workspace/194.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.3750371888
Short name	T600
Test name
Test status
Simulation time	752068278 ps
CPU time	5.2 seconds
Started	Apr 30 03:48:26 PM PDT 24
Finished	Apr 30 03:48:32 PM PDT 24
Peak memory	241224 kb
Host	smart-2ee1c72a-6856-48f5-8e21-a32d063c6976
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3750371888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.3750371888
Directory	/workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/195.otp_ctrl_init_fail.482153423
Short name	T1029
Test name
Test status
Simulation time	116939243 ps
CPU time	4.18 seconds
Started	Apr 30 03:48:27 PM PDT 24
Finished	Apr 30 03:48:32 PM PDT 24
Peak memory	241704 kb
Host	smart-7874bb68-7e60-4a09-82d7-640fac3f9a8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482153423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.482153423
Directory	/workspace/195.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.4019545698
Short name	T1066
Test name
Test status
Simulation time	3642701048 ps
CPU time	28.82 seconds
Started	Apr 30 03:48:28 PM PDT 24
Finished	Apr 30 03:48:57 PM PDT 24
Peak memory	248044 kb
Host	smart-9c4ff1f0-d4b7-49b6-afa7-b8362c62af52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4019545698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.4019545698
Directory	/workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/196.otp_ctrl_init_fail.3398234573
Short name	T497
Test name
Test status
Simulation time	142010138 ps
CPU time	4.04 seconds
Started	Apr 30 03:48:28 PM PDT 24
Finished	Apr 30 03:48:33 PM PDT 24
Peak memory	241336 kb
Host	smart-ab8e7f9f-3a60-4b2c-b908-0e6123bac9e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3398234573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.3398234573
Directory	/workspace/196.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.530870807
Short name	T961
Test name
Test status
Simulation time	228193120 ps
CPU time	4.53 seconds
Started	Apr 30 03:48:28 PM PDT 24
Finished	Apr 30 03:48:33 PM PDT 24
Peak memory	241348 kb
Host	smart-4caa2060-4706-4874-8a6d-d97a481f5e4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=530870807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.530870807
Directory	/workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/197.otp_ctrl_init_fail.3088772225
Short name	T736
Test name
Test status
Simulation time	173728613 ps
CPU time	4.18 seconds
Started	Apr 30 03:48:27 PM PDT 24
Finished	Apr 30 03:48:31 PM PDT 24
Peak memory	241728 kb
Host	smart-e629424b-b0bb-4d75-ba48-81b4a18ac0b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3088772225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3088772225
Directory	/workspace/197.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.1413981734
Short name	T758
Test name
Test status
Simulation time	1178431022 ps
CPU time	16.66 seconds
Started	Apr 30 03:48:26 PM PDT 24
Finished	Apr 30 03:48:43 PM PDT 24
Peak memory	241500 kb
Host	smart-f895f522-0057-4a7b-8595-108248eaa162
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413981734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1413981734
Directory	/workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/198.otp_ctrl_init_fail.3881045180
Short name	T148
Test name
Test status
Simulation time	185471575 ps
CPU time	4.57 seconds
Started	Apr 30 03:48:29 PM PDT 24
Finished	Apr 30 03:48:34 PM PDT 24
Peak memory	241404 kb
Host	smart-91e36283-81ff-4884-92c9-bbe4e5af4eea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881045180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.3881045180
Directory	/workspace/198.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.2474491269
Short name	T214
Test name
Test status
Simulation time	1569765071 ps
CPU time	11.91 seconds
Started	Apr 30 03:48:36 PM PDT 24
Finished	Apr 30 03:48:48 PM PDT 24
Peak memory	241820 kb
Host	smart-098e110e-8ec8-43ac-9151-7e77840865f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2474491269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2474491269
Directory	/workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/199.otp_ctrl_init_fail.2644941453
Short name	T131
Test name
Test status
Simulation time	180535877 ps
CPU time	3.12 seconds
Started	Apr 30 03:48:34 PM PDT 24
Finished	Apr 30 03:48:38 PM PDT 24
Peak memory	241608 kb
Host	smart-54d97f47-9359-4aeb-bb41-0935a98262d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2644941453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.2644941453
Directory	/workspace/199.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.1729184305
Short name	T683
Test name
Test status
Simulation time	162141032 ps
CPU time	3.25 seconds
Started	Apr 30 03:48:33 PM PDT 24
Finished	Apr 30 03:48:37 PM PDT 24
Peak memory	247868 kb
Host	smart-6a51aaf7-f8f5-4213-bf51-5544cb962c9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1729184305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.1729184305
Directory	/workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/2.otp_ctrl_alert_test.2940743883
Short name	T854
Test name
Test status
Simulation time	79878637 ps
CPU time	1.81 seconds
Started	Apr 30 03:40:12 PM PDT 24
Finished	Apr 30 03:40:14 PM PDT 24
Peak memory	240184 kb
Host	smart-79963971-81ff-4be6-8aa2-d8ad648a2c75
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940743883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2940743883
Directory	/workspace/2.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.otp_ctrl_background_chks.4133346816
Short name	T706
Test name
Test status
Simulation time	6104539382 ps
CPU time	38.16 seconds
Started	Apr 30 03:40:14 PM PDT 24
Finished	Apr 30 03:40:52 PM PDT 24
Peak memory	242584 kb
Host	smart-123c9b5c-b2f2-4f24-a40b-8aaa98107c53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4133346816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.4133346816
Directory	/workspace/2.otp_ctrl_background_chks/latest

Test location	/workspace/coverage/default/2.otp_ctrl_dai_errs.1078579576
Short name	T232
Test name
Test status
Simulation time	6784109670 ps
CPU time	59.14 seconds
Started	Apr 30 03:40:12 PM PDT 24
Finished	Apr 30 03:41:12 PM PDT 24
Peak memory	256740 kb
Host	smart-10bef8b7-e8a5-4822-a447-c242d52400bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1078579576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1078579576
Directory	/workspace/2.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/2.otp_ctrl_dai_lock.1662973170
Short name	T990
Test name
Test status
Simulation time	3683840852 ps
CPU time	27.37 seconds
Started	Apr 30 03:40:11 PM PDT 24
Finished	Apr 30 03:40:39 PM PDT 24
Peak memory	241392 kb
Host	smart-9e8aba51-44c2-4451-b929-a6a0f938f606
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1662973170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.1662973170
Directory	/workspace/2.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/2.otp_ctrl_init_fail.205092901
Short name	T491
Test name
Test status
Simulation time	342044141 ps
CPU time	3.72 seconds
Started	Apr 30 03:40:05 PM PDT 24
Finished	Apr 30 03:40:09 PM PDT 24
Peak memory	241316 kb
Host	smart-b0ecb4fd-f01b-4ba1-9233-b8f241cc6d1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205092901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.205092901
Directory	/workspace/2.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/2.otp_ctrl_macro_errs.102927507
Short name	T1194
Test name
Test status
Simulation time	2292576605 ps
CPU time	21.05 seconds
Started	Apr 30 03:40:12 PM PDT 24
Finished	Apr 30 03:40:33 PM PDT 24
Peak memory	241908 kb
Host	smart-a605e6ed-cac6-4fc2-8431-cd1e847d6afa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102927507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.102927507
Directory	/workspace/2.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/2.otp_ctrl_parallel_key_req.786534387
Short name	T550
Test name
Test status
Simulation time	1510157710 ps
CPU time	10.55 seconds
Started	Apr 30 03:40:12 PM PDT 24
Finished	Apr 30 03:40:23 PM PDT 24
Peak memory	241440 kb
Host	smart-6788f0cf-cfd3-4708-9b40-2dffaa3a2c47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786534387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.786534387
Directory	/workspace/2.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.1219032116
Short name	T657
Test name
Test status
Simulation time	1383128377 ps
CPU time	10.97 seconds
Started	Apr 30 03:40:14 PM PDT 24
Finished	Apr 30 03:40:25 PM PDT 24
Peak memory	241736 kb
Host	smart-b95b7a48-10b3-4cff-921e-3e6ff2ab6d49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1219032116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.1219032116
Directory	/workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/2.otp_ctrl_parallel_lc_req.3148084753
Short name	T978
Test name
Test status
Simulation time	404623802 ps
CPU time	10.24 seconds
Started	Apr 30 03:40:15 PM PDT 24
Finished	Apr 30 03:40:26 PM PDT 24
Peak memory	241384 kb
Host	smart-822505fa-b053-43d0-8084-13da83982981
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3148084753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.3148084753
Directory	/workspace/2.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/2.otp_ctrl_regwen.647698238
Short name	T395
Test name
Test status
Simulation time	2515081377 ps
CPU time	7.44 seconds
Started	Apr 30 03:40:12 PM PDT 24
Finished	Apr 30 03:40:20 PM PDT 24
Peak memory	241500 kb
Host	smart-a4ca36ec-b41d-4ce9-9568-a38cd5689440
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=647698238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.647698238
Directory	/workspace/2.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/2.otp_ctrl_sec_cm.3042645067
Short name	T21
Test name
Test status
Simulation time	24678468300 ps
CPU time	186.11 seconds
Started	Apr 30 03:40:15 PM PDT 24
Finished	Apr 30 03:43:22 PM PDT 24
Peak memory	270408 kb
Host	smart-6f991027-728a-4544-9bc8-561ef9651d8e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042645067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.3042645067
Directory	/workspace/2.otp_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.otp_ctrl_smoke.2887338668
Short name	T364
Test name
Test status
Simulation time	150801107 ps
CPU time	5.32 seconds
Started	Apr 30 03:40:07 PM PDT 24
Finished	Apr 30 03:40:13 PM PDT 24
Peak memory	241572 kb
Host	smart-80ca212a-416a-4245-addf-a3501e15528d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2887338668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.2887338668
Directory	/workspace/2.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.otp_ctrl_stress_all.3618500107
Short name	T1068
Test name
Test status
Simulation time	6456401713 ps
CPU time	55.65 seconds
Started	Apr 30 03:40:15 PM PDT 24
Finished	Apr 30 03:41:11 PM PDT 24
Peak memory	242516 kb
Host	smart-40c14737-71d8-4a6b-8d78-4e7ea82c416a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618500107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all. 3618500107
Directory	/workspace/2.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.otp_ctrl_test_access.1570790171
Short name	T1091
Test name
Test status
Simulation time	3161391643 ps
CPU time	37.35 seconds
Started	Apr 30 03:40:12 PM PDT 24
Finished	Apr 30 03:40:50 PM PDT 24
Peak memory	241436 kb
Host	smart-33c3f39a-bfe0-4a60-911a-397fd883dd08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570790171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.1570790171
Directory	/workspace/2.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/20.otp_ctrl_alert_test.2736338615
Short name	T963
Test name
Test status
Simulation time	630984549 ps
CPU time	1.79 seconds
Started	Apr 30 03:42:49 PM PDT 24
Finished	Apr 30 03:42:52 PM PDT 24
Peak memory	240168 kb
Host	smart-9c394c85-5310-4849-a985-7786e0479a2b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736338615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.2736338615
Directory	/workspace/20.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.otp_ctrl_check_fail.750192206
Short name	T37
Test name
Test status
Simulation time	670103395 ps
CPU time	18.88 seconds
Started	Apr 30 03:42:50 PM PDT 24
Finished	Apr 30 03:43:10 PM PDT 24
Peak memory	247944 kb
Host	smart-122801f6-19a5-4759-a76b-c31c4c2d24f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750192206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.750192206
Directory	/workspace/20.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/20.otp_ctrl_dai_errs.3937979102
Short name	T1020
Test name
Test status
Simulation time	221244513 ps
CPU time	12.28 seconds
Started	Apr 30 03:42:49 PM PDT 24
Finished	Apr 30 03:43:02 PM PDT 24
Peak memory	241576 kb
Host	smart-846c5fa7-07cf-4e97-9d1d-a59ed5da8681
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3937979102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.3937979102
Directory	/workspace/20.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/20.otp_ctrl_dai_lock.341594717
Short name	T755
Test name
Test status
Simulation time	22881047035 ps
CPU time	43.57 seconds
Started	Apr 30 03:42:33 PM PDT 24
Finished	Apr 30 03:43:18 PM PDT 24
Peak memory	241692 kb
Host	smart-112483df-ca84-4b4d-b2d9-6bf1f392d87d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=341594717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.341594717
Directory	/workspace/20.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/20.otp_ctrl_init_fail.3884493724
Short name	T578
Test name
Test status
Simulation time	173118489 ps
CPU time	4.65 seconds
Started	Apr 30 03:42:33 PM PDT 24
Finished	Apr 30 03:42:39 PM PDT 24
Peak memory	241420 kb
Host	smart-9e5fe2e9-0056-4e73-acf0-bfd687dd6a0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884493724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.3884493724
Directory	/workspace/20.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/20.otp_ctrl_macro_errs.2105570794
Short name	T581
Test name
Test status
Simulation time	336451345 ps
CPU time	7.75 seconds
Started	Apr 30 03:42:37 PM PDT 24
Finished	Apr 30 03:42:46 PM PDT 24
Peak memory	241476 kb
Host	smart-3e108fcb-fe79-40fd-9419-144d8c13c5b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2105570794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.2105570794
Directory	/workspace/20.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/20.otp_ctrl_parallel_key_req.3242112064
Short name	T1022
Test name
Test status
Simulation time	261373200 ps
CPU time	6.59 seconds
Started	Apr 30 03:42:39 PM PDT 24
Finished	Apr 30 03:42:46 PM PDT 24
Peak memory	241784 kb
Host	smart-92e725e5-7de5-4878-a245-e73cad7210e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3242112064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.3242112064
Directory	/workspace/20.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.4074623977
Short name	T163
Test name
Test status
Simulation time	284442529 ps
CPU time	3.89 seconds
Started	Apr 30 03:42:32 PM PDT 24
Finished	Apr 30 03:42:37 PM PDT 24
Peak memory	241536 kb
Host	smart-79049072-d50a-429e-b47e-81445341988a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074623977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.4074623977
Directory	/workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/20.otp_ctrl_parallel_lc_req.2937095248
Short name	T1143
Test name
Test status
Simulation time	544351688 ps
CPU time	14.36 seconds
Started	Apr 30 03:42:36 PM PDT 24
Finished	Apr 30 03:42:51 PM PDT 24
Peak memory	247956 kb
Host	smart-e13c3870-7b52-4113-9ec7-e0fee51bebdb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2937095248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.2937095248
Directory	/workspace/20.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/20.otp_ctrl_regwen.2919212953
Short name	T573
Test name
Test status
Simulation time	255919000 ps
CPU time	4.38 seconds
Started	Apr 30 03:42:37 PM PDT 24
Finished	Apr 30 03:42:42 PM PDT 24
Peak memory	241384 kb
Host	smart-83cf9f35-c207-4dce-a076-31f928dfe688
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2919212953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.2919212953
Directory	/workspace/20.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/20.otp_ctrl_smoke.4294054142
Short name	T452
Test name
Test status
Simulation time	234599255 ps
CPU time	5.3 seconds
Started	Apr 30 03:42:31 PM PDT 24
Finished	Apr 30 03:42:37 PM PDT 24
Peak memory	241312 kb
Host	smart-df625962-9b3a-4a2e-a717-f4c561a75163
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4294054142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.4294054142
Directory	/workspace/20.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.otp_ctrl_stress_all.3214742705
Short name	T744
Test name
Test status
Simulation time	9597101644 ps
CPU time	228.08 seconds
Started	Apr 30 03:42:42 PM PDT 24
Finished	Apr 30 03:46:30 PM PDT 24
Peak memory	249448 kb
Host	smart-eb7e7c24-c0d8-4aa1-9f48-c56377702039
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214742705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all .3214742705
Directory	/workspace/20.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.1309767836
Short name	T842
Test name
Test status
Simulation time	275678254260 ps
CPU time	1823.92 seconds
Started	Apr 30 03:42:49 PM PDT 24
Finished	Apr 30 04:13:14 PM PDT 24
Peak memory	376060 kb
Host	smart-e170c782-af16-4b53-914d-5dc0eb079147
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309767836 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.1309767836
Directory	/workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.otp_ctrl_test_access.2788404841
Short name	T460
Test name
Test status
Simulation time	9944289824 ps
CPU time	18.45 seconds
Started	Apr 30 03:42:39 PM PDT 24
Finished	Apr 30 03:42:58 PM PDT 24
Peak memory	242824 kb
Host	smart-9ff3d2aa-2cd9-463c-a1ff-04a25b436fad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2788404841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.2788404841
Directory	/workspace/20.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/200.otp_ctrl_init_fail.2504162988
Short name	T793
Test name
Test status
Simulation time	372184591 ps
CPU time	3.85 seconds
Started	Apr 30 03:48:34 PM PDT 24
Finished	Apr 30 03:48:39 PM PDT 24
Peak memory	241624 kb
Host	smart-84d87670-c237-4158-b76d-24242c56ead7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2504162988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.2504162988
Directory	/workspace/200.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/201.otp_ctrl_init_fail.272679440
Short name	T666
Test name
Test status
Simulation time	112321031 ps
CPU time	3.87 seconds
Started	Apr 30 03:48:35 PM PDT 24
Finished	Apr 30 03:48:39 PM PDT 24
Peak memory	241660 kb
Host	smart-988910d4-6f86-4e7b-94d1-f84eedbc0819
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272679440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.272679440
Directory	/workspace/201.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/202.otp_ctrl_init_fail.1304254858
Short name	T685
Test name
Test status
Simulation time	1768563047 ps
CPU time	3.76 seconds
Started	Apr 30 03:48:33 PM PDT 24
Finished	Apr 30 03:48:37 PM PDT 24
Peak memory	241384 kb
Host	smart-616e0b96-629b-4343-b445-1a9bf726937e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304254858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.1304254858
Directory	/workspace/202.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/203.otp_ctrl_init_fail.1358789995
Short name	T338
Test name
Test status
Simulation time	644525536 ps
CPU time	4.9 seconds
Started	Apr 30 03:48:35 PM PDT 24
Finished	Apr 30 03:48:41 PM PDT 24
Peak memory	241356 kb
Host	smart-0f85fc7a-9450-4e3c-a3b1-50e68c4fecd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1358789995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.1358789995
Directory	/workspace/203.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/204.otp_ctrl_init_fail.2649735580
Short name	T167
Test name
Test status
Simulation time	93609683 ps
CPU time	3.38 seconds
Started	Apr 30 03:48:36 PM PDT 24
Finished	Apr 30 03:48:40 PM PDT 24
Peak memory	241312 kb
Host	smart-65efe5b8-d285-481f-9f0a-cb5e081594cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2649735580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.2649735580
Directory	/workspace/204.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/205.otp_ctrl_init_fail.1841609074
Short name	T757
Test name
Test status
Simulation time	230567708 ps
CPU time	4.43 seconds
Started	Apr 30 03:48:34 PM PDT 24
Finished	Apr 30 03:48:39 PM PDT 24
Peak memory	241472 kb
Host	smart-d8c1c6ea-18ea-4ec0-a3ff-b93d977bb8b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1841609074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.1841609074
Directory	/workspace/205.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/206.otp_ctrl_init_fail.935243080
Short name	T327
Test name
Test status
Simulation time	90823724 ps
CPU time	2.81 seconds
Started	Apr 30 03:48:33 PM PDT 24
Finished	Apr 30 03:48:36 PM PDT 24
Peak memory	241604 kb
Host	smart-61552cfa-1b32-4ff0-971b-c23457e6c005
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935243080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.935243080
Directory	/workspace/206.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/207.otp_ctrl_init_fail.802581330
Short name	T986
Test name
Test status
Simulation time	1517103164 ps
CPU time	4.94 seconds
Started	Apr 30 03:48:34 PM PDT 24
Finished	Apr 30 03:48:39 PM PDT 24
Peak memory	241436 kb
Host	smart-8a73af20-3c56-42fb-9536-a35d603f0d34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802581330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.802581330
Directory	/workspace/207.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/208.otp_ctrl_init_fail.3281670968
Short name	T730
Test name
Test status
Simulation time	127366937 ps
CPU time	3.4 seconds
Started	Apr 30 03:48:34 PM PDT 24
Finished	Apr 30 03:48:38 PM PDT 24
Peak memory	241400 kb
Host	smart-28f5079a-aafb-4e00-8c0c-a3af288cae0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281670968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3281670968
Directory	/workspace/208.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/209.otp_ctrl_init_fail.295156352
Short name	T893
Test name
Test status
Simulation time	223330975 ps
CPU time	3.22 seconds
Started	Apr 30 03:48:42 PM PDT 24
Finished	Apr 30 03:48:46 PM PDT 24
Peak memory	241764 kb
Host	smart-9ac93f84-d3e5-46ae-8f81-384d80dd3eb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=295156352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.295156352
Directory	/workspace/209.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/21.otp_ctrl_alert_test.3535753073
Short name	T753
Test name
Test status
Simulation time	672334859 ps
CPU time	2.03 seconds
Started	Apr 30 03:42:45 PM PDT 24
Finished	Apr 30 03:42:47 PM PDT 24
Peak memory	240056 kb
Host	smart-3264ca23-818e-41a5-967e-2e12af0a2d14
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535753073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.3535753073
Directory	/workspace/21.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.otp_ctrl_dai_errs.701103486
Short name	T463
Test name
Test status
Simulation time	361003402 ps
CPU time	21.8 seconds
Started	Apr 30 03:42:41 PM PDT 24
Finished	Apr 30 03:43:03 PM PDT 24
Peak memory	241248 kb
Host	smart-bd2c7539-a54b-4306-be45-9bbc1107ab3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701103486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.701103486
Directory	/workspace/21.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/21.otp_ctrl_dai_lock.2564852475
Short name	T948
Test name
Test status
Simulation time	6609974041 ps
CPU time	10.86 seconds
Started	Apr 30 03:42:50 PM PDT 24
Finished	Apr 30 03:43:02 PM PDT 24
Peak memory	241392 kb
Host	smart-aeecc8f3-1a9c-4080-a959-64d9472a5ac2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2564852475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.2564852475
Directory	/workspace/21.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/21.otp_ctrl_init_fail.988894859
Short name	T953
Test name
Test status
Simulation time	1687739563 ps
CPU time	6.07 seconds
Started	Apr 30 03:42:37 PM PDT 24
Finished	Apr 30 03:42:44 PM PDT 24
Peak memory	241476 kb
Host	smart-a9e6350b-279b-4ef7-9b19-87c4840854c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=988894859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.988894859
Directory	/workspace/21.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/21.otp_ctrl_macro_errs.775917998
Short name	T908
Test name
Test status
Simulation time	3810499667 ps
CPU time	26.42 seconds
Started	Apr 30 03:42:39 PM PDT 24
Finished	Apr 30 03:43:06 PM PDT 24
Peak memory	248120 kb
Host	smart-4be50809-2007-4280-b3fc-bd705e69ec84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775917998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.775917998
Directory	/workspace/21.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/21.otp_ctrl_parallel_key_req.4280834945
Short name	T1059
Test name
Test status
Simulation time	1140791351 ps
CPU time	25.53 seconds
Started	Apr 30 03:42:44 PM PDT 24
Finished	Apr 30 03:43:10 PM PDT 24
Peak memory	241348 kb
Host	smart-fee23353-49cd-4ac4-ab95-88c4f86d4235
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280834945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.4280834945
Directory	/workspace/21.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.3325966707
Short name	T1130
Test name
Test status
Simulation time	253188640 ps
CPU time	11.51 seconds
Started	Apr 30 03:42:50 PM PDT 24
Finished	Apr 30 03:43:03 PM PDT 24
Peak memory	241308 kb
Host	smart-9e098f7a-42e4-4de0-9182-c3e3e9a31f9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325966707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.3325966707
Directory	/workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/21.otp_ctrl_parallel_lc_req.89305940
Short name	T149
Test name
Test status
Simulation time	464267762 ps
CPU time	15.21 seconds
Started	Apr 30 03:42:39 PM PDT 24
Finished	Apr 30 03:42:55 PM PDT 24
Peak memory	247900 kb
Host	smart-b026dd46-9859-426e-a1ca-97dc67e9f6bf
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=89305940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.89305940
Directory	/workspace/21.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/21.otp_ctrl_regwen.881401264
Short name	T787
Test name
Test status
Simulation time	273721417 ps
CPU time	5.21 seconds
Started	Apr 30 03:42:44 PM PDT 24
Finished	Apr 30 03:42:50 PM PDT 24
Peak memory	247876 kb
Host	smart-8f17af15-bbad-44ca-b2e4-9f818397c532
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=881401264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.881401264
Directory	/workspace/21.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/21.otp_ctrl_smoke.1349213966
Short name	T823
Test name
Test status
Simulation time	5186417155 ps
CPU time	12.16 seconds
Started	Apr 30 03:42:38 PM PDT 24
Finished	Apr 30 03:42:50 PM PDT 24
Peak memory	241516 kb
Host	smart-947b6e9b-8caa-4f33-8489-6c7c50d2ff93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349213966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.1349213966
Directory	/workspace/21.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.otp_ctrl_stress_all.1838173171
Short name	T213
Test name
Test status
Simulation time	19242552365 ps
CPU time	143.38 seconds
Started	Apr 30 03:42:43 PM PDT 24
Finished	Apr 30 03:45:07 PM PDT 24
Peak memory	256260 kb
Host	smart-c68d2a7e-9a6d-421b-ac3a-1e924fd69fe5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838173171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all .1838173171
Directory	/workspace/21.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.1314424323
Short name	T74
Test name
Test status
Simulation time	84931190998 ps
CPU time	1746.64 seconds
Started	Apr 30 03:42:42 PM PDT 24
Finished	Apr 30 04:11:49 PM PDT 24
Peak memory	487568 kb
Host	smart-92f3e94e-7e70-4cca-a254-33eca54a409f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314424323 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.1314424323
Directory	/workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.otp_ctrl_test_access.3873773597
Short name	T878
Test name
Test status
Simulation time	1962460218 ps
CPU time	31.66 seconds
Started	Apr 30 03:42:43 PM PDT 24
Finished	Apr 30 03:43:15 PM PDT 24
Peak memory	241444 kb
Host	smart-25619417-4a7f-47df-8582-e43a06018f39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3873773597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.3873773597
Directory	/workspace/21.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/210.otp_ctrl_init_fail.2692769734
Short name	T593
Test name
Test status
Simulation time	126264664 ps
CPU time	4.45 seconds
Started	Apr 30 03:48:43 PM PDT 24
Finished	Apr 30 03:48:48 PM PDT 24
Peak memory	241552 kb
Host	smart-3fe966f1-6dc7-475c-8888-44be75536c26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2692769734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.2692769734
Directory	/workspace/210.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/211.otp_ctrl_init_fail.790051966
Short name	T1156
Test name
Test status
Simulation time	172818969 ps
CPU time	3.93 seconds
Started	Apr 30 03:48:41 PM PDT 24
Finished	Apr 30 03:48:46 PM PDT 24
Peak memory	241440 kb
Host	smart-6918acd6-094e-485d-ac76-44efec5a4bbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=790051966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.790051966
Directory	/workspace/211.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/212.otp_ctrl_init_fail.3334226731
Short name	T62
Test name
Test status
Simulation time	353159587 ps
CPU time	4.66 seconds
Started	Apr 30 03:48:40 PM PDT 24
Finished	Apr 30 03:48:46 PM PDT 24
Peak memory	241776 kb
Host	smart-556b762e-cf56-412a-925f-f1ae14aa4503
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3334226731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.3334226731
Directory	/workspace/212.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/213.otp_ctrl_init_fail.2324925030
Short name	T1043
Test name
Test status
Simulation time	2180992429 ps
CPU time	6.5 seconds
Started	Apr 30 03:48:42 PM PDT 24
Finished	Apr 30 03:48:49 PM PDT 24
Peak memory	241536 kb
Host	smart-71feacc8-eb1d-4599-ad9b-bad002db0258
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2324925030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.2324925030
Directory	/workspace/213.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/214.otp_ctrl_init_fail.714812399
Short name	T738
Test name
Test status
Simulation time	153152726 ps
CPU time	4.41 seconds
Started	Apr 30 03:48:42 PM PDT 24
Finished	Apr 30 03:48:47 PM PDT 24
Peak memory	241436 kb
Host	smart-2876de28-f740-4030-8eb6-6ef281887f02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714812399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.714812399
Directory	/workspace/214.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/215.otp_ctrl_init_fail.692953912
Short name	T517
Test name
Test status
Simulation time	154956476 ps
CPU time	3.53 seconds
Started	Apr 30 03:48:42 PM PDT 24
Finished	Apr 30 03:48:46 PM PDT 24
Peak memory	241452 kb
Host	smart-4057b342-6a92-4f14-98b7-77f700bb834d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=692953912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.692953912
Directory	/workspace/215.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/216.otp_ctrl_init_fail.1224069412
Short name	T1185
Test name
Test status
Simulation time	168734060 ps
CPU time	3.66 seconds
Started	Apr 30 03:48:41 PM PDT 24
Finished	Apr 30 03:48:46 PM PDT 24
Peak memory	241356 kb
Host	smart-434671f4-a99a-494c-a582-9f7338cfb4b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1224069412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.1224069412
Directory	/workspace/216.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/217.otp_ctrl_init_fail.1605463901
Short name	T664
Test name
Test status
Simulation time	132913260 ps
CPU time	4.33 seconds
Started	Apr 30 03:48:41 PM PDT 24
Finished	Apr 30 03:48:47 PM PDT 24
Peak memory	241384 kb
Host	smart-b0d528b2-2f13-45d0-ac68-269ee0e3faee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605463901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.1605463901
Directory	/workspace/217.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/218.otp_ctrl_init_fail.2115725189
Short name	T1074
Test name
Test status
Simulation time	112185714 ps
CPU time	3.14 seconds
Started	Apr 30 03:48:41 PM PDT 24
Finished	Apr 30 03:48:45 PM PDT 24
Peak memory	241576 kb
Host	smart-599f363a-cf54-4aaf-99d8-e3112a0c44c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2115725189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.2115725189
Directory	/workspace/218.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/219.otp_ctrl_init_fail.2994154058
Short name	T508
Test name
Test status
Simulation time	137589866 ps
CPU time	3.82 seconds
Started	Apr 30 03:48:40 PM PDT 24
Finished	Apr 30 03:48:45 PM PDT 24
Peak memory	241696 kb
Host	smart-ba1c4a25-e8b7-436b-93b2-5340a85c1b97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2994154058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2994154058
Directory	/workspace/219.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/22.otp_ctrl_alert_test.3422417793
Short name	T499
Test name
Test status
Simulation time	158476346 ps
CPU time	1.86 seconds
Started	Apr 30 03:42:57 PM PDT 24
Finished	Apr 30 03:43:00 PM PDT 24
Peak memory	239900 kb
Host	smart-1189c12d-a947-4758-8ad1-efb7c36fa912
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422417793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.3422417793
Directory	/workspace/22.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.otp_ctrl_check_fail.1985004358
Short name	T52
Test name
Test status
Simulation time	23012750507 ps
CPU time	49.04 seconds
Started	Apr 30 03:42:49 PM PDT 24
Finished	Apr 30 03:43:39 PM PDT 24
Peak memory	248156 kb
Host	smart-bfadcfbf-aa2c-427a-b900-9ef5a679c065
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1985004358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.1985004358
Directory	/workspace/22.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/22.otp_ctrl_dai_errs.987110160
Short name	T528
Test name
Test status
Simulation time	3639099869 ps
CPU time	30.21 seconds
Started	Apr 30 03:42:50 PM PDT 24
Finished	Apr 30 03:43:22 PM PDT 24
Peak memory	245572 kb
Host	smart-3a453660-23e8-4de5-a130-e91ac28323d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=987110160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.987110160
Directory	/workspace/22.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/22.otp_ctrl_dai_lock.2223200945
Short name	T317
Test name
Test status
Simulation time	401689460 ps
CPU time	13.03 seconds
Started	Apr 30 03:42:49 PM PDT 24
Finished	Apr 30 03:43:03 PM PDT 24
Peak memory	241312 kb
Host	smart-6e9a35f8-30c6-44cf-b237-c581fa2ed299
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223200945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2223200945
Directory	/workspace/22.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/22.otp_ctrl_init_fail.934538263
Short name	T788
Test name
Test status
Simulation time	258349085 ps
CPU time	3.86 seconds
Started	Apr 30 03:42:44 PM PDT 24
Finished	Apr 30 03:42:48 PM PDT 24
Peak memory	241616 kb
Host	smart-d61d203e-142f-45ff-a655-f53c7fe99c36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=934538263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.934538263
Directory	/workspace/22.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/22.otp_ctrl_macro_errs.1267467776
Short name	T1176
Test name
Test status
Simulation time	1730641477 ps
CPU time	28.53 seconds
Started	Apr 30 03:42:51 PM PDT 24
Finished	Apr 30 03:43:20 PM PDT 24
Peak memory	246176 kb
Host	smart-4a8e73be-2684-477b-85de-28d9acc201a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1267467776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.1267467776
Directory	/workspace/22.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/22.otp_ctrl_parallel_key_req.3826435009
Short name	T537
Test name
Test status
Simulation time	1666703410 ps
CPU time	12.86 seconds
Started	Apr 30 03:42:49 PM PDT 24
Finished	Apr 30 03:43:04 PM PDT 24
Peak memory	241368 kb
Host	smart-5c86d0b2-5ed0-4e43-8e02-14c474d02049
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3826435009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.3826435009
Directory	/workspace/22.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.2896373448
Short name	T849
Test name
Test status
Simulation time	505452933 ps
CPU time	8.07 seconds
Started	Apr 30 03:42:49 PM PDT 24
Finished	Apr 30 03:42:58 PM PDT 24
Peak memory	241340 kb
Host	smart-67349805-b767-4bdd-be87-7fecf1d7f58f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896373448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.2896373448
Directory	/workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/22.otp_ctrl_parallel_lc_req.3537486676
Short name	T257
Test name
Test status
Simulation time	7358468803 ps
CPU time	16.08 seconds
Started	Apr 30 03:42:50 PM PDT 24
Finished	Apr 30 03:43:07 PM PDT 24
Peak memory	241408 kb
Host	smart-92d35729-6b75-4c73-ac4c-c69e5bbc72a6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3537486676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.3537486676
Directory	/workspace/22.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/22.otp_ctrl_regwen.2244230564
Short name	T794
Test name
Test status
Simulation time	186016166 ps
CPU time	4.55 seconds
Started	Apr 30 03:42:50 PM PDT 24
Finished	Apr 30 03:42:56 PM PDT 24
Peak memory	241332 kb
Host	smart-aeac2406-ffb2-416f-a81a-d0bc0a2e1382
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2244230564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.2244230564
Directory	/workspace/22.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/22.otp_ctrl_smoke.2224288032
Short name	T989
Test name
Test status
Simulation time	1999384838 ps
CPU time	7.28 seconds
Started	Apr 30 03:42:43 PM PDT 24
Finished	Apr 30 03:42:51 PM PDT 24
Peak memory	241368 kb
Host	smart-dbf93b68-3f1e-46bf-963a-a5c90251b075
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2224288032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.2224288032
Directory	/workspace/22.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.otp_ctrl_stress_all.1197273642
Short name	T1024
Test name
Test status
Simulation time	27177533666 ps
CPU time	212.15 seconds
Started	Apr 30 03:42:54 PM PDT 24
Finished	Apr 30 03:46:27 PM PDT 24
Peak memory	276480 kb
Host	smart-ce3e9dbc-c465-4924-ba3f-7cea92652f96
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197273642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all .1197273642
Directory	/workspace/22.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.2770721272
Short name	T164
Test name
Test status
Simulation time	52278485640 ps
CPU time	1403.59 seconds
Started	Apr 30 03:42:58 PM PDT 24
Finished	Apr 30 04:06:23 PM PDT 24
Peak memory	276888 kb
Host	smart-495246e5-d41b-4514-bbde-46d2dad73060
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770721272 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.2770721272
Directory	/workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/221.otp_ctrl_init_fail.3744785874
Short name	T927
Test name
Test status
Simulation time	347402922 ps
CPU time	4.98 seconds
Started	Apr 30 03:48:40 PM PDT 24
Finished	Apr 30 03:48:46 PM PDT 24
Peak memory	241748 kb
Host	smart-499e726a-ced5-4764-8e92-ce8246c6ddde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744785874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3744785874
Directory	/workspace/221.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/222.otp_ctrl_init_fail.2591072727
Short name	T691
Test name
Test status
Simulation time	2065814352 ps
CPU time	5 seconds
Started	Apr 30 03:48:39 PM PDT 24
Finished	Apr 30 03:48:44 PM PDT 24
Peak memory	241716 kb
Host	smart-ee7a0c24-e03e-43d3-bc77-79633fd15cd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591072727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.2591072727
Directory	/workspace/222.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/223.otp_ctrl_init_fail.3323518430
Short name	T165
Test name
Test status
Simulation time	1886039536 ps
CPU time	4.19 seconds
Started	Apr 30 03:48:41 PM PDT 24
Finished	Apr 30 03:48:46 PM PDT 24
Peak memory	241288 kb
Host	smart-a761c1d4-9a4e-48d5-b75c-d73c73a123d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3323518430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.3323518430
Directory	/workspace/223.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/224.otp_ctrl_init_fail.2550001525
Short name	T465
Test name
Test status
Simulation time	143273578 ps
CPU time	5.02 seconds
Started	Apr 30 03:48:40 PM PDT 24
Finished	Apr 30 03:48:45 PM PDT 24
Peak memory	241660 kb
Host	smart-4091ae6b-ccc5-44ff-a363-62a8ed434f83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2550001525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.2550001525
Directory	/workspace/224.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/225.otp_ctrl_init_fail.2569711892
Short name	T760
Test name
Test status
Simulation time	221677336 ps
CPU time	4.55 seconds
Started	Apr 30 03:48:40 PM PDT 24
Finished	Apr 30 03:48:46 PM PDT 24
Peak memory	241368 kb
Host	smart-b7cfbeb7-a602-4e5a-b1a9-8afb3ed258b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569711892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.2569711892
Directory	/workspace/225.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/226.otp_ctrl_init_fail.795029077
Short name	T690
Test name
Test status
Simulation time	130755885 ps
CPU time	3.6 seconds
Started	Apr 30 03:48:39 PM PDT 24
Finished	Apr 30 03:48:44 PM PDT 24
Peak memory	241368 kb
Host	smart-4be631f8-9457-402c-9548-409140870457
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=795029077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.795029077
Directory	/workspace/226.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/227.otp_ctrl_init_fail.1925178593
Short name	T972
Test name
Test status
Simulation time	196085699 ps
CPU time	5.28 seconds
Started	Apr 30 03:48:42 PM PDT 24
Finished	Apr 30 03:48:48 PM PDT 24
Peak memory	241400 kb
Host	smart-263308d5-afdf-48cd-9f9b-5f74f22c30ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925178593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.1925178593
Directory	/workspace/227.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/228.otp_ctrl_init_fail.1543187475
Short name	T84
Test name
Test status
Simulation time	356287883 ps
CPU time	4.71 seconds
Started	Apr 30 03:48:41 PM PDT 24
Finished	Apr 30 03:48:46 PM PDT 24
Peak memory	241384 kb
Host	smart-a3edd263-4e91-4039-a1c9-56deb456f5b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1543187475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1543187475
Directory	/workspace/228.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/229.otp_ctrl_init_fail.4055044744
Short name	T687
Test name
Test status
Simulation time	412749083 ps
CPU time	4.47 seconds
Started	Apr 30 03:48:39 PM PDT 24
Finished	Apr 30 03:48:44 PM PDT 24
Peak memory	241424 kb
Host	smart-662458af-5538-49c2-b1fc-9bf4fc8c301f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055044744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.4055044744
Directory	/workspace/229.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/23.otp_ctrl_alert_test.3169177851
Short name	T957
Test name
Test status
Simulation time	264873527 ps
CPU time	3.59 seconds
Started	Apr 30 03:43:00 PM PDT 24
Finished	Apr 30 03:43:04 PM PDT 24
Peak memory	240068 kb
Host	smart-54bee5d3-4f90-499b-8a7a-8df3653ec3ca
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169177851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.3169177851
Directory	/workspace/23.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.otp_ctrl_check_fail.4214624820
Short name	T871
Test name
Test status
Simulation time	1675914887 ps
CPU time	13.1 seconds
Started	Apr 30 03:42:55 PM PDT 24
Finished	Apr 30 03:43:09 PM PDT 24
Peak memory	241560 kb
Host	smart-0e0bd660-538c-4171-8a33-d1c0db666a64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4214624820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.4214624820
Directory	/workspace/23.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/23.otp_ctrl_dai_errs.552840772
Short name	T179
Test name
Test status
Simulation time	16543247740 ps
CPU time	45.66 seconds
Started	Apr 30 03:42:58 PM PDT 24
Finished	Apr 30 03:43:44 PM PDT 24
Peak memory	247696 kb
Host	smart-1265d5dd-7dad-47cc-bd6b-7fb46576cc32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=552840772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.552840772
Directory	/workspace/23.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/23.otp_ctrl_dai_lock.2064528966
Short name	T26
Test name
Test status
Simulation time	2522374558 ps
CPU time	16.81 seconds
Started	Apr 30 03:42:56 PM PDT 24
Finished	Apr 30 03:43:14 PM PDT 24
Peak memory	241504 kb
Host	smart-bf993a65-5cb1-4c3a-8cd6-0a5a0ea36e74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2064528966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.2064528966
Directory	/workspace/23.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/23.otp_ctrl_init_fail.3341916288
Short name	T621
Test name
Test status
Simulation time	162579094 ps
CPU time	3.26 seconds
Started	Apr 30 03:42:56 PM PDT 24
Finished	Apr 30 03:43:00 PM PDT 24
Peak memory	241372 kb
Host	smart-0049818b-95a1-4d9d-b62c-6042d265b20f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3341916288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.3341916288
Directory	/workspace/23.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/23.otp_ctrl_macro_errs.1141798514
Short name	T370
Test name
Test status
Simulation time	1718121365 ps
CPU time	33.68 seconds
Started	Apr 30 03:42:57 PM PDT 24
Finished	Apr 30 03:43:31 PM PDT 24
Peak memory	243736 kb
Host	smart-44d20bcf-169a-4d53-ada5-1c9cf8ea467e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1141798514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.1141798514
Directory	/workspace/23.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/23.otp_ctrl_parallel_key_req.385128258
Short name	T569
Test name
Test status
Simulation time	2535087566 ps
CPU time	31.54 seconds
Started	Apr 30 03:43:01 PM PDT 24
Finished	Apr 30 03:43:33 PM PDT 24
Peak memory	241780 kb
Host	smart-4697e2ab-a3d7-4cd3-a02e-248957335c46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=385128258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.385128258
Directory	/workspace/23.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.807235219
Short name	T328
Test name
Test status
Simulation time	162890340 ps
CPU time	8.69 seconds
Started	Apr 30 03:42:57 PM PDT 24
Finished	Apr 30 03:43:06 PM PDT 24
Peak memory	241620 kb
Host	smart-2e7d85f5-d323-44e8-b415-e05d68620a26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=807235219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.807235219
Directory	/workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/23.otp_ctrl_parallel_lc_req.4269072366
Short name	T254
Test name
Test status
Simulation time	972217435 ps
CPU time	20.02 seconds
Started	Apr 30 03:42:57 PM PDT 24
Finished	Apr 30 03:43:18 PM PDT 24
Peak memory	241328 kb
Host	smart-9470ed5a-ef6a-4460-aa9e-7aa79c403d72
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4269072366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.4269072366
Directory	/workspace/23.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/23.otp_ctrl_regwen.3504782475
Short name	T1122
Test name
Test status
Simulation time	277190516 ps
CPU time	9.71 seconds
Started	Apr 30 03:43:04 PM PDT 24
Finished	Apr 30 03:43:14 PM PDT 24
Peak memory	241664 kb
Host	smart-022d97b2-f3e7-4f11-aee6-dcfda17d1de4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3504782475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.3504782475
Directory	/workspace/23.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/23.otp_ctrl_smoke.418457064
Short name	T1100
Test name
Test status
Simulation time	156340215 ps
CPU time	4.68 seconds
Started	Apr 30 03:42:58 PM PDT 24
Finished	Apr 30 03:43:04 PM PDT 24
Peak memory	247952 kb
Host	smart-fc7b8198-b840-4adb-b609-580b10341889
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=418457064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.418457064
Directory	/workspace/23.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.otp_ctrl_stress_all.2726205607
Short name	T613
Test name
Test status
Simulation time	60919029842 ps
CPU time	153.1 seconds
Started	Apr 30 03:43:00 PM PDT 24
Finished	Apr 30 03:45:33 PM PDT 24
Peak memory	256260 kb
Host	smart-033d8507-c257-4b62-bdd2-3e28ed200d21
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726205607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all .2726205607
Directory	/workspace/23.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.2159829808
Short name	T18
Test name
Test status
Simulation time	109872715421 ps
CPU time	1738.86 seconds
Started	Apr 30 03:43:02 PM PDT 24
Finished	Apr 30 04:12:02 PM PDT 24
Peak memory	437296 kb
Host	smart-dcde8d47-00d3-4449-9b74-6bf340885b47
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159829808 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.2159829808
Directory	/workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.otp_ctrl_test_access.588760657
Short name	T456
Test name
Test status
Simulation time	955573487 ps
CPU time	11.6 seconds
Started	Apr 30 03:43:01 PM PDT 24
Finished	Apr 30 03:43:14 PM PDT 24
Peak memory	241640 kb
Host	smart-0e43efbe-3248-420a-b444-d5995539601b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=588760657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.588760657
Directory	/workspace/23.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/230.otp_ctrl_init_fail.2555718509
Short name	T870
Test name
Test status
Simulation time	1963614549 ps
CPU time	4.59 seconds
Started	Apr 30 03:48:47 PM PDT 24
Finished	Apr 30 03:48:52 PM PDT 24
Peak memory	241428 kb
Host	smart-029391d7-fca2-49d1-9bfc-0ccbb8de1563
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555718509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.2555718509
Directory	/workspace/230.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/231.otp_ctrl_init_fail.3815764557
Short name	T791
Test name
Test status
Simulation time	308405423 ps
CPU time	4.24 seconds
Started	Apr 30 03:48:47 PM PDT 24
Finished	Apr 30 03:48:52 PM PDT 24
Peak memory	241740 kb
Host	smart-fa95bcda-f62c-4387-bac6-09103dc7a829
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3815764557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3815764557
Directory	/workspace/231.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/232.otp_ctrl_init_fail.1616016396
Short name	T648
Test name
Test status
Simulation time	199116976 ps
CPU time	3.87 seconds
Started	Apr 30 03:48:48 PM PDT 24
Finished	Apr 30 03:48:53 PM PDT 24
Peak memory	241348 kb
Host	smart-2d9bdf12-d7b3-4c6b-96ba-fea5d687fd63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1616016396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.1616016396
Directory	/workspace/232.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/233.otp_ctrl_init_fail.2708435528
Short name	T128
Test name
Test status
Simulation time	634640142 ps
CPU time	5.06 seconds
Started	Apr 30 03:48:48 PM PDT 24
Finished	Apr 30 03:48:54 PM PDT 24
Peak memory	241548 kb
Host	smart-a1658acc-dc24-481c-8fa7-35219cd57999
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2708435528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.2708435528
Directory	/workspace/233.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/234.otp_ctrl_init_fail.1728921679
Short name	T785
Test name
Test status
Simulation time	344250929 ps
CPU time	4.31 seconds
Started	Apr 30 03:48:48 PM PDT 24
Finished	Apr 30 03:48:54 PM PDT 24
Peak memory	241356 kb
Host	smart-489d773c-8063-48df-8344-7a25c55291af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1728921679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.1728921679
Directory	/workspace/234.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/235.otp_ctrl_init_fail.1832981446
Short name	T336
Test name
Test status
Simulation time	405947025 ps
CPU time	4.14 seconds
Started	Apr 30 03:48:48 PM PDT 24
Finished	Apr 30 03:48:53 PM PDT 24
Peak memory	241380 kb
Host	smart-6df7e34f-5d0e-407a-bbf7-1cc0bce7eb59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832981446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.1832981446
Directory	/workspace/235.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/236.otp_ctrl_init_fail.2878025515
Short name	T589
Test name
Test status
Simulation time	125334440 ps
CPU time	4.07 seconds
Started	Apr 30 03:48:46 PM PDT 24
Finished	Apr 30 03:48:50 PM PDT 24
Peak memory	241292 kb
Host	smart-a964ee7f-6899-42e1-ad77-cad9bece7018
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878025515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2878025515
Directory	/workspace/236.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/237.otp_ctrl_init_fail.1495802617
Short name	T1076
Test name
Test status
Simulation time	141357889 ps
CPU time	3.79 seconds
Started	Apr 30 03:48:48 PM PDT 24
Finished	Apr 30 03:48:52 PM PDT 24
Peak memory	241752 kb
Host	smart-c2d2a4f5-d64a-4435-8c5b-cf6bbe965639
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1495802617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.1495802617
Directory	/workspace/237.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/238.otp_ctrl_init_fail.4188927009
Short name	T999
Test name
Test status
Simulation time	218095406 ps
CPU time	3.16 seconds
Started	Apr 30 03:48:49 PM PDT 24
Finished	Apr 30 03:48:53 PM PDT 24
Peak memory	241452 kb
Host	smart-00855778-4e72-4b8d-a442-8c82831f0a87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4188927009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.4188927009
Directory	/workspace/238.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/239.otp_ctrl_init_fail.4202018806
Short name	T824
Test name
Test status
Simulation time	328122071 ps
CPU time	4.81 seconds
Started	Apr 30 03:48:52 PM PDT 24
Finished	Apr 30 03:48:58 PM PDT 24
Peak memory	241748 kb
Host	smart-0e0da5bb-947a-4a50-bef2-658201810fc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4202018806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.4202018806
Directory	/workspace/239.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/24.otp_ctrl_alert_test.1437698357
Short name	T667
Test name
Test status
Simulation time	103381090 ps
CPU time	1.92 seconds
Started	Apr 30 03:43:07 PM PDT 24
Finished	Apr 30 03:43:10 PM PDT 24
Peak memory	239848 kb
Host	smart-d65784f9-785f-42d3-bb6c-38aee6fbbd2c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437698357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.1437698357
Directory	/workspace/24.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.otp_ctrl_check_fail.513812954
Short name	T242
Test name
Test status
Simulation time	2139808470 ps
CPU time	4.29 seconds
Started	Apr 30 03:43:02 PM PDT 24
Finished	Apr 30 03:43:07 PM PDT 24
Peak memory	247944 kb
Host	smart-61ba8eaf-2fc3-495b-a5a0-44896dffc5d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513812954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.513812954
Directory	/workspace/24.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/24.otp_ctrl_dai_errs.2503624549
Short name	T438
Test name
Test status
Simulation time	4897211010 ps
CPU time	24.96 seconds
Started	Apr 30 03:43:00 PM PDT 24
Finished	Apr 30 03:43:26 PM PDT 24
Peak memory	241508 kb
Host	smart-4c4e2ab2-04b9-4087-9c79-64d750f46e65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2503624549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.2503624549
Directory	/workspace/24.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/24.otp_ctrl_dai_lock.724978494
Short name	T120
Test name
Test status
Simulation time	3442644960 ps
CPU time	8.83 seconds
Started	Apr 30 03:43:00 PM PDT 24
Finished	Apr 30 03:43:10 PM PDT 24
Peak memory	241408 kb
Host	smart-061fdf9f-6a82-4df4-bf39-f577892e35ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724978494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.724978494
Directory	/workspace/24.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/24.otp_ctrl_init_fail.1022050973
Short name	T169
Test name
Test status
Simulation time	458537204 ps
CPU time	3.75 seconds
Started	Apr 30 03:42:57 PM PDT 24
Finished	Apr 30 03:43:02 PM PDT 24
Peak memory	241792 kb
Host	smart-5ae4e825-5349-4bac-ad0c-7b901e3bee22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022050973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.1022050973
Directory	/workspace/24.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/24.otp_ctrl_macro_errs.1169360061
Short name	T231
Test name
Test status
Simulation time	4653878457 ps
CPU time	58.32 seconds
Started	Apr 30 03:43:03 PM PDT 24
Finished	Apr 30 03:44:01 PM PDT 24
Peak memory	264560 kb
Host	smart-a8b3e973-1af6-44ba-a167-1b2c87e30da1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169360061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.1169360061
Directory	/workspace/24.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/24.otp_ctrl_parallel_key_req.2879249162
Short name	T680
Test name
Test status
Simulation time	1966907116 ps
CPU time	15.07 seconds
Started	Apr 30 03:43:01 PM PDT 24
Finished	Apr 30 03:43:16 PM PDT 24
Peak memory	241456 kb
Host	smart-c94a8da7-89a5-4ca8-a89b-3ef572c9540b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2879249162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.2879249162
Directory	/workspace/24.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.3500818566
Short name	T268
Test name
Test status
Simulation time	4234028693 ps
CPU time	20.09 seconds
Started	Apr 30 03:43:01 PM PDT 24
Finished	Apr 30 03:43:22 PM PDT 24
Peak memory	241592 kb
Host	smart-66383d7f-e94c-4e68-bc4e-a0a9f613f38b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3500818566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.3500818566
Directory	/workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/24.otp_ctrl_parallel_lc_req.925611422
Short name	T763
Test name
Test status
Simulation time	282729843 ps
CPU time	4.05 seconds
Started	Apr 30 03:43:00 PM PDT 24
Finished	Apr 30 03:43:05 PM PDT 24
Peak memory	241280 kb
Host	smart-b363cd59-665b-4aaf-a587-19f9c48477fc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=925611422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.925611422
Directory	/workspace/24.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/24.otp_ctrl_regwen.1969370781
Short name	T382
Test name
Test status
Simulation time	505366492 ps
CPU time	6.23 seconds
Started	Apr 30 03:43:07 PM PDT 24
Finished	Apr 30 03:43:13 PM PDT 24
Peak memory	241620 kb
Host	smart-1e45734f-8be3-4995-9be6-2e06660c8083
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1969370781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.1969370781
Directory	/workspace/24.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/24.otp_ctrl_smoke.1066828331
Short name	T1152
Test name
Test status
Simulation time	160336401 ps
CPU time	5.96 seconds
Started	Apr 30 03:43:01 PM PDT 24
Finished	Apr 30 03:43:07 PM PDT 24
Peak memory	241392 kb
Host	smart-e60600fc-23db-4a0d-a8b9-8ec4632bf949
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1066828331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.1066828331
Directory	/workspace/24.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.otp_ctrl_stress_all.3306036664
Short name	T1053
Test name
Test status
Simulation time	7764583560 ps
CPU time	12.63 seconds
Started	Apr 30 03:43:09 PM PDT 24
Finished	Apr 30 03:43:22 PM PDT 24
Peak memory	241000 kb
Host	smart-926a2d52-77c6-435f-b575-f6bf8f1cde39
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306036664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all .3306036664
Directory	/workspace/24.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.3848936550
Short name	T208
Test name
Test status
Simulation time	142226373867 ps
CPU time	2003.3 seconds
Started	Apr 30 03:43:06 PM PDT 24
Finished	Apr 30 04:16:30 PM PDT 24
Peak memory	350336 kb
Host	smart-f4fb4ac9-86a2-4561-988e-5d23ec8c010f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848936550 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.3848936550
Directory	/workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.otp_ctrl_test_access.3270377040
Short name	T1069
Test name
Test status
Simulation time	1520690885 ps
CPU time	17.03 seconds
Started	Apr 30 03:43:07 PM PDT 24
Finished	Apr 30 03:43:25 PM PDT 24
Peak memory	241308 kb
Host	smart-b3d35587-f1b1-4292-bebf-a73547a9672e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3270377040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.3270377040
Directory	/workspace/24.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/240.otp_ctrl_init_fail.3088437956
Short name	T625
Test name
Test status
Simulation time	131059145 ps
CPU time	3.21 seconds
Started	Apr 30 03:48:50 PM PDT 24
Finished	Apr 30 03:48:55 PM PDT 24
Peak memory	241344 kb
Host	smart-5c2e4053-b1e8-4c05-98d2-3c2c5afbadb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3088437956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.3088437956
Directory	/workspace/240.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/241.otp_ctrl_init_fail.23660130
Short name	T132
Test name
Test status
Simulation time	2089434049 ps
CPU time	4.31 seconds
Started	Apr 30 03:48:48 PM PDT 24
Finished	Apr 30 03:48:53 PM PDT 24
Peak memory	241776 kb
Host	smart-3ddbaf35-93db-4bca-83b1-8414ba69316f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=23660130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.23660130
Directory	/workspace/241.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/242.otp_ctrl_init_fail.2532993472
Short name	T632
Test name
Test status
Simulation time	515294183 ps
CPU time	4.36 seconds
Started	Apr 30 03:48:48 PM PDT 24
Finished	Apr 30 03:48:54 PM PDT 24
Peak memory	241396 kb
Host	smart-2ca4be6b-ed1c-4230-9c84-ccb334e9dbfe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532993472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.2532993472
Directory	/workspace/242.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/243.otp_ctrl_init_fail.1340010447
Short name	T917
Test name
Test status
Simulation time	1742288015 ps
CPU time	4.63 seconds
Started	Apr 30 03:48:55 PM PDT 24
Finished	Apr 30 03:49:00 PM PDT 24
Peak memory	241360 kb
Host	smart-9e300f59-0c76-438c-8deb-77071a5da819
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340010447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.1340010447
Directory	/workspace/243.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/244.otp_ctrl_init_fail.760688769
Short name	T117
Test name
Test status
Simulation time	1805720658 ps
CPU time	4.16 seconds
Started	Apr 30 03:48:55 PM PDT 24
Finished	Apr 30 03:49:00 PM PDT 24
Peak memory	241528 kb
Host	smart-8bd7553a-c4c5-408a-ae48-229eb21b6e50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=760688769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.760688769
Directory	/workspace/244.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/245.otp_ctrl_init_fail.3672027573
Short name	T1150
Test name
Test status
Simulation time	1868479240 ps
CPU time	6.79 seconds
Started	Apr 30 03:48:54 PM PDT 24
Finished	Apr 30 03:49:02 PM PDT 24
Peak memory	241516 kb
Host	smart-21e8c3e4-ef81-4a7b-87af-9cc867b576ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3672027573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.3672027573
Directory	/workspace/245.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/246.otp_ctrl_init_fail.2443637817
Short name	T1113
Test name
Test status
Simulation time	480686584 ps
CPU time	4.67 seconds
Started	Apr 30 03:48:56 PM PDT 24
Finished	Apr 30 03:49:01 PM PDT 24
Peak memory	241392 kb
Host	smart-357cd4f6-e6b6-42d8-b9bc-79be055b8c21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2443637817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.2443637817
Directory	/workspace/246.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/247.otp_ctrl_init_fail.1552072412
Short name	T172
Test name
Test status
Simulation time	282534752 ps
CPU time	3.75 seconds
Started	Apr 30 03:48:54 PM PDT 24
Finished	Apr 30 03:48:59 PM PDT 24
Peak memory	241404 kb
Host	smart-fc21bca7-2a98-4e76-befa-8b3d8955070d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1552072412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.1552072412
Directory	/workspace/247.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/249.otp_ctrl_init_fail.3071508072
Short name	T644
Test name
Test status
Simulation time	288053158 ps
CPU time	4.32 seconds
Started	Apr 30 03:48:55 PM PDT 24
Finished	Apr 30 03:49:00 PM PDT 24
Peak memory	241452 kb
Host	smart-63b13fc5-2740-478e-9a4d-1b2e281a8285
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071508072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.3071508072
Directory	/workspace/249.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/25.otp_ctrl_alert_test.1366898600
Short name	T363
Test name
Test status
Simulation time	91512787 ps
CPU time	1.87 seconds
Started	Apr 30 03:43:20 PM PDT 24
Finished	Apr 30 03:43:22 PM PDT 24
Peak memory	240228 kb
Host	smart-1f00ad86-4ddc-4961-afd1-5e1afae5d363
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366898600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.1366898600
Directory	/workspace/25.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.otp_ctrl_check_fail.691970765
Short name	T707
Test name
Test status
Simulation time	1185322879 ps
CPU time	7.68 seconds
Started	Apr 30 03:43:07 PM PDT 24
Finished	Apr 30 03:43:15 PM PDT 24
Peak memory	247960 kb
Host	smart-37b9bfa9-8134-455e-ac41-f0991270ff3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=691970765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.691970765
Directory	/workspace/25.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/25.otp_ctrl_dai_errs.762904791
Short name	T445
Test name
Test status
Simulation time	231158756 ps
CPU time	11.31 seconds
Started	Apr 30 03:43:08 PM PDT 24
Finished	Apr 30 03:43:19 PM PDT 24
Peak memory	241376 kb
Host	smart-6cd6ac52-4060-4bed-940f-0f97a1041e07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762904791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.762904791
Directory	/workspace/25.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/25.otp_ctrl_dai_lock.787252676
Short name	T1040
Test name
Test status
Simulation time	1201738728 ps
CPU time	13.31 seconds
Started	Apr 30 03:43:07 PM PDT 24
Finished	Apr 30 03:43:21 PM PDT 24
Peak memory	241348 kb
Host	smart-e69dea62-fe79-4954-8841-da1cbcbb55fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=787252676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.787252676
Directory	/workspace/25.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/25.otp_ctrl_init_fail.1003959667
Short name	T717
Test name
Test status
Simulation time	315081813 ps
CPU time	4.09 seconds
Started	Apr 30 03:43:07 PM PDT 24
Finished	Apr 30 03:43:12 PM PDT 24
Peak memory	241644 kb
Host	smart-4e37b042-69f2-453a-8b1a-720d8e058376
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003959667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.1003959667
Directory	/workspace/25.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/25.otp_ctrl_macro_errs.4253807784
Short name	T803
Test name
Test status
Simulation time	3467220074 ps
CPU time	21.84 seconds
Started	Apr 30 03:43:07 PM PDT 24
Finished	Apr 30 03:43:30 PM PDT 24
Peak memory	248148 kb
Host	smart-73b68c1c-6680-48ea-80d8-fc138ed5f362
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4253807784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.4253807784
Directory	/workspace/25.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/25.otp_ctrl_parallel_key_req.2775641192
Short name	T459
Test name
Test status
Simulation time	4256997083 ps
CPU time	14.76 seconds
Started	Apr 30 03:43:18 PM PDT 24
Finished	Apr 30 03:43:34 PM PDT 24
Peak memory	248052 kb
Host	smart-f82e1458-ce8d-464f-8a0e-711055e84f50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2775641192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.2775641192
Directory	/workspace/25.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.2544128365
Short name	T1051
Test name
Test status
Simulation time	1323251768 ps
CPU time	31.22 seconds
Started	Apr 30 03:43:07 PM PDT 24
Finished	Apr 30 03:43:39 PM PDT 24
Peak memory	241296 kb
Host	smart-4ad73695-5106-49b4-a1ee-31aac09cb46e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544128365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.2544128365
Directory	/workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/25.otp_ctrl_parallel_lc_req.2097545078
Short name	T1044
Test name
Test status
Simulation time	511380284 ps
CPU time	18.74 seconds
Started	Apr 30 03:43:07 PM PDT 24
Finished	Apr 30 03:43:27 PM PDT 24
Peak memory	247460 kb
Host	smart-27677e52-cd27-4b6a-bd08-8961ac41f251
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2097545078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.2097545078
Directory	/workspace/25.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/25.otp_ctrl_regwen.2402601330
Short name	T1114
Test name
Test status
Simulation time	216170813 ps
CPU time	6.24 seconds
Started	Apr 30 03:43:12 PM PDT 24
Finished	Apr 30 03:43:19 PM PDT 24
Peak memory	241676 kb
Host	smart-b4222f9b-fa7a-40a2-a279-ffd834f10097
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2402601330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.2402601330
Directory	/workspace/25.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/25.otp_ctrl_smoke.3917113779
Short name	T94
Test name
Test status
Simulation time	4789261684 ps
CPU time	9.6 seconds
Started	Apr 30 03:43:12 PM PDT 24
Finished	Apr 30 03:43:23 PM PDT 24
Peak memory	242052 kb
Host	smart-5c04fabe-c36b-4dbc-80a1-c6f83883c413
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3917113779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.3917113779
Directory	/workspace/25.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.otp_ctrl_test_access.4030675096
Short name	T101
Test name
Test status
Simulation time	2326701333 ps
CPU time	11.78 seconds
Started	Apr 30 03:43:13 PM PDT 24
Finished	Apr 30 03:43:25 PM PDT 24
Peak memory	241400 kb
Host	smart-0bff2bba-5e60-4c75-a45b-ab41a5cfbd24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4030675096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.4030675096
Directory	/workspace/25.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/250.otp_ctrl_init_fail.1682539804
Short name	T99
Test name
Test status
Simulation time	133385301 ps
CPU time	3.99 seconds
Started	Apr 30 03:48:55 PM PDT 24
Finished	Apr 30 03:48:59 PM PDT 24
Peak memory	241668 kb
Host	smart-6785838a-63a3-4e0a-b271-b66355bcfb0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1682539804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.1682539804
Directory	/workspace/250.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/251.otp_ctrl_init_fail.34223617
Short name	T144
Test name
Test status
Simulation time	113555322 ps
CPU time	4.49 seconds
Started	Apr 30 03:48:54 PM PDT 24
Finished	Apr 30 03:48:59 PM PDT 24
Peak memory	241400 kb
Host	smart-00856c7a-6f97-4da9-8ac7-7bf6bd4f4b84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34223617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.34223617
Directory	/workspace/251.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/252.otp_ctrl_init_fail.739858069
Short name	T693
Test name
Test status
Simulation time	401306116 ps
CPU time	4.39 seconds
Started	Apr 30 03:48:56 PM PDT 24
Finished	Apr 30 03:49:01 PM PDT 24
Peak memory	241280 kb
Host	smart-fd856542-75b3-452b-aa98-698863f1a458
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739858069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.739858069
Directory	/workspace/252.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/253.otp_ctrl_init_fail.4023309699
Short name	T737
Test name
Test status
Simulation time	201023545 ps
CPU time	4 seconds
Started	Apr 30 03:48:59 PM PDT 24
Finished	Apr 30 03:49:04 PM PDT 24
Peak memory	241384 kb
Host	smart-058ca7df-f7c4-40b0-8c26-41f67e252b40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023309699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.4023309699
Directory	/workspace/253.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/255.otp_ctrl_init_fail.112451517
Short name	T176
Test name
Test status
Simulation time	132489543 ps
CPU time	4.5 seconds
Started	Apr 30 03:48:54 PM PDT 24
Finished	Apr 30 03:48:59 PM PDT 24
Peak memory	241668 kb
Host	smart-7f56a4bc-e3b1-4610-ae57-2ba3a7c0f9e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112451517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.112451517
Directory	/workspace/255.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/256.otp_ctrl_init_fail.3988974445
Short name	T631
Test name
Test status
Simulation time	177691496 ps
CPU time	4.34 seconds
Started	Apr 30 03:48:55 PM PDT 24
Finished	Apr 30 03:49:00 PM PDT 24
Peak memory	241336 kb
Host	smart-113a7ca8-b69b-406d-94ea-d98ca3960f80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3988974445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.3988974445
Directory	/workspace/256.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/257.otp_ctrl_init_fail.4120322359
Short name	T1075
Test name
Test status
Simulation time	1719866957 ps
CPU time	5.48 seconds
Started	Apr 30 03:48:56 PM PDT 24
Finished	Apr 30 03:49:03 PM PDT 24
Peak memory	241348 kb
Host	smart-7c176e7f-5237-428c-8872-e4c9e5527da4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4120322359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.4120322359
Directory	/workspace/257.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/258.otp_ctrl_init_fail.834229674
Short name	T1105
Test name
Test status
Simulation time	152384874 ps
CPU time	4.34 seconds
Started	Apr 30 03:48:54 PM PDT 24
Finished	Apr 30 03:48:59 PM PDT 24
Peak memory	241656 kb
Host	smart-d687fed1-f4da-4e7b-872c-431722c17b82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834229674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.834229674
Directory	/workspace/258.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/259.otp_ctrl_init_fail.2568854568
Short name	T835
Test name
Test status
Simulation time	200874997 ps
CPU time	4.07 seconds
Started	Apr 30 03:48:54 PM PDT 24
Finished	Apr 30 03:48:58 PM PDT 24
Peak memory	241376 kb
Host	smart-23c87d21-e0ff-4ff1-bc6d-68c1f8a31bb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2568854568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.2568854568
Directory	/workspace/259.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/26.otp_ctrl_alert_test.2681813819
Short name	T429
Test name
Test status
Simulation time	172767363 ps
CPU time	1.77 seconds
Started	Apr 30 03:43:20 PM PDT 24
Finished	Apr 30 03:43:23 PM PDT 24
Peak memory	240068 kb
Host	smart-baee00c6-2586-4325-8bb9-47273ed8fafa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681813819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2681813819
Directory	/workspace/26.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.otp_ctrl_check_fail.908581486
Short name	T900
Test name
Test status
Simulation time	585712175 ps
CPU time	10.39 seconds
Started	Apr 30 03:43:13 PM PDT 24
Finished	Apr 30 03:43:24 PM PDT 24
Peak memory	241460 kb
Host	smart-0860bac6-1ea1-4c59-8c77-1b79efeb16a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=908581486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.908581486
Directory	/workspace/26.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/26.otp_ctrl_dai_errs.1248935252
Short name	T129
Test name
Test status
Simulation time	4747322535 ps
CPU time	21.39 seconds
Started	Apr 30 03:43:15 PM PDT 24
Finished	Apr 30 03:43:37 PM PDT 24
Peak memory	241532 kb
Host	smart-e2901344-7aa1-49ac-a990-1d48f9d6d2fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1248935252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.1248935252
Directory	/workspace/26.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/26.otp_ctrl_dai_lock.2863631405
Short name	T534
Test name
Test status
Simulation time	468420173 ps
CPU time	3.28 seconds
Started	Apr 30 03:43:15 PM PDT 24
Finished	Apr 30 03:43:19 PM PDT 24
Peak memory	241276 kb
Host	smart-f6491b3a-19ad-497e-ab98-ec8dc1b7bb99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863631405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.2863631405
Directory	/workspace/26.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/26.otp_ctrl_init_fail.1696820486
Short name	T502
Test name
Test status
Simulation time	339303507 ps
CPU time	4.11 seconds
Started	Apr 30 03:43:13 PM PDT 24
Finished	Apr 30 03:43:17 PM PDT 24
Peak memory	241696 kb
Host	smart-dd347d89-418a-4c9b-b06b-7f7e00f2ff1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1696820486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.1696820486
Directory	/workspace/26.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/26.otp_ctrl_macro_errs.2556258042
Short name	T697
Test name
Test status
Simulation time	1929707249 ps
CPU time	19.03 seconds
Started	Apr 30 03:43:15 PM PDT 24
Finished	Apr 30 03:43:35 PM PDT 24
Peak memory	243684 kb
Host	smart-37bbbb61-60ad-486e-8295-c9100cbbacca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2556258042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.2556258042
Directory	/workspace/26.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/26.otp_ctrl_parallel_key_req.583944994
Short name	T579
Test name
Test status
Simulation time	1373109663 ps
CPU time	36.02 seconds
Started	Apr 30 03:43:16 PM PDT 24
Finished	Apr 30 03:43:53 PM PDT 24
Peak memory	241536 kb
Host	smart-58780ee7-89e1-4ffd-a96a-f675ef733728
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=583944994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.583944994
Directory	/workspace/26.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.3388310243
Short name	T650
Test name
Test status
Simulation time	1380668260 ps
CPU time	3.99 seconds
Started	Apr 30 03:43:16 PM PDT 24
Finished	Apr 30 03:43:20 PM PDT 24
Peak memory	241200 kb
Host	smart-f41d013a-9a21-4261-b39d-333adbf550e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388310243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.3388310243
Directory	/workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/26.otp_ctrl_parallel_lc_req.2359559831
Short name	T251
Test name
Test status
Simulation time	1955288049 ps
CPU time	22.77 seconds
Started	Apr 30 03:43:14 PM PDT 24
Finished	Apr 30 03:43:37 PM PDT 24
Peak memory	247988 kb
Host	smart-d2525c71-b2ba-4e86-bcc4-67369ba5b3b3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2359559831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.2359559831
Directory	/workspace/26.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/26.otp_ctrl_regwen.3494390738
Short name	T1009
Test name
Test status
Simulation time	1733643326 ps
CPU time	5.25 seconds
Started	Apr 30 03:43:12 PM PDT 24
Finished	Apr 30 03:43:17 PM PDT 24
Peak memory	241252 kb
Host	smart-2ab81a62-8007-46d6-95fd-1bb7fc4df081
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3494390738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.3494390738
Directory	/workspace/26.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/26.otp_ctrl_smoke.2807209500
Short name	T739
Test name
Test status
Simulation time	182005228 ps
CPU time	5.11 seconds
Started	Apr 30 03:43:13 PM PDT 24
Finished	Apr 30 03:43:19 PM PDT 24
Peak memory	241524 kb
Host	smart-69d31ecd-7fe8-4f54-a6ef-963f4840ce90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2807209500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.2807209500
Directory	/workspace/26.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.otp_ctrl_stress_all.1720772838
Short name	T410
Test name
Test status
Simulation time	21247333696 ps
CPU time	163.27 seconds
Started	Apr 30 03:43:19 PM PDT 24
Finished	Apr 30 03:46:03 PM PDT 24
Peak memory	248140 kb
Host	smart-bada79b4-c666-434b-ab5a-818ecab0390d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720772838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all .1720772838
Directory	/workspace/26.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.3586763024
Short name	T229
Test name
Test status
Simulation time	107428044795 ps
CPU time	1945.86 seconds
Started	Apr 30 03:43:20 PM PDT 24
Finished	Apr 30 04:15:47 PM PDT 24
Peak memory	543208 kb
Host	smart-13901a5d-47bc-4c98-882d-65b1fd7325b8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586763024 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.3586763024
Directory	/workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.otp_ctrl_test_access.2170077185
Short name	T1128
Test name
Test status
Simulation time	401277223 ps
CPU time	5.09 seconds
Started	Apr 30 03:43:15 PM PDT 24
Finished	Apr 30 03:43:21 PM PDT 24
Peak memory	241216 kb
Host	smart-8dbdc889-3e32-4ec4-92dc-2821c5f89272
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2170077185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.2170077185
Directory	/workspace/26.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/260.otp_ctrl_init_fail.3724506984
Short name	T1026
Test name
Test status
Simulation time	564773581 ps
CPU time	3.72 seconds
Started	Apr 30 03:48:56 PM PDT 24
Finished	Apr 30 03:49:01 PM PDT 24
Peak memory	241776 kb
Host	smart-a624e6a4-6562-487b-b9f8-0445cd9f3bcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724506984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.3724506984
Directory	/workspace/260.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/261.otp_ctrl_init_fail.3708318754
Short name	T980
Test name
Test status
Simulation time	129455624 ps
CPU time	4.15 seconds
Started	Apr 30 03:49:02 PM PDT 24
Finished	Apr 30 03:49:07 PM PDT 24
Peak memory	241596 kb
Host	smart-24ed0865-a3aa-4e42-9953-13ff47d2f91d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708318754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.3708318754
Directory	/workspace/261.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/263.otp_ctrl_init_fail.1067648524
Short name	T1144
Test name
Test status
Simulation time	2701769262 ps
CPU time	7.4 seconds
Started	Apr 30 03:48:59 PM PDT 24
Finished	Apr 30 03:49:08 PM PDT 24
Peak memory	241468 kb
Host	smart-5ad0b9aa-fe24-4a59-bfb8-caa17190ebe0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067648524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.1067648524
Directory	/workspace/263.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/264.otp_ctrl_init_fail.4078328433
Short name	T1030
Test name
Test status
Simulation time	88087748 ps
CPU time	2.78 seconds
Started	Apr 30 03:49:01 PM PDT 24
Finished	Apr 30 03:49:05 PM PDT 24
Peak memory	241724 kb
Host	smart-41849ef3-5a14-44d0-b5e2-6f7ee4d23e20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078328433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.4078328433
Directory	/workspace/264.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/265.otp_ctrl_init_fail.2787822440
Short name	T1165
Test name
Test status
Simulation time	344357168 ps
CPU time	4.99 seconds
Started	Apr 30 03:49:01 PM PDT 24
Finished	Apr 30 03:49:07 PM PDT 24
Peak memory	241572 kb
Host	smart-1a1f0633-db7c-4a17-b535-de70f7193d0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2787822440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.2787822440
Directory	/workspace/265.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/266.otp_ctrl_init_fail.711499204
Short name	T202
Test name
Test status
Simulation time	413999953 ps
CPU time	3.82 seconds
Started	Apr 30 03:49:00 PM PDT 24
Finished	Apr 30 03:49:05 PM PDT 24
Peak memory	241816 kb
Host	smart-1acfcd95-1f98-47ea-8f84-afe25506d461
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=711499204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.711499204
Directory	/workspace/266.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/267.otp_ctrl_init_fail.2200081623
Short name	T539
Test name
Test status
Simulation time	277558707 ps
CPU time	5.64 seconds
Started	Apr 30 03:48:59 PM PDT 24
Finished	Apr 30 03:49:05 PM PDT 24
Peak memory	241320 kb
Host	smart-68ff6693-e729-47cd-8327-7dfa23fff9e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2200081623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.2200081623
Directory	/workspace/267.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/268.otp_ctrl_init_fail.2664656959
Short name	T715
Test name
Test status
Simulation time	325413658 ps
CPU time	4.73 seconds
Started	Apr 30 03:49:01 PM PDT 24
Finished	Apr 30 03:49:07 PM PDT 24
Peak memory	241740 kb
Host	smart-878f6308-bdc1-4105-85c0-89b1443ff4f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2664656959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.2664656959
Directory	/workspace/268.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/269.otp_ctrl_init_fail.3320937370
Short name	T160
Test name
Test status
Simulation time	309672865 ps
CPU time	5.37 seconds
Started	Apr 30 03:49:01 PM PDT 24
Finished	Apr 30 03:49:08 PM PDT 24
Peak memory	241664 kb
Host	smart-faf87bd7-0927-4067-ac1d-3c7213d837eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3320937370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.3320937370
Directory	/workspace/269.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/27.otp_ctrl_alert_test.1633598122
Short name	T1
Test name
Test status
Simulation time	555240577 ps
CPU time	5.34 seconds
Started	Apr 30 03:43:27 PM PDT 24
Finished	Apr 30 03:43:33 PM PDT 24
Peak memory	240228 kb
Host	smart-bf8b3d2e-fe72-4bf3-b426-ad45c847c4a9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633598122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.1633598122
Directory	/workspace/27.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.otp_ctrl_dai_errs.1144752053
Short name	T455
Test name
Test status
Simulation time	477336476 ps
CPU time	14.33 seconds
Started	Apr 30 03:43:21 PM PDT 24
Finished	Apr 30 03:43:36 PM PDT 24
Peak memory	241224 kb
Host	smart-84dda6fc-2520-4796-80b5-48bc01c80a0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1144752053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1144752053
Directory	/workspace/27.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/27.otp_ctrl_dai_lock.1438598472
Short name	T533
Test name
Test status
Simulation time	1874235058 ps
CPU time	22.92 seconds
Started	Apr 30 03:43:22 PM PDT 24
Finished	Apr 30 03:43:46 PM PDT 24
Peak memory	241348 kb
Host	smart-89fb0317-5325-4720-a1ad-6a6b6e453127
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1438598472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.1438598472
Directory	/workspace/27.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/27.otp_ctrl_init_fail.3110544370
Short name	T157
Test name
Test status
Simulation time	1558772275 ps
CPU time	4.62 seconds
Started	Apr 30 03:43:24 PM PDT 24
Finished	Apr 30 03:43:29 PM PDT 24
Peak memory	241396 kb
Host	smart-90072d21-80e0-4ba8-83b8-53ff7334e57e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3110544370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3110544370
Directory	/workspace/27.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/27.otp_ctrl_macro_errs.1344325023
Short name	T168
Test name
Test status
Simulation time	2208423948 ps
CPU time	41.6 seconds
Started	Apr 30 03:43:22 PM PDT 24
Finished	Apr 30 03:44:04 PM PDT 24
Peak memory	247160 kb
Host	smart-247e9297-2d32-4d77-9c56-d177ab47f174
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1344325023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.1344325023
Directory	/workspace/27.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/27.otp_ctrl_parallel_key_req.3448509060
Short name	T921
Test name
Test status
Simulation time	616432010 ps
CPU time	21.68 seconds
Started	Apr 30 03:43:21 PM PDT 24
Finished	Apr 30 03:43:44 PM PDT 24
Peak memory	241688 kb
Host	smart-61b696b5-72de-4b47-bb60-4be42c6bb077
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3448509060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.3448509060
Directory	/workspace/27.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.3908860316
Short name	T780
Test name
Test status
Simulation time	143415025 ps
CPU time	5.83 seconds
Started	Apr 30 03:43:25 PM PDT 24
Finished	Apr 30 03:43:31 PM PDT 24
Peak memory	241212 kb
Host	smart-15ebe6db-cdd4-49f8-8f75-7d7986c4102d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3908860316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3908860316
Directory	/workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/27.otp_ctrl_parallel_lc_req.4023511299
Short name	T555
Test name
Test status
Simulation time	15045356165 ps
CPU time	39.43 seconds
Started	Apr 30 03:43:27 PM PDT 24
Finished	Apr 30 03:44:07 PM PDT 24
Peak memory	248092 kb
Host	smart-ab10b3dc-c74a-44bd-b46c-eec5dd230752
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4023511299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.4023511299
Directory	/workspace/27.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/27.otp_ctrl_regwen.939332096
Short name	T506
Test name
Test status
Simulation time	208954995 ps
CPU time	4.25 seconds
Started	Apr 30 03:43:22 PM PDT 24
Finished	Apr 30 03:43:27 PM PDT 24
Peak memory	241608 kb
Host	smart-cf785253-395f-43ff-add9-adfd61f41e09
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=939332096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.939332096
Directory	/workspace/27.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/27.otp_ctrl_smoke.3353942866
Short name	T764
Test name
Test status
Simulation time	339030971 ps
CPU time	4.34 seconds
Started	Apr 30 03:43:21 PM PDT 24
Finished	Apr 30 03:43:27 PM PDT 24
Peak memory	241356 kb
Host	smart-1223c711-ca5b-438d-88c4-616d7404db38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3353942866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.3353942866
Directory	/workspace/27.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.otp_ctrl_stress_all.3502737442
Short name	T1164
Test name
Test status
Simulation time	2477469753 ps
CPU time	33.76 seconds
Started	Apr 30 03:43:29 PM PDT 24
Finished	Apr 30 03:44:03 PM PDT 24
Peak memory	242312 kb
Host	smart-e713d3e1-49c4-42d6-aef0-b3ef69e79e62
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502737442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all .3502737442
Directory	/workspace/27.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.4256634317
Short name	T281
Test name
Test status
Simulation time	79315008025 ps
CPU time	491.84 seconds
Started	Apr 30 03:43:31 PM PDT 24
Finished	Apr 30 03:51:43 PM PDT 24
Peak memory	300432 kb
Host	smart-daa09074-9ccd-47ad-807b-113cb6b8aa8c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256634317 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.4256634317
Directory	/workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.otp_ctrl_test_access.1731069648
Short name	T159
Test name
Test status
Simulation time	1534337932 ps
CPU time	17.43 seconds
Started	Apr 30 03:43:21 PM PDT 24
Finished	Apr 30 03:43:39 PM PDT 24
Peak memory	241592 kb
Host	smart-b2fdd40c-ef99-4a63-acec-ff38dc9647cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1731069648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.1731069648
Directory	/workspace/27.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/270.otp_ctrl_init_fail.1727010932
Short name	T545
Test name
Test status
Simulation time	169946998 ps
CPU time	4.57 seconds
Started	Apr 30 03:49:00 PM PDT 24
Finished	Apr 30 03:49:05 PM PDT 24
Peak memory	241288 kb
Host	smart-bfc8e526-50e8-4a54-81dd-aec980bb96a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1727010932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.1727010932
Directory	/workspace/270.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/271.otp_ctrl_init_fail.3089247164
Short name	T535
Test name
Test status
Simulation time	98714812 ps
CPU time	3.8 seconds
Started	Apr 30 03:49:06 PM PDT 24
Finished	Apr 30 03:49:10 PM PDT 24
Peak memory	241284 kb
Host	smart-914bf2a3-ad44-46f8-8b99-bd0789734d38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3089247164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3089247164
Directory	/workspace/271.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/272.otp_ctrl_init_fail.4008547231
Short name	T776
Test name
Test status
Simulation time	282742392 ps
CPU time	5.22 seconds
Started	Apr 30 03:49:01 PM PDT 24
Finished	Apr 30 03:49:08 PM PDT 24
Peak memory	241260 kb
Host	smart-347b9859-c5aa-4da2-94e8-672b7fcbb3fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4008547231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.4008547231
Directory	/workspace/272.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/273.otp_ctrl_init_fail.3419158845
Short name	T1110
Test name
Test status
Simulation time	647436913 ps
CPU time	5.07 seconds
Started	Apr 30 03:49:01 PM PDT 24
Finished	Apr 30 03:49:07 PM PDT 24
Peak memory	241440 kb
Host	smart-3c654290-6130-4fb7-92b7-fcfb73f3a098
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3419158845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.3419158845
Directory	/workspace/273.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/274.otp_ctrl_init_fail.2906478273
Short name	T586
Test name
Test status
Simulation time	222558308 ps
CPU time	4.25 seconds
Started	Apr 30 03:49:06 PM PDT 24
Finished	Apr 30 03:49:11 PM PDT 24
Peak memory	241324 kb
Host	smart-d3794eea-317e-4633-952a-75c9e51bad6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2906478273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2906478273
Directory	/workspace/274.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/275.otp_ctrl_init_fail.811884403
Short name	T574
Test name
Test status
Simulation time	100387936 ps
CPU time	3.1 seconds
Started	Apr 30 03:48:59 PM PDT 24
Finished	Apr 30 03:49:03 PM PDT 24
Peak memory	241688 kb
Host	smart-ceaa731b-927e-4bdb-bca9-d3b48cc2afd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=811884403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.811884403
Directory	/workspace/275.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/276.otp_ctrl_init_fail.1829795757
Short name	T523
Test name
Test status
Simulation time	152756617 ps
CPU time	3.73 seconds
Started	Apr 30 03:49:06 PM PDT 24
Finished	Apr 30 03:49:10 PM PDT 24
Peak memory	241460 kb
Host	smart-5e7a4368-f949-48d3-b3fc-c03ac2bc5e4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1829795757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.1829795757
Directory	/workspace/276.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/277.otp_ctrl_init_fail.2980909100
Short name	T722
Test name
Test status
Simulation time	337927725 ps
CPU time	4.37 seconds
Started	Apr 30 03:49:00 PM PDT 24
Finished	Apr 30 03:49:05 PM PDT 24
Peak memory	241776 kb
Host	smart-90938cca-8cf1-4dc9-b3e5-b89ed2c0bed9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2980909100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.2980909100
Directory	/workspace/277.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/278.otp_ctrl_init_fail.985133382
Short name	T1175
Test name
Test status
Simulation time	224957468 ps
CPU time	4.07 seconds
Started	Apr 30 03:48:59 PM PDT 24
Finished	Apr 30 03:49:04 PM PDT 24
Peak memory	241384 kb
Host	smart-ae839312-808b-4678-aad3-effecba67d6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985133382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.985133382
Directory	/workspace/278.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/279.otp_ctrl_init_fail.3797378064
Short name	T200
Test name
Test status
Simulation time	258298866 ps
CPU time	3.87 seconds
Started	Apr 30 03:49:03 PM PDT 24
Finished	Apr 30 03:49:07 PM PDT 24
Peak memory	241772 kb
Host	smart-33eac330-1a0a-4a9d-9b92-b2c7640ef01c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797378064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.3797378064
Directory	/workspace/279.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/28.otp_ctrl_alert_test.3089600147
Short name	T1060
Test name
Test status
Simulation time	96626875 ps
CPU time	1.69 seconds
Started	Apr 30 03:43:43 PM PDT 24
Finished	Apr 30 03:43:46 PM PDT 24
Peak memory	239720 kb
Host	smart-2ae8a976-af29-46a1-a1ed-fa79ad5c43de
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089600147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.3089600147
Directory	/workspace/28.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.otp_ctrl_check_fail.1836958368
Short name	T903
Test name
Test status
Simulation time	3814973502 ps
CPU time	9.23 seconds
Started	Apr 30 03:43:30 PM PDT 24
Finished	Apr 30 03:43:40 PM PDT 24
Peak memory	248152 kb
Host	smart-de1c054e-8fc4-4439-90a5-173da5e208eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1836958368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.1836958368
Directory	/workspace/28.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/28.otp_ctrl_dai_errs.2820950594
Short name	T426
Test name
Test status
Simulation time	1079606204 ps
CPU time	17.47 seconds
Started	Apr 30 03:43:29 PM PDT 24
Finished	Apr 30 03:43:46 PM PDT 24
Peak memory	241380 kb
Host	smart-d88c041d-35b7-4d9f-9ce1-b913586f5050
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820950594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.2820950594
Directory	/workspace/28.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/28.otp_ctrl_dai_lock.3776714792
Short name	T585
Test name
Test status
Simulation time	19101562877 ps
CPU time	36.3 seconds
Started	Apr 30 03:43:28 PM PDT 24
Finished	Apr 30 03:44:05 PM PDT 24
Peak memory	241724 kb
Host	smart-71a9f3fc-7149-4715-94f2-5b444e8d38ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3776714792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.3776714792
Directory	/workspace/28.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/28.otp_ctrl_init_fail.3577326504
Short name	T1151
Test name
Test status
Simulation time	437734823 ps
CPU time	3.74 seconds
Started	Apr 30 03:43:29 PM PDT 24
Finished	Apr 30 03:43:33 PM PDT 24
Peak memory	241524 kb
Host	smart-20d03599-7c00-4db2-ba10-afab1b951cd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577326504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.3577326504
Directory	/workspace/28.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/28.otp_ctrl_parallel_key_req.963251198
Short name	T540
Test name
Test status
Simulation time	953909430 ps
CPU time	19.23 seconds
Started	Apr 30 03:43:27 PM PDT 24
Finished	Apr 30 03:43:47 PM PDT 24
Peak memory	241300 kb
Host	smart-0491869e-fc91-4be5-8376-2dbd39d2a641
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963251198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.963251198
Directory	/workspace/28.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.4049363591
Short name	T108
Test name
Test status
Simulation time	316297973 ps
CPU time	7.88 seconds
Started	Apr 30 03:43:30 PM PDT 24
Finished	Apr 30 03:43:38 PM PDT 24
Peak memory	241296 kb
Host	smart-a0d4193a-cd74-43f6-9e87-6a5472612dff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4049363591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.4049363591
Directory	/workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/28.otp_ctrl_parallel_lc_req.3508421710
Short name	T590
Test name
Test status
Simulation time	1091535738 ps
CPU time	16.24 seconds
Started	Apr 30 03:43:33 PM PDT 24
Finished	Apr 30 03:43:49 PM PDT 24
Peak memory	241308 kb
Host	smart-b6ec8e25-bd70-4cb4-9926-b13c752a569e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3508421710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.3508421710
Directory	/workspace/28.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/28.otp_ctrl_regwen.3013698042
Short name	T572
Test name
Test status
Simulation time	207460688 ps
CPU time	3.35 seconds
Started	Apr 30 03:43:35 PM PDT 24
Finished	Apr 30 03:43:39 PM PDT 24
Peak memory	247844 kb
Host	smart-08d47f90-c381-43c9-a655-cb67e20bda08
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3013698042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.3013698042
Directory	/workspace/28.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/28.otp_ctrl_smoke.1019470535
Short name	T422
Test name
Test status
Simulation time	6761171811 ps
CPU time	14.54 seconds
Started	Apr 30 03:43:27 PM PDT 24
Finished	Apr 30 03:43:42 PM PDT 24
Peak memory	241668 kb
Host	smart-82bb5e99-ef02-46df-9069-514ed6681a7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1019470535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.1019470535
Directory	/workspace/28.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.otp_ctrl_stress_all.3596711701
Short name	T1079
Test name
Test status
Simulation time	5315656609 ps
CPU time	44.06 seconds
Started	Apr 30 03:43:35 PM PDT 24
Finished	Apr 30 03:44:19 PM PDT 24
Peak memory	244428 kb
Host	smart-55c3e43d-7d39-4ffa-a464-9c7283f281ee
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596711701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all .3596711701
Directory	/workspace/28.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.2958121258
Short name	T191
Test name
Test status
Simulation time	139741734454 ps
CPU time	877.7 seconds
Started	Apr 30 03:43:36 PM PDT 24
Finished	Apr 30 03:58:14 PM PDT 24
Peak memory	264584 kb
Host	smart-7948b3f9-1de5-4ff3-ac1e-bee82d0e82d8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958121258 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.2958121258
Directory	/workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.otp_ctrl_test_access.1792284641
Short name	T474
Test name
Test status
Simulation time	2446799749 ps
CPU time	24.32 seconds
Started	Apr 30 03:43:34 PM PDT 24
Finished	Apr 30 03:43:59 PM PDT 24
Peak memory	241924 kb
Host	smart-bd57ee5c-f1a9-4ef7-bd9f-ab71be64c30e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1792284641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.1792284641
Directory	/workspace/28.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/281.otp_ctrl_init_fail.146687818
Short name	T54
Test name
Test status
Simulation time	186125422 ps
CPU time	5.09 seconds
Started	Apr 30 03:49:02 PM PDT 24
Finished	Apr 30 03:49:08 PM PDT 24
Peak memory	241284 kb
Host	smart-90030023-bc35-4bd8-8560-805dac45ef46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=146687818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.146687818
Directory	/workspace/281.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/282.otp_ctrl_init_fail.1022981403
Short name	T762
Test name
Test status
Simulation time	2743954200 ps
CPU time	5.48 seconds
Started	Apr 30 03:49:01 PM PDT 24
Finished	Apr 30 03:49:08 PM PDT 24
Peak memory	241844 kb
Host	smart-59494a62-0621-40ff-980b-647246b8983a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022981403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.1022981403
Directory	/workspace/282.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/283.otp_ctrl_init_fail.3096419355
Short name	T1179
Test name
Test status
Simulation time	181292390 ps
CPU time	5.1 seconds
Started	Apr 30 03:49:07 PM PDT 24
Finished	Apr 30 03:49:13 PM PDT 24
Peak memory	241512 kb
Host	smart-ac80636a-799f-4eec-9ae2-9e01f7c25d1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3096419355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.3096419355
Directory	/workspace/283.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/284.otp_ctrl_init_fail.1352320293
Short name	T833
Test name
Test status
Simulation time	546076715 ps
CPU time	4.65 seconds
Started	Apr 30 03:49:06 PM PDT 24
Finished	Apr 30 03:49:12 PM PDT 24
Peak memory	241300 kb
Host	smart-9c76d527-8878-4abc-a241-6858810f8b03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1352320293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.1352320293
Directory	/workspace/284.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/285.otp_ctrl_init_fail.2008752031
Short name	T856
Test name
Test status
Simulation time	1745632245 ps
CPU time	3.85 seconds
Started	Apr 30 03:49:08 PM PDT 24
Finished	Apr 30 03:49:12 PM PDT 24
Peak memory	241688 kb
Host	smart-30cd0f87-70b8-4466-9449-fc3653f3f16e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2008752031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.2008752031
Directory	/workspace/285.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/286.otp_ctrl_init_fail.2178388302
Short name	T530
Test name
Test status
Simulation time	1949717316 ps
CPU time	5.9 seconds
Started	Apr 30 03:49:10 PM PDT 24
Finished	Apr 30 03:49:16 PM PDT 24
Peak memory	241524 kb
Host	smart-5cf98031-46af-4e76-8a0f-7fa670226820
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2178388302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.2178388302
Directory	/workspace/286.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/287.otp_ctrl_init_fail.2131248176
Short name	T935
Test name
Test status
Simulation time	1568444659 ps
CPU time	5.58 seconds
Started	Apr 30 03:49:08 PM PDT 24
Finished	Apr 30 03:49:14 PM PDT 24
Peak memory	241336 kb
Host	smart-4f1ba910-fafc-4e1e-beae-05462a198b52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2131248176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.2131248176
Directory	/workspace/287.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/288.otp_ctrl_init_fail.2272899286
Short name	T601
Test name
Test status
Simulation time	166359400 ps
CPU time	4.36 seconds
Started	Apr 30 03:49:10 PM PDT 24
Finished	Apr 30 03:49:15 PM PDT 24
Peak memory	241512 kb
Host	smart-70945385-b9bf-4fdd-8b6e-612052a47d0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2272899286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.2272899286
Directory	/workspace/288.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/289.otp_ctrl_init_fail.1376348116
Short name	T1087
Test name
Test status
Simulation time	111034139 ps
CPU time	3.62 seconds
Started	Apr 30 03:49:09 PM PDT 24
Finished	Apr 30 03:49:13 PM PDT 24
Peak memory	241264 kb
Host	smart-0eed80fa-6e20-4f1f-8527-8cf082f61ca2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1376348116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.1376348116
Directory	/workspace/289.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/29.otp_ctrl_alert_test.3610217533
Short name	T449
Test name
Test status
Simulation time	93490482 ps
CPU time	1.9 seconds
Started	Apr 30 03:43:43 PM PDT 24
Finished	Apr 30 03:43:45 PM PDT 24
Peak memory	239848 kb
Host	smart-7a991afa-a909-4dca-9047-12a8d5010ee7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610217533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3610217533
Directory	/workspace/29.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.otp_ctrl_check_fail.738600750
Short name	T115
Test name
Test status
Simulation time	1269941914 ps
CPU time	30.15 seconds
Started	Apr 30 03:43:41 PM PDT 24
Finished	Apr 30 03:44:12 PM PDT 24
Peak memory	241316 kb
Host	smart-900985e1-bfb1-44b9-97f1-6057b2f79dea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738600750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.738600750
Directory	/workspace/29.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/29.otp_ctrl_dai_errs.1188314350
Short name	T431
Test name
Test status
Simulation time	438026799 ps
CPU time	11.83 seconds
Started	Apr 30 03:43:44 PM PDT 24
Finished	Apr 30 03:43:56 PM PDT 24
Peak memory	241620 kb
Host	smart-6be63dcb-c817-45db-957d-98bd1b092f84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188314350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.1188314350
Directory	/workspace/29.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/29.otp_ctrl_dai_lock.1459080651
Short name	T1126
Test name
Test status
Simulation time	884133974 ps
CPU time	21.96 seconds
Started	Apr 30 03:43:42 PM PDT 24
Finished	Apr 30 03:44:05 PM PDT 24
Peak memory	241720 kb
Host	smart-51b649b7-d9f3-42ac-b355-f5a06b1b9481
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1459080651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.1459080651
Directory	/workspace/29.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/29.otp_ctrl_init_fail.2949961199
Short name	T124
Test name
Test status
Simulation time	582804835 ps
CPU time	4.19 seconds
Started	Apr 30 03:43:40 PM PDT 24
Finished	Apr 30 03:43:44 PM PDT 24
Peak memory	241332 kb
Host	smart-fae6bd64-2483-4758-b820-4ba629c5e2af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2949961199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.2949961199
Directory	/workspace/29.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/29.otp_ctrl_macro_errs.1809877765
Short name	T692
Test name
Test status
Simulation time	1723126653 ps
CPU time	15.84 seconds
Started	Apr 30 03:43:41 PM PDT 24
Finished	Apr 30 03:43:57 PM PDT 24
Peak memory	241440 kb
Host	smart-8497195e-a016-41a8-b80e-657223180928
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809877765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.1809877765
Directory	/workspace/29.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/29.otp_ctrl_parallel_key_req.736780855
Short name	T424
Test name
Test status
Simulation time	4414167469 ps
CPU time	31.01 seconds
Started	Apr 30 03:43:46 PM PDT 24
Finished	Apr 30 03:44:17 PM PDT 24
Peak memory	241972 kb
Host	smart-d76a8e6c-c06e-4992-9974-100836db0cfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736780855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.736780855
Directory	/workspace/29.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.2637390520
Short name	T269
Test name
Test status
Simulation time	327514437 ps
CPU time	7.39 seconds
Started	Apr 30 03:43:37 PM PDT 24
Finished	Apr 30 03:43:45 PM PDT 24
Peak memory	241412 kb
Host	smart-3d66e1a1-c3ac-462a-aef0-732a999db868
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637390520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.2637390520
Directory	/workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/29.otp_ctrl_parallel_lc_req.1566360838
Short name	T1036
Test name
Test status
Simulation time	392858993 ps
CPU time	9.67 seconds
Started	Apr 30 03:43:46 PM PDT 24
Finished	Apr 30 03:43:56 PM PDT 24
Peak memory	241280 kb
Host	smart-2fe537a2-745f-4ac6-80fe-57c627462bf6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1566360838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1566360838
Directory	/workspace/29.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/29.otp_ctrl_regwen.3244977979
Short name	T619
Test name
Test status
Simulation time	126346600 ps
CPU time	5.02 seconds
Started	Apr 30 03:43:42 PM PDT 24
Finished	Apr 30 03:43:48 PM PDT 24
Peak memory	241312 kb
Host	smart-e1c07460-eb9b-4685-adfc-330ddd427d79
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3244977979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.3244977979
Directory	/workspace/29.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/29.otp_ctrl_smoke.3110863723
Short name	T855
Test name
Test status
Simulation time	153115579 ps
CPU time	4.11 seconds
Started	Apr 30 03:43:40 PM PDT 24
Finished	Apr 30 03:43:45 PM PDT 24
Peak memory	241592 kb
Host	smart-0052499d-8801-4284-810b-719e3c8a0df4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3110863723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.3110863723
Directory	/workspace/29.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.otp_ctrl_stress_all.3404220889
Short name	T538
Test name
Test status
Simulation time	867546376 ps
CPU time	18.98 seconds
Started	Apr 30 03:43:39 PM PDT 24
Finished	Apr 30 03:43:58 PM PDT 24
Peak memory	240872 kb
Host	smart-64c2d011-d109-4570-a349-924140b2f60c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404220889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all .3404220889
Directory	/workspace/29.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.3804110513
Short name	T360
Test name
Test status
Simulation time	29135456238 ps
CPU time	779.12 seconds
Started	Apr 30 03:43:39 PM PDT 24
Finished	Apr 30 03:56:39 PM PDT 24
Peak memory	330240 kb
Host	smart-23f5fa75-d996-4ff8-bf8c-4d071a01244b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804110513 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.3804110513
Directory	/workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.otp_ctrl_test_access.668495411
Short name	T677
Test name
Test status
Simulation time	26608407337 ps
CPU time	59.72 seconds
Started	Apr 30 03:43:40 PM PDT 24
Finished	Apr 30 03:44:41 PM PDT 24
Peak memory	241608 kb
Host	smart-c4c95d2d-81a6-4e8a-a618-635b4fdaf85a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=668495411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.668495411
Directory	/workspace/29.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/290.otp_ctrl_init_fail.2753503547
Short name	T1158
Test name
Test status
Simulation time	211689321 ps
CPU time	4.7 seconds
Started	Apr 30 03:49:08 PM PDT 24
Finished	Apr 30 03:49:13 PM PDT 24
Peak memory	241388 kb
Host	smart-73c23871-0bd5-4338-911c-627d1edee71b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2753503547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.2753503547
Directory	/workspace/290.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/291.otp_ctrl_init_fail.2495983767
Short name	T973
Test name
Test status
Simulation time	114383579 ps
CPU time	4.26 seconds
Started	Apr 30 03:49:08 PM PDT 24
Finished	Apr 30 03:49:13 PM PDT 24
Peak memory	241192 kb
Host	smart-708997ee-1ced-4041-a958-4c3d26d5fd0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2495983767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.2495983767
Directory	/workspace/291.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/292.otp_ctrl_init_fail.474995179
Short name	T175
Test name
Test status
Simulation time	233441176 ps
CPU time	4.35 seconds
Started	Apr 30 03:49:09 PM PDT 24
Finished	Apr 30 03:49:14 PM PDT 24
Peak memory	241464 kb
Host	smart-7c82559e-5033-4e6a-b227-36a0340df37f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=474995179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.474995179
Directory	/workspace/292.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/293.otp_ctrl_init_fail.2956773478
Short name	T48
Test name
Test status
Simulation time	365466825 ps
CPU time	4.72 seconds
Started	Apr 30 03:49:08 PM PDT 24
Finished	Apr 30 03:49:14 PM PDT 24
Peak memory	241420 kb
Host	smart-d8663358-982f-4d17-a8d8-1ef13c545cea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2956773478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.2956773478
Directory	/workspace/293.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/294.otp_ctrl_init_fail.2300573649
Short name	T544
Test name
Test status
Simulation time	200618172 ps
CPU time	4.71 seconds
Started	Apr 30 03:49:08 PM PDT 24
Finished	Apr 30 03:49:14 PM PDT 24
Peak memory	241444 kb
Host	smart-292ff4ae-82f2-46bb-b659-c8f3f83a5b67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2300573649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.2300573649
Directory	/workspace/294.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/295.otp_ctrl_init_fail.3793132210
Short name	T563
Test name
Test status
Simulation time	195111990 ps
CPU time	4.56 seconds
Started	Apr 30 03:49:07 PM PDT 24
Finished	Apr 30 03:49:13 PM PDT 24
Peak memory	241388 kb
Host	smart-365e8901-1fe4-40f3-8e95-952ff0658aa5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3793132210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.3793132210
Directory	/workspace/295.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/296.otp_ctrl_init_fail.834423123
Short name	T1021
Test name
Test status
Simulation time	88736949 ps
CPU time	3.06 seconds
Started	Apr 30 03:49:11 PM PDT 24
Finished	Apr 30 03:49:14 PM PDT 24
Peak memory	241428 kb
Host	smart-084348a3-4e81-4899-a161-2b3e5bb12a3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834423123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.834423123
Directory	/workspace/296.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/297.otp_ctrl_init_fail.1570321697
Short name	T122
Test name
Test status
Simulation time	110494252 ps
CPU time	3.34 seconds
Started	Apr 30 03:49:10 PM PDT 24
Finished	Apr 30 03:49:14 PM PDT 24
Peak memory	241488 kb
Host	smart-22c8335a-25f8-48d3-9b6b-6a8f5640407a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570321697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.1570321697
Directory	/workspace/297.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/298.otp_ctrl_init_fail.1533627717
Short name	T930
Test name
Test status
Simulation time	158223178 ps
CPU time	3.69 seconds
Started	Apr 30 03:49:07 PM PDT 24
Finished	Apr 30 03:49:12 PM PDT 24
Peak memory	241352 kb
Host	smart-17db8526-7e79-4916-8dbe-e64769068c5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1533627717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.1533627717
Directory	/workspace/298.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/299.otp_ctrl_init_fail.4126759162
Short name	T1038
Test name
Test status
Simulation time	302851862 ps
CPU time	4.12 seconds
Started	Apr 30 03:49:07 PM PDT 24
Finished	Apr 30 03:49:12 PM PDT 24
Peak memory	241752 kb
Host	smart-2cf26306-e63d-4f56-8b60-ef917759ec4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126759162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.4126759162
Directory	/workspace/299.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/3.otp_ctrl_alert_test.1873513035
Short name	T1147
Test name
Test status
Simulation time	66219732 ps
CPU time	1.87 seconds
Started	Apr 30 03:40:16 PM PDT 24
Finished	Apr 30 03:40:18 PM PDT 24
Peak memory	240132 kb
Host	smart-e0eece52-a90a-4eaf-981d-b668638659ae
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873513035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.1873513035
Directory	/workspace/3.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.otp_ctrl_background_chks.2880872260
Short name	T1157
Test name
Test status
Simulation time	789659684 ps
CPU time	22.72 seconds
Started	Apr 30 03:40:16 PM PDT 24
Finished	Apr 30 03:40:39 PM PDT 24
Peak memory	241560 kb
Host	smart-dfaa02da-6f5e-4e53-93a5-84925bc750f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2880872260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.2880872260
Directory	/workspace/3.otp_ctrl_background_chks/latest

Test location	/workspace/coverage/default/3.otp_ctrl_check_fail.4172175304
Short name	T1090
Test name
Test status
Simulation time	710615168 ps
CPU time	8.4 seconds
Started	Apr 30 03:40:16 PM PDT 24
Finished	Apr 30 03:40:25 PM PDT 24
Peak memory	241360 kb
Host	smart-0289848f-2dfd-463f-9321-f6d2ff3b3add
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4172175304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.4172175304
Directory	/workspace/3.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/3.otp_ctrl_dai_errs.2757871894
Short name	T775
Test name
Test status
Simulation time	1453480450 ps
CPU time	22.95 seconds
Started	Apr 30 03:40:15 PM PDT 24
Finished	Apr 30 03:40:38 PM PDT 24
Peak memory	241464 kb
Host	smart-e34b3b1c-47c6-4427-a90e-5983e329ca98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2757871894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.2757871894
Directory	/workspace/3.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/3.otp_ctrl_dai_lock.1223837301
Short name	T1010
Test name
Test status
Simulation time	430547560 ps
CPU time	13.2 seconds
Started	Apr 30 03:40:16 PM PDT 24
Finished	Apr 30 03:40:29 PM PDT 24
Peak memory	241360 kb
Host	smart-759a349a-c9df-42fd-9e31-989ad2a0e326
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1223837301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.1223837301
Directory	/workspace/3.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/3.otp_ctrl_init_fail.2609104603
Short name	T32
Test name
Test status
Simulation time	193196531 ps
CPU time	4.18 seconds
Started	Apr 30 03:40:16 PM PDT 24
Finished	Apr 30 03:40:21 PM PDT 24
Peak memory	241764 kb
Host	smart-f2d88644-a101-44a3-a8fb-a7ba83627dc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2609104603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.2609104603
Directory	/workspace/3.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/3.otp_ctrl_macro_errs.3549935312
Short name	T198
Test name
Test status
Simulation time	4119925303 ps
CPU time	17.34 seconds
Started	Apr 30 03:40:17 PM PDT 24
Finished	Apr 30 03:40:34 PM PDT 24
Peak memory	244076 kb
Host	smart-b50ac302-f7b4-490f-b8ce-56e5462c9b3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3549935312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.3549935312
Directory	/workspace/3.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/3.otp_ctrl_parallel_key_req.151317595
Short name	T437
Test name
Test status
Simulation time	650214827 ps
CPU time	5.9 seconds
Started	Apr 30 03:40:16 PM PDT 24
Finished	Apr 30 03:40:23 PM PDT 24
Peak memory	247916 kb
Host	smart-dde85c63-c0dd-4b8f-8442-816f35c19743
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=151317595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.151317595
Directory	/workspace/3.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.2257858883
Short name	T1028
Test name
Test status
Simulation time	235635131 ps
CPU time	3.67 seconds
Started	Apr 30 03:40:24 PM PDT 24
Finished	Apr 30 03:40:28 PM PDT 24
Peak memory	241432 kb
Host	smart-5e12fcb3-8010-44dc-87c1-51d9acef5850
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257858883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.2257858883
Directory	/workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/3.otp_ctrl_parallel_lc_req.1539867400
Short name	T731
Test name
Test status
Simulation time	4009649440 ps
CPU time	8.71 seconds
Started	Apr 30 03:40:15 PM PDT 24
Finished	Apr 30 03:40:24 PM PDT 24
Peak memory	241488 kb
Host	smart-08ec5153-888b-41e0-bf50-a010fe3351f7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1539867400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.1539867400
Directory	/workspace/3.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/3.otp_ctrl_regwen.3361183734
Short name	T392
Test name
Test status
Simulation time	495451704 ps
CPU time	4.36 seconds
Started	Apr 30 03:40:17 PM PDT 24
Finished	Apr 30 03:40:22 PM PDT 24
Peak memory	241628 kb
Host	smart-5fa186d2-9035-49c6-9067-58e132b47366
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3361183734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3361183734
Directory	/workspace/3.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/3.otp_ctrl_sec_cm.1266848186
Short name	T237
Test name
Test status
Simulation time	9323700198 ps
CPU time	176.22 seconds
Started	Apr 30 03:40:16 PM PDT 24
Finished	Apr 30 03:43:13 PM PDT 24
Peak memory	263420 kb
Host	smart-9ea5e16b-3cd0-408c-82ba-6ea780e5ee2d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266848186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1266848186
Directory	/workspace/3.otp_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.otp_ctrl_smoke.2188002249
Short name	T662
Test name
Test status
Simulation time	556912597 ps
CPU time	7.79 seconds
Started	Apr 30 03:40:11 PM PDT 24
Finished	Apr 30 03:40:19 PM PDT 24
Peak memory	241604 kb
Host	smart-07f29cd0-7909-488c-9fd0-1e2983b332ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2188002249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2188002249
Directory	/workspace/3.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.otp_ctrl_stress_all.1464359319
Short name	T796
Test name
Test status
Simulation time	60648814363 ps
CPU time	262.31 seconds
Started	Apr 30 03:40:15 PM PDT 24
Finished	Apr 30 03:44:38 PM PDT 24
Peak memory	256728 kb
Host	smart-292c4485-9fa9-4263-9f2e-dd40e5633fd5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464359319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all. 1464359319
Directory	/workspace/3.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.40150666
Short name	T19
Test name
Test status
Simulation time	1409856472232 ps
CPU time	1796 seconds
Started	Apr 30 03:40:16 PM PDT 24
Finished	Apr 30 04:10:13 PM PDT 24
Peak memory	435212 kb
Host	smart-84c73528-2791-4e88-a844-37abe22c52e1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40150666 -assert nopos tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.40150666
Directory	/workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.otp_ctrl_test_access.1629172230
Short name	T897
Test name
Test status
Simulation time	463377650 ps
CPU time	15.78 seconds
Started	Apr 30 03:40:15 PM PDT 24
Finished	Apr 30 03:40:32 PM PDT 24
Peak memory	241276 kb
Host	smart-2541a326-2fe0-46b0-b4f8-7c1d3f5e31eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629172230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.1629172230
Directory	/workspace/3.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/30.otp_ctrl_alert_test.4187907396
Short name	T1171
Test name
Test status
Simulation time	648579991 ps
CPU time	1.89 seconds
Started	Apr 30 03:43:45 PM PDT 24
Finished	Apr 30 03:43:48 PM PDT 24
Peak memory	240184 kb
Host	smart-58f92d02-a4ff-475b-8f0a-aedf4872f586
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187907396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.4187907396
Directory	/workspace/30.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.otp_ctrl_check_fail.3061521248
Short name	T134
Test name
Test status
Simulation time	1661766088 ps
CPU time	33.3 seconds
Started	Apr 30 03:43:47 PM PDT 24
Finished	Apr 30 03:44:21 PM PDT 24
Peak memory	247972 kb
Host	smart-c79284d5-ed69-4b1e-9e01-a46a8aa57d5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3061521248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.3061521248
Directory	/workspace/30.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/30.otp_ctrl_dai_errs.3163745001
Short name	T1041
Test name
Test status
Simulation time	568551773 ps
CPU time	16.4 seconds
Started	Apr 30 03:43:41 PM PDT 24
Finished	Apr 30 03:43:58 PM PDT 24
Peak memory	241840 kb
Host	smart-3bc0e7b6-b9c7-4f6c-9eae-a61df974bffd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3163745001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.3163745001
Directory	/workspace/30.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/30.otp_ctrl_dai_lock.1948193553
Short name	T612
Test name
Test status
Simulation time	1108321263 ps
CPU time	14.43 seconds
Started	Apr 30 03:43:40 PM PDT 24
Finished	Apr 30 03:43:55 PM PDT 24
Peak memory	241244 kb
Host	smart-ca7d95ae-d1b9-4535-85fb-25eb8fec8d44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948193553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.1948193553
Directory	/workspace/30.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/30.otp_ctrl_init_fail.3784387042
Short name	T976
Test name
Test status
Simulation time	198045523 ps
CPU time	3.84 seconds
Started	Apr 30 03:43:39 PM PDT 24
Finished	Apr 30 03:43:43 PM PDT 24
Peak memory	241656 kb
Host	smart-a6fda09f-1b9a-49dd-a62a-b81058e7fa3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3784387042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.3784387042
Directory	/workspace/30.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/30.otp_ctrl_macro_errs.326592631
Short name	T230
Test name
Test status
Simulation time	4114707025 ps
CPU time	52.56 seconds
Started	Apr 30 03:43:46 PM PDT 24
Finished	Apr 30 03:44:40 PM PDT 24
Peak memory	256340 kb
Host	smart-ae1e8dc6-c299-4032-aeb7-18d275fc1dc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326592631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.326592631
Directory	/workspace/30.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/30.otp_ctrl_parallel_key_req.2232836684
Short name	T442
Test name
Test status
Simulation time	264695794 ps
CPU time	6.81 seconds
Started	Apr 30 03:43:45 PM PDT 24
Finished	Apr 30 03:43:52 PM PDT 24
Peak memory	247996 kb
Host	smart-3c5e0075-28c8-4cd9-a456-12e739ece8fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2232836684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.2232836684
Directory	/workspace/30.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.2711146776
Short name	T285
Test name
Test status
Simulation time	112350902 ps
CPU time	2.93 seconds
Started	Apr 30 03:43:39 PM PDT 24
Finished	Apr 30 03:43:42 PM PDT 24
Peak memory	241252 kb
Host	smart-2fdb5fc9-9645-4438-8a18-173598af96ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2711146776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.2711146776
Directory	/workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/30.otp_ctrl_parallel_lc_req.1399439818
Short name	T107
Test name
Test status
Simulation time	1390049516 ps
CPU time	12.71 seconds
Started	Apr 30 03:43:41 PM PDT 24
Finished	Apr 30 03:43:55 PM PDT 24
Peak memory	241256 kb
Host	smart-cabc8d8b-94c0-4ad1-a945-5c97b83bb900
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1399439818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.1399439818
Directory	/workspace/30.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/30.otp_ctrl_smoke.3176166467
Short name	T641
Test name
Test status
Simulation time	8267040859 ps
CPU time	14.53 seconds
Started	Apr 30 03:43:44 PM PDT 24
Finished	Apr 30 03:44:00 PM PDT 24
Peak memory	247880 kb
Host	smart-300bd696-b5f6-480f-9a92-18515afa7a91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3176166467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.3176166467
Directory	/workspace/30.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.otp_ctrl_stress_all.570090932
Short name	T939
Test name
Test status
Simulation time	3022442883 ps
CPU time	86.86 seconds
Started	Apr 30 03:43:45 PM PDT 24
Finished	Apr 30 03:45:13 PM PDT 24
Peak memory	255208 kb
Host	smart-8173846e-bf4d-4015-9dba-53888cabb8ea
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570090932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all. 570090932
Directory	/workspace/30.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.2626368361
Short name	T883
Test name
Test status
Simulation time	59780640114 ps
CPU time	1503.31 seconds
Started	Apr 30 03:43:49 PM PDT 24
Finished	Apr 30 04:08:53 PM PDT 24
Peak memory	280996 kb
Host	smart-49528e25-e566-4e08-99df-48d89fa005d4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626368361 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.2626368361
Directory	/workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.otp_ctrl_test_access.3825980508
Short name	T1195
Test name
Test status
Simulation time	4342440069 ps
CPU time	35.55 seconds
Started	Apr 30 03:43:48 PM PDT 24
Finished	Apr 30 03:44:24 PM PDT 24
Peak memory	241428 kb
Host	smart-df1231b0-0eae-42e0-a53b-6c93bc5b6968
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3825980508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.3825980508
Directory	/workspace/30.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/31.otp_ctrl_alert_test.2183567362
Short name	T786
Test name
Test status
Simulation time	97614889 ps
CPU time	1.95 seconds
Started	Apr 30 03:43:55 PM PDT 24
Finished	Apr 30 03:43:57 PM PDT 24
Peak memory	240056 kb
Host	smart-3497ff97-bea8-4a5d-8ebe-20f20f72424d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183567362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.2183567362
Directory	/workspace/31.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.otp_ctrl_check_fail.620635255
Short name	T126
Test name
Test status
Simulation time	14615911080 ps
CPU time	25.96 seconds
Started	Apr 30 03:43:53 PM PDT 24
Finished	Apr 30 03:44:19 PM PDT 24
Peak memory	248228 kb
Host	smart-97affd3e-308d-48a7-97bb-ac946e94720d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620635255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.620635255
Directory	/workspace/31.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/31.otp_ctrl_dai_errs.105766203
Short name	T541
Test name
Test status
Simulation time	245251351 ps
CPU time	8.5 seconds
Started	Apr 30 03:43:51 PM PDT 24
Finished	Apr 30 03:44:00 PM PDT 24
Peak memory	241304 kb
Host	smart-4b5ba958-d090-496b-af8e-95f15a37e952
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105766203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.105766203
Directory	/workspace/31.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/31.otp_ctrl_dai_lock.4190826168
Short name	T106
Test name
Test status
Simulation time	3725088883 ps
CPU time	7.75 seconds
Started	Apr 30 03:43:52 PM PDT 24
Finished	Apr 30 03:44:00 PM PDT 24
Peak memory	241632 kb
Host	smart-57c61cf2-99a0-43f3-b880-a876723a762d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4190826168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.4190826168
Directory	/workspace/31.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/31.otp_ctrl_init_fail.1432616469
Short name	T145
Test name
Test status
Simulation time	1645905382 ps
CPU time	5.39 seconds
Started	Apr 30 03:43:46 PM PDT 24
Finished	Apr 30 03:43:52 PM PDT 24
Peak memory	241676 kb
Host	smart-1782fb83-6949-4f20-8451-8818a2e48635
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432616469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.1432616469
Directory	/workspace/31.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/31.otp_ctrl_macro_errs.706958218
Short name	T840
Test name
Test status
Simulation time	13202403186 ps
CPU time	26.78 seconds
Started	Apr 30 03:43:52 PM PDT 24
Finished	Apr 30 03:44:20 PM PDT 24
Peak memory	243828 kb
Host	smart-81d87eac-72a2-4a41-bad1-191882928e64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=706958218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.706958218
Directory	/workspace/31.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/31.otp_ctrl_parallel_key_req.1160505264
Short name	T603
Test name
Test status
Simulation time	604421040 ps
CPU time	14.41 seconds
Started	Apr 30 03:43:52 PM PDT 24
Finished	Apr 30 03:44:07 PM PDT 24
Peak memory	247896 kb
Host	smart-92e16638-82e4-41b8-911c-113dafca3a43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160505264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.1160505264
Directory	/workspace/31.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.1425509121
Short name	T188
Test name
Test status
Simulation time	1749472134 ps
CPU time	23.38 seconds
Started	Apr 30 03:43:50 PM PDT 24
Finished	Apr 30 03:44:14 PM PDT 24
Peak memory	241392 kb
Host	smart-c76f91c5-da94-412b-a203-eb94fbf6eb1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1425509121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1425509121
Directory	/workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/31.otp_ctrl_parallel_lc_req.86592918
Short name	T417
Test name
Test status
Simulation time	1228137506 ps
CPU time	24.41 seconds
Started	Apr 30 03:43:45 PM PDT 24
Finished	Apr 30 03:44:10 PM PDT 24
Peak memory	247884 kb
Host	smart-8544ddfc-bdcc-4d8b-a95d-ac1cca9c2b6a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=86592918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.86592918
Directory	/workspace/31.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/31.otp_ctrl_smoke.844029779
Short name	T1084
Test name
Test status
Simulation time	158343774 ps
CPU time	5.97 seconds
Started	Apr 30 03:43:48 PM PDT 24
Finished	Apr 30 03:43:55 PM PDT 24
Peak memory	241156 kb
Host	smart-46cdb7ec-bdb6-4c42-beb6-a08a3448b88e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844029779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.844029779
Directory	/workspace/31.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.otp_ctrl_stress_all.3370014800
Short name	T522
Test name
Test status
Simulation time	14048277582 ps
CPU time	85.08 seconds
Started	Apr 30 03:43:51 PM PDT 24
Finished	Apr 30 03:45:17 PM PDT 24
Peak memory	244740 kb
Host	smart-63a8e254-3b59-49c7-861d-cd54d1343f76
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370014800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all .3370014800
Directory	/workspace/31.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.1570752708
Short name	T795
Test name
Test status
Simulation time	957341053282 ps
CPU time	2256.77 seconds
Started	Apr 30 03:43:53 PM PDT 24
Finished	Apr 30 04:21:31 PM PDT 24
Peak memory	609008 kb
Host	smart-7fcfb696-73a1-42af-a162-0fafab46ffd7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570752708 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.1570752708
Directory	/workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.otp_ctrl_test_access.3409858604
Short name	T1016
Test name
Test status
Simulation time	650575078 ps
CPU time	13.28 seconds
Started	Apr 30 03:43:54 PM PDT 24
Finished	Apr 30 03:44:08 PM PDT 24
Peak memory	241676 kb
Host	smart-e13cff2f-8b4d-47eb-8b3f-f6d1d23a5dbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409858604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.3409858604
Directory	/workspace/31.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/32.otp_ctrl_alert_test.3821473493
Short name	T701
Test name
Test status
Simulation time	224150609 ps
CPU time	2.14 seconds
Started	Apr 30 03:44:00 PM PDT 24
Finished	Apr 30 03:44:03 PM PDT 24
Peak memory	239976 kb
Host	smart-3996bffe-b09c-43e0-8539-c1ddfe414435
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821473493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.3821473493
Directory	/workspace/32.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.otp_ctrl_check_fail.2867550070
Short name	T1092
Test name
Test status
Simulation time	1760448313 ps
CPU time	4.08 seconds
Started	Apr 30 03:43:59 PM PDT 24
Finished	Apr 30 03:44:03 PM PDT 24
Peak memory	241852 kb
Host	smart-45f6d971-001f-4b1b-9053-d9a5ac81e66a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867550070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.2867550070
Directory	/workspace/32.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/32.otp_ctrl_dai_errs.630584502
Short name	T8
Test name
Test status
Simulation time	1377066560 ps
CPU time	37.18 seconds
Started	Apr 30 03:44:02 PM PDT 24
Finished	Apr 30 03:44:40 PM PDT 24
Peak memory	252008 kb
Host	smart-aff5fc78-fac4-4179-803a-58d4e377648f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=630584502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.630584502
Directory	/workspace/32.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/32.otp_ctrl_dai_lock.2041480355
Short name	T898
Test name
Test status
Simulation time	1328467087 ps
CPU time	21.15 seconds
Started	Apr 30 03:43:58 PM PDT 24
Finished	Apr 30 03:44:20 PM PDT 24
Peak memory	241248 kb
Host	smart-edd31af6-b25b-44d9-9e57-b49484f4a191
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041480355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.2041480355
Directory	/workspace/32.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/32.otp_ctrl_init_fail.2702086006
Short name	T97
Test name
Test status
Simulation time	2523886120 ps
CPU time	5.32 seconds
Started	Apr 30 03:43:53 PM PDT 24
Finished	Apr 30 03:43:59 PM PDT 24
Peak memory	241516 kb
Host	smart-69f66151-7531-4b09-ab99-e8185715e948
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2702086006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.2702086006
Directory	/workspace/32.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/32.otp_ctrl_macro_errs.88483733
Short name	T864
Test name
Test status
Simulation time	1505575394 ps
CPU time	14.52 seconds
Started	Apr 30 03:44:00 PM PDT 24
Finished	Apr 30 03:44:16 PM PDT 24
Peak memory	243088 kb
Host	smart-ae8487a7-a7e6-4212-9f42-a97562b4cf0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=88483733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.88483733
Directory	/workspace/32.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/32.otp_ctrl_parallel_key_req.3163640381
Short name	T1196
Test name
Test status
Simulation time	629621380 ps
CPU time	22.8 seconds
Started	Apr 30 03:43:59 PM PDT 24
Finished	Apr 30 03:44:22 PM PDT 24
Peak memory	241216 kb
Host	smart-a1ad832a-7f62-494a-a348-b4a0793b99ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3163640381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.3163640381
Directory	/workspace/32.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.1666110280
Short name	T186
Test name
Test status
Simulation time	2158962098 ps
CPU time	13.69 seconds
Started	Apr 30 03:43:58 PM PDT 24
Finished	Apr 30 03:44:12 PM PDT 24
Peak memory	241504 kb
Host	smart-529fe82e-d20b-4896-9cf7-ebfff1e53bbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666110280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.1666110280
Directory	/workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/32.otp_ctrl_parallel_lc_req.2342563684
Short name	T562
Test name
Test status
Simulation time	1429290098 ps
CPU time	29.66 seconds
Started	Apr 30 03:44:02 PM PDT 24
Finished	Apr 30 03:44:33 PM PDT 24
Peak memory	241340 kb
Host	smart-b7236f7a-d2a4-41b4-81e7-8992b62d11ba
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2342563684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.2342563684
Directory	/workspace/32.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/32.otp_ctrl_regwen.2835675273
Short name	T828
Test name
Test status
Simulation time	475155526 ps
CPU time	10.42 seconds
Started	Apr 30 03:44:00 PM PDT 24
Finished	Apr 30 03:44:11 PM PDT 24
Peak memory	241264 kb
Host	smart-ea6f6a32-0997-42de-b6e0-813d404ffa5f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2835675273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.2835675273
Directory	/workspace/32.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/32.otp_ctrl_smoke.2714470245
Short name	T694
Test name
Test status
Simulation time	968296755 ps
CPU time	9.53 seconds
Started	Apr 30 03:43:50 PM PDT 24
Finished	Apr 30 03:44:01 PM PDT 24
Peak memory	241228 kb
Host	smart-6f3ec27e-0fbf-4b18-b4c6-e7f848172700
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2714470245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.2714470245
Directory	/workspace/32.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.otp_ctrl_stress_all.2565132563
Short name	T851
Test name
Test status
Simulation time	76247590314 ps
CPU time	215.44 seconds
Started	Apr 30 03:43:58 PM PDT 24
Finished	Apr 30 03:47:34 PM PDT 24
Peak memory	261588 kb
Host	smart-9f45f4df-251f-42b5-abce-9935c46e0b19
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565132563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all .2565132563
Directory	/workspace/32.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.2796788220
Short name	T782
Test name
Test status
Simulation time	69464600518 ps
CPU time	768.69 seconds
Started	Apr 30 03:43:59 PM PDT 24
Finished	Apr 30 03:56:48 PM PDT 24
Peak memory	330572 kb
Host	smart-1421f79b-a759-43e4-99fd-9dae3c513e10
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796788220 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.2796788220
Directory	/workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.otp_ctrl_test_access.2368372545
Short name	T1061
Test name
Test status
Simulation time	31025602098 ps
CPU time	27.35 seconds
Started	Apr 30 03:43:57 PM PDT 24
Finished	Apr 30 03:44:25 PM PDT 24
Peak memory	241712 kb
Host	smart-d8365dec-4298-4d4b-a307-d5375b834df0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2368372545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.2368372545
Directory	/workspace/32.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/33.otp_ctrl_alert_test.2647791027
Short name	T767
Test name
Test status
Simulation time	46408199 ps
CPU time	1.61 seconds
Started	Apr 30 03:44:08 PM PDT 24
Finished	Apr 30 03:44:10 PM PDT 24
Peak memory	239812 kb
Host	smart-e7b821f7-f6b0-4413-9636-2b59df0f192b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647791027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.2647791027
Directory	/workspace/33.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.otp_ctrl_check_fail.2850109424
Short name	T56
Test name
Test status
Simulation time	1571788352 ps
CPU time	25.88 seconds
Started	Apr 30 03:44:01 PM PDT 24
Finished	Apr 30 03:44:28 PM PDT 24
Peak memory	248056 kb
Host	smart-2f2ef567-2b99-4d38-8faf-237eeb6efcef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2850109424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2850109424
Directory	/workspace/33.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/33.otp_ctrl_dai_errs.228506284
Short name	T645
Test name
Test status
Simulation time	2781484419 ps
CPU time	24.05 seconds
Started	Apr 30 03:44:00 PM PDT 24
Finished	Apr 30 03:44:25 PM PDT 24
Peak memory	241724 kb
Host	smart-405c7e33-e7d9-41ee-bca0-a0611dc50ef8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=228506284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.228506284
Directory	/workspace/33.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/33.otp_ctrl_dai_lock.2645326066
Short name	T832
Test name
Test status
Simulation time	7039736988 ps
CPU time	11.38 seconds
Started	Apr 30 03:44:01 PM PDT 24
Finished	Apr 30 03:44:13 PM PDT 24
Peak memory	241480 kb
Host	smart-8a3adf8b-5e52-49f4-a5fb-6f4560c429fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2645326066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.2645326066
Directory	/workspace/33.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/33.otp_ctrl_init_fail.2053258785
Short name	T587
Test name
Test status
Simulation time	119117143 ps
CPU time	3.61 seconds
Started	Apr 30 03:44:00 PM PDT 24
Finished	Apr 30 03:44:04 PM PDT 24
Peak memory	241356 kb
Host	smart-9519d62d-a327-4a90-b61f-f832472f634f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053258785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.2053258785
Directory	/workspace/33.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/33.otp_ctrl_macro_errs.2216847052
Short name	T1035
Test name
Test status
Simulation time	1130358285 ps
CPU time	10.83 seconds
Started	Apr 30 03:44:05 PM PDT 24
Finished	Apr 30 03:44:16 PM PDT 24
Peak memory	241456 kb
Host	smart-af33e7b4-673a-49b1-a9b8-7d6432efaee5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2216847052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.2216847052
Directory	/workspace/33.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/33.otp_ctrl_parallel_key_req.2297263256
Short name	T450
Test name
Test status
Simulation time	2196717855 ps
CPU time	23.65 seconds
Started	Apr 30 03:44:09 PM PDT 24
Finished	Apr 30 03:44:33 PM PDT 24
Peak memory	241456 kb
Host	smart-23eb08b7-6286-4d1b-942b-d42cd59e42f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2297263256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2297263256
Directory	/workspace/33.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.886197832
Short name	T146
Test name
Test status
Simulation time	902308671 ps
CPU time	13.73 seconds
Started	Apr 30 03:44:01 PM PDT 24
Finished	Apr 30 03:44:16 PM PDT 24
Peak memory	241680 kb
Host	smart-b273dfd7-a308-44a9-abeb-ef35bd984a4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=886197832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.886197832
Directory	/workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/33.otp_ctrl_parallel_lc_req.292330626
Short name	T1138
Test name
Test status
Simulation time	3136119046 ps
CPU time	25.32 seconds
Started	Apr 30 03:43:58 PM PDT 24
Finished	Apr 30 03:44:23 PM PDT 24
Peak memory	241436 kb
Host	smart-ff70f843-458a-4c59-964a-8fc080b56fdc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=292330626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.292330626
Directory	/workspace/33.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/33.otp_ctrl_regwen.2158929071
Short name	T324
Test name
Test status
Simulation time	261508893 ps
CPU time	8.1 seconds
Started	Apr 30 03:44:07 PM PDT 24
Finished	Apr 30 03:44:15 PM PDT 24
Peak memory	241276 kb
Host	smart-b580835b-d484-4c67-9a27-de045b11ac8b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2158929071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.2158929071
Directory	/workspace/33.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/33.otp_ctrl_smoke.3712732152
Short name	T655
Test name
Test status
Simulation time	1135253736 ps
CPU time	12.37 seconds
Started	Apr 30 03:43:59 PM PDT 24
Finished	Apr 30 03:44:12 PM PDT 24
Peak memory	241596 kb
Host	smart-bb86f6c0-8d81-4960-93a9-d33660cb13b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3712732152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.3712732152
Directory	/workspace/33.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.otp_ctrl_test_access.2055129915
Short name	T669
Test name
Test status
Simulation time	160081612 ps
CPU time	4.32 seconds
Started	Apr 30 03:44:09 PM PDT 24
Finished	Apr 30 03:44:14 PM PDT 24
Peak memory	241332 kb
Host	smart-ee9395e4-6808-4e75-bd99-15a25f524cd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2055129915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.2055129915
Directory	/workspace/33.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/34.otp_ctrl_alert_test.2100967681
Short name	T430
Test name
Test status
Simulation time	954636405 ps
CPU time	2.41 seconds
Started	Apr 30 03:44:12 PM PDT 24
Finished	Apr 30 03:44:15 PM PDT 24
Peak memory	239804 kb
Host	smart-0dcceeab-a7e2-4b9f-8495-2f333be9c6a5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100967681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.2100967681
Directory	/workspace/34.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.otp_ctrl_check_fail.1216439652
Short name	T76
Test name
Test status
Simulation time	3228693071 ps
CPU time	20.28 seconds
Started	Apr 30 03:44:13 PM PDT 24
Finished	Apr 30 03:44:34 PM PDT 24
Peak memory	248148 kb
Host	smart-9066956f-3364-48b7-8f7d-ec4231c73f71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1216439652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1216439652
Directory	/workspace/34.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/34.otp_ctrl_dai_errs.2072997987
Short name	T3
Test name
Test status
Simulation time	2821782319 ps
CPU time	26.7 seconds
Started	Apr 30 03:44:14 PM PDT 24
Finished	Apr 30 03:44:41 PM PDT 24
Peak memory	241540 kb
Host	smart-6fa644b2-7f08-4668-9aca-891a7663cfd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2072997987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2072997987
Directory	/workspace/34.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/34.otp_ctrl_dai_lock.3331892398
Short name	T512
Test name
Test status
Simulation time	6493510867 ps
CPU time	26.07 seconds
Started	Apr 30 03:44:07 PM PDT 24
Finished	Apr 30 03:44:33 PM PDT 24
Peak memory	242720 kb
Host	smart-663fa97d-29f9-4059-bf38-3ca437cc86cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3331892398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.3331892398
Directory	/workspace/34.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/34.otp_ctrl_init_fail.1391362353
Short name	T783
Test name
Test status
Simulation time	704291806 ps
CPU time	3.96 seconds
Started	Apr 30 03:44:05 PM PDT 24
Finished	Apr 30 03:44:09 PM PDT 24
Peak memory	241492 kb
Host	smart-9f430106-7fd3-4a66-b09c-12040ab1533d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1391362353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.1391362353
Directory	/workspace/34.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/34.otp_ctrl_macro_errs.4263555544
Short name	T199
Test name
Test status
Simulation time	593105817 ps
CPU time	17.49 seconds
Started	Apr 30 03:44:17 PM PDT 24
Finished	Apr 30 03:44:35 PM PDT 24
Peak memory	241624 kb
Host	smart-3880cd34-45b5-40a2-8ade-59f075014ed2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4263555544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.4263555544
Directory	/workspace/34.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/34.otp_ctrl_parallel_key_req.989252733
Short name	T1191
Test name
Test status
Simulation time	3305551873 ps
CPU time	23.6 seconds
Started	Apr 30 03:44:16 PM PDT 24
Finished	Apr 30 03:44:40 PM PDT 24
Peak memory	241592 kb
Host	smart-c5f1eb33-3583-442c-9048-f05d3a71f972
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=989252733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.989252733
Directory	/workspace/34.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.3542768841
Short name	T1073
Test name
Test status
Simulation time	4618627826 ps
CPU time	10.61 seconds
Started	Apr 30 03:44:09 PM PDT 24
Finished	Apr 30 03:44:20 PM PDT 24
Peak memory	241328 kb
Host	smart-d1df62c2-ab92-45f1-9a29-e4f2aeac4053
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542768841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.3542768841
Directory	/workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/34.otp_ctrl_parallel_lc_req.705029359
Short name	T735
Test name
Test status
Simulation time	670757313 ps
CPU time	9.1 seconds
Started	Apr 30 03:44:07 PM PDT 24
Finished	Apr 30 03:44:17 PM PDT 24
Peak memory	241548 kb
Host	smart-7342db8a-79f7-4d52-adb6-afc3a7803213
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=705029359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.705029359
Directory	/workspace/34.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/34.otp_ctrl_regwen.931961872
Short name	T778
Test name
Test status
Simulation time	2539696882 ps
CPU time	8.41 seconds
Started	Apr 30 03:44:14 PM PDT 24
Finished	Apr 30 03:44:22 PM PDT 24
Peak memory	241544 kb
Host	smart-f4420ca9-5790-48e8-a72e-a4eae6086ac4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=931961872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.931961872
Directory	/workspace/34.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/34.otp_ctrl_smoke.1189194745
Short name	T725
Test name
Test status
Simulation time	607260939 ps
CPU time	3.41 seconds
Started	Apr 30 03:44:08 PM PDT 24
Finished	Apr 30 03:44:12 PM PDT 24
Peak memory	241280 kb
Host	smart-12956ca7-2387-4ec7-ba19-45d7b737a49e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1189194745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1189194745
Directory	/workspace/34.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.otp_ctrl_stress_all.1933348789
Short name	T288
Test name
Test status
Simulation time	8760820440 ps
CPU time	83.79 seconds
Started	Apr 30 03:44:15 PM PDT 24
Finished	Apr 30 03:45:40 PM PDT 24
Peak memory	245944 kb
Host	smart-acac99a6-14c7-401f-a630-eee5ddf64b4e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933348789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all .1933348789
Directory	/workspace/34.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.1304671551
Short name	T298
Test name
Test status
Simulation time	59594253713 ps
CPU time	1758.79 seconds
Started	Apr 30 03:44:15 PM PDT 24
Finished	Apr 30 04:13:35 PM PDT 24
Peak memory	531472 kb
Host	smart-19fa4367-9bd8-465a-98b6-58661b326fce
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304671551 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.1304671551
Directory	/workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.otp_ctrl_test_access.573687634
Short name	T1086
Test name
Test status
Simulation time	2447245029 ps
CPU time	14.05 seconds
Started	Apr 30 03:44:15 PM PDT 24
Finished	Apr 30 03:44:30 PM PDT 24
Peak memory	248080 kb
Host	smart-553edd65-c896-47bd-97bc-157504352840
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=573687634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.573687634
Directory	/workspace/34.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/35.otp_ctrl_alert_test.967845517
Short name	T546
Test name
Test status
Simulation time	601981345 ps
CPU time	1.69 seconds
Started	Apr 30 03:44:29 PM PDT 24
Finished	Apr 30 03:44:31 PM PDT 24
Peak memory	239904 kb
Host	smart-b372df8d-06ef-42c3-8912-2e00a0cb7370
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967845517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.967845517
Directory	/workspace/35.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.otp_ctrl_check_fail.983020817
Short name	T60
Test name
Test status
Simulation time	1176443444 ps
CPU time	7.61 seconds
Started	Apr 30 03:44:18 PM PDT 24
Finished	Apr 30 03:44:26 PM PDT 24
Peak memory	248004 kb
Host	smart-697c15d8-76ab-494f-9777-bb7998a450bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983020817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.983020817
Directory	/workspace/35.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/35.otp_ctrl_dai_errs.516985410
Short name	T1180
Test name
Test status
Simulation time	1259980156 ps
CPU time	18.97 seconds
Started	Apr 30 03:44:22 PM PDT 24
Finished	Apr 30 03:44:42 PM PDT 24
Peak memory	241256 kb
Host	smart-201f5907-5669-4033-8365-36debf709264
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=516985410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.516985410
Directory	/workspace/35.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/35.otp_ctrl_dai_lock.2885772076
Short name	T493
Test name
Test status
Simulation time	1481718538 ps
CPU time	18.38 seconds
Started	Apr 30 03:44:17 PM PDT 24
Finished	Apr 30 03:44:35 PM PDT 24
Peak memory	247824 kb
Host	smart-9c7a4aab-bb48-425b-ba56-0c09221bb358
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2885772076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.2885772076
Directory	/workspace/35.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/35.otp_ctrl_init_fail.3437924335
Short name	T1089
Test name
Test status
Simulation time	119005499 ps
CPU time	3.22 seconds
Started	Apr 30 03:44:15 PM PDT 24
Finished	Apr 30 03:44:18 PM PDT 24
Peak memory	241332 kb
Host	smart-3e8c3f84-8fc0-4ef0-8871-6add33ceb578
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3437924335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.3437924335
Directory	/workspace/35.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/35.otp_ctrl_macro_errs.2786982938
Short name	T204
Test name
Test status
Simulation time	2678927969 ps
CPU time	12.45 seconds
Started	Apr 30 03:44:18 PM PDT 24
Finished	Apr 30 03:44:31 PM PDT 24
Peak memory	241816 kb
Host	smart-855b40ab-df37-4299-bc1e-1484f7bfbf5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786982938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.2786982938
Directory	/workspace/35.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/35.otp_ctrl_parallel_key_req.1084837365
Short name	T875
Test name
Test status
Simulation time	1492350705 ps
CPU time	20.87 seconds
Started	Apr 30 03:44:19 PM PDT 24
Finished	Apr 30 03:44:40 PM PDT 24
Peak memory	241360 kb
Host	smart-3f191a44-0669-4863-9bcd-d9a6c5afd382
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1084837365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1084837365
Directory	/workspace/35.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/35.otp_ctrl_parallel_lc_req.2470214527
Short name	T1161
Test name
Test status
Simulation time	6734632972 ps
CPU time	17.6 seconds
Started	Apr 30 03:44:15 PM PDT 24
Finished	Apr 30 03:44:33 PM PDT 24
Peak memory	247968 kb
Host	smart-4e64369f-ca5c-4433-a2ae-2c8b9d8d1de7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2470214527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.2470214527
Directory	/workspace/35.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/35.otp_ctrl_regwen.2013583029
Short name	T769
Test name
Test status
Simulation time	4316022481 ps
CPU time	12.82 seconds
Started	Apr 30 03:44:17 PM PDT 24
Finished	Apr 30 03:44:30 PM PDT 24
Peak memory	241492 kb
Host	smart-79d0370c-ead0-46d0-916d-f74ab0f3c034
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2013583029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.2013583029
Directory	/workspace/35.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/35.otp_ctrl_smoke.3341915876
Short name	T825
Test name
Test status
Simulation time	1022478707 ps
CPU time	11.34 seconds
Started	Apr 30 03:44:15 PM PDT 24
Finished	Apr 30 03:44:27 PM PDT 24
Peak memory	241320 kb
Host	smart-a55dc827-bfcc-4ca4-8880-34afabc8e85e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3341915876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.3341915876
Directory	/workspace/35.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.otp_ctrl_test_access.1986419472
Short name	T570
Test name
Test status
Simulation time	701431634 ps
CPU time	22.18 seconds
Started	Apr 30 03:44:19 PM PDT 24
Finished	Apr 30 03:44:41 PM PDT 24
Peak memory	241676 kb
Host	smart-ee7aae76-3247-4ba8-aea7-cf3630495466
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986419472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.1986419472
Directory	/workspace/35.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/36.otp_ctrl_alert_test.2072422511
Short name	T1072
Test name
Test status
Simulation time	801640667 ps
CPU time	2.76 seconds
Started	Apr 30 03:44:24 PM PDT 24
Finished	Apr 30 03:44:27 PM PDT 24
Peak memory	240152 kb
Host	smart-661a1f6e-fd5f-4ed3-8687-113b744b1214
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072422511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.2072422511
Directory	/workspace/36.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.otp_ctrl_check_fail.3497290592
Short name	T1120
Test name
Test status
Simulation time	11144110685 ps
CPU time	31.19 seconds
Started	Apr 30 03:44:24 PM PDT 24
Finished	Apr 30 03:44:56 PM PDT 24
Peak memory	242312 kb
Host	smart-bc40a0e3-b78a-4a63-8f60-aeee8c1d3b0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3497290592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.3497290592
Directory	/workspace/36.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/36.otp_ctrl_dai_errs.4177894299
Short name	T1071
Test name
Test status
Simulation time	1806752043 ps
CPU time	23.04 seconds
Started	Apr 30 03:44:24 PM PDT 24
Finished	Apr 30 03:44:48 PM PDT 24
Peak memory	241436 kb
Host	smart-d25ea0c9-0999-4de9-bd75-a409bc9d8b12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4177894299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.4177894299
Directory	/workspace/36.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/36.otp_ctrl_dai_lock.2326492306
Short name	T520
Test name
Test status
Simulation time	515819580 ps
CPU time	20.92 seconds
Started	Apr 30 03:44:19 PM PDT 24
Finished	Apr 30 03:44:40 PM PDT 24
Peak memory	247948 kb
Host	smart-0a21ffd2-fd85-440f-9a58-7ed36a890047
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2326492306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.2326492306
Directory	/workspace/36.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/36.otp_ctrl_init_fail.1285885747
Short name	T547
Test name
Test status
Simulation time	249266503 ps
CPU time	4.05 seconds
Started	Apr 30 03:44:22 PM PDT 24
Finished	Apr 30 03:44:26 PM PDT 24
Peak memory	241392 kb
Host	smart-3bac23c5-8ec6-4260-a111-9de692638730
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1285885747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.1285885747
Directory	/workspace/36.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/36.otp_ctrl_macro_errs.3590127251
Short name	T679
Test name
Test status
Simulation time	7099554102 ps
CPU time	49.55 seconds
Started	Apr 30 03:44:23 PM PDT 24
Finished	Apr 30 03:45:13 PM PDT 24
Peak memory	246456 kb
Host	smart-fa459fb1-e95d-410b-addd-7b4d32ccfb75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3590127251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.3590127251
Directory	/workspace/36.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/36.otp_ctrl_parallel_key_req.1831611683
Short name	T325
Test name
Test status
Simulation time	227084040 ps
CPU time	6.35 seconds
Started	Apr 30 03:44:24 PM PDT 24
Finished	Apr 30 03:44:31 PM PDT 24
Peak memory	241720 kb
Host	smart-156e4f66-3f28-4b23-8d31-77cd1fcb1d13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831611683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1831611683
Directory	/workspace/36.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/36.otp_ctrl_parallel_lc_req.414033144
Short name	T408
Test name
Test status
Simulation time	1814461287 ps
CPU time	28.81 seconds
Started	Apr 30 03:44:20 PM PDT 24
Finished	Apr 30 03:44:49 PM PDT 24
Peak memory	247988 kb
Host	smart-77b68c05-b561-423b-86d8-a8950a835ad7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=414033144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.414033144
Directory	/workspace/36.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/36.otp_ctrl_regwen.1355301683
Short name	T1002
Test name
Test status
Simulation time	331165144 ps
CPU time	5.96 seconds
Started	Apr 30 03:44:27 PM PDT 24
Finished	Apr 30 03:44:33 PM PDT 24
Peak memory	241608 kb
Host	smart-b6b89c62-5e93-4c30-8313-9a229d0b8ac9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1355301683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.1355301683
Directory	/workspace/36.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/36.otp_ctrl_smoke.832307208
Short name	T349
Test name
Test status
Simulation time	840732618 ps
CPU time	6.62 seconds
Started	Apr 30 03:44:19 PM PDT 24
Finished	Apr 30 03:44:26 PM PDT 24
Peak memory	247712 kb
Host	smart-233a539d-4f5a-4690-88f0-1bc4e47278a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832307208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.832307208
Directory	/workspace/36.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.otp_ctrl_stress_all.629750644
Short name	T816
Test name
Test status
Simulation time	71027357704 ps
CPU time	198.84 seconds
Started	Apr 30 03:44:23 PM PDT 24
Finished	Apr 30 03:47:42 PM PDT 24
Peak memory	262852 kb
Host	smart-1c754cc2-a897-473a-bbca-39a7f28eb309
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629750644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all. 629750644
Directory	/workspace/36.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.2584892863
Short name	T329
Test name
Test status
Simulation time	67057462810 ps
CPU time	510.62 seconds
Started	Apr 30 03:44:23 PM PDT 24
Finished	Apr 30 03:52:54 PM PDT 24
Peak memory	264628 kb
Host	smart-9d27e17f-78de-4d9a-bea0-8d4a81f73192
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584892863 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.2584892863
Directory	/workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.otp_ctrl_test_access.3325341117
Short name	T480
Test name
Test status
Simulation time	301139521 ps
CPU time	8.51 seconds
Started	Apr 30 03:44:24 PM PDT 24
Finished	Apr 30 03:44:33 PM PDT 24
Peak memory	241256 kb
Host	smart-dd3a1a06-ef51-4b83-ac55-ff413752437d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325341117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.3325341117
Directory	/workspace/36.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/37.otp_ctrl_alert_test.2715709763
Short name	T518
Test name
Test status
Simulation time	77934082 ps
CPU time	1.87 seconds
Started	Apr 30 03:44:39 PM PDT 24
Finished	Apr 30 03:44:41 PM PDT 24
Peak memory	240140 kb
Host	smart-d943d0dc-5d4c-4e4f-9551-950bacc16913
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715709763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2715709763
Directory	/workspace/37.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.otp_ctrl_dai_errs.2242304745
Short name	T918
Test name
Test status
Simulation time	1140319784 ps
CPU time	17.59 seconds
Started	Apr 30 03:44:31 PM PDT 24
Finished	Apr 30 03:44:49 PM PDT 24
Peak memory	241740 kb
Host	smart-85e8b016-4854-49cb-a871-b4e25f9cc206
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2242304745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.2242304745
Directory	/workspace/37.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/37.otp_ctrl_dai_lock.2423370304
Short name	T1182
Test name
Test status
Simulation time	6056537833 ps
CPU time	20.69 seconds
Started	Apr 30 03:44:30 PM PDT 24
Finished	Apr 30 03:44:52 PM PDT 24
Peak memory	242324 kb
Host	smart-b707e055-1d84-4636-8a35-6e1e24d2d4bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423370304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.2423370304
Directory	/workspace/37.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/37.otp_ctrl_init_fail.3230198799
Short name	T761
Test name
Test status
Simulation time	124394163 ps
CPU time	4.64 seconds
Started	Apr 30 03:44:23 PM PDT 24
Finished	Apr 30 03:44:28 PM PDT 24
Peak memory	241424 kb
Host	smart-5cad82cd-7028-4ef8-b94f-995c8014ec0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3230198799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.3230198799
Directory	/workspace/37.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/37.otp_ctrl_macro_errs.1506452814
Short name	T174
Test name
Test status
Simulation time	8337634190 ps
CPU time	57.15 seconds
Started	Apr 30 03:44:31 PM PDT 24
Finished	Apr 30 03:45:29 PM PDT 24
Peak memory	256260 kb
Host	smart-439c8dbf-81b1-438a-9e7e-222c14e27ac3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1506452814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.1506452814
Directory	/workspace/37.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/37.otp_ctrl_parallel_key_req.926860866
Short name	T1094
Test name
Test status
Simulation time	17116399711 ps
CPU time	32.83 seconds
Started	Apr 30 03:44:29 PM PDT 24
Finished	Apr 30 03:45:02 PM PDT 24
Peak memory	248016 kb
Host	smart-da4cbcf6-ba5f-40e5-9b43-f05e246f30bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926860866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.926860866
Directory	/workspace/37.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.2497963399
Short name	T889
Test name
Test status
Simulation time	1778658552 ps
CPU time	22.53 seconds
Started	Apr 30 03:44:31 PM PDT 24
Finished	Apr 30 03:44:54 PM PDT 24
Peak memory	241276 kb
Host	smart-704611cc-debd-4971-a2f6-b74a58e140f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497963399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.2497963399
Directory	/workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/37.otp_ctrl_parallel_lc_req.2414620137
Short name	T552
Test name
Test status
Simulation time	646060159 ps
CPU time	22.89 seconds
Started	Apr 30 03:44:27 PM PDT 24
Finished	Apr 30 03:44:51 PM PDT 24
Peak memory	241216 kb
Host	smart-e5ed4b7a-b7df-43f6-8d13-1ece4eab15a8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2414620137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.2414620137
Directory	/workspace/37.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/37.otp_ctrl_regwen.3773197853
Short name	T841
Test name
Test status
Simulation time	2138899734 ps
CPU time	4.82 seconds
Started	Apr 30 03:44:35 PM PDT 24
Finished	Apr 30 03:44:41 PM PDT 24
Peak memory	241304 kb
Host	smart-52009d6f-5dee-4cb2-9662-e0e98b7d10cd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3773197853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.3773197853
Directory	/workspace/37.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/37.otp_ctrl_smoke.3768619090
Short name	T490
Test name
Test status
Simulation time	507827290 ps
CPU time	5.72 seconds
Started	Apr 30 03:44:23 PM PDT 24
Finished	Apr 30 03:44:30 PM PDT 24
Peak memory	241268 kb
Host	smart-48d15a4a-7ac9-4a1b-8fda-458be4da888b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3768619090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.3768619090
Directory	/workspace/37.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.otp_ctrl_stress_all.2449087002
Short name	T906
Test name
Test status
Simulation time	1637586022 ps
CPU time	47.99 seconds
Started	Apr 30 03:44:38 PM PDT 24
Finished	Apr 30 03:45:26 PM PDT 24
Peak memory	243116 kb
Host	smart-8c70dff5-c885-4490-aa58-decd5bb99174
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449087002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all .2449087002
Directory	/workspace/37.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.otp_ctrl_test_access.523082803
Short name	T531
Test name
Test status
Simulation time	4053453436 ps
CPU time	30.81 seconds
Started	Apr 30 03:44:36 PM PDT 24
Finished	Apr 30 03:45:07 PM PDT 24
Peak memory	248048 kb
Host	smart-17c9249e-503b-4051-aeec-fff5478f1d13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=523082803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.523082803
Directory	/workspace/37.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/38.otp_ctrl_alert_test.4182453091
Short name	T743
Test name
Test status
Simulation time	80371157 ps
CPU time	1.66 seconds
Started	Apr 30 03:44:41 PM PDT 24
Finished	Apr 30 03:44:44 PM PDT 24
Peak memory	240044 kb
Host	smart-393e1691-bf71-4c37-8483-ec2fe637ad4b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182453091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.4182453091
Directory	/workspace/38.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.otp_ctrl_check_fail.2129074971
Short name	T1033
Test name
Test status
Simulation time	820313565 ps
CPU time	8.05 seconds
Started	Apr 30 03:44:38 PM PDT 24
Finished	Apr 30 03:44:47 PM PDT 24
Peak memory	248040 kb
Host	smart-0cd8559c-cad0-46cb-a29d-cf18d24e1693
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2129074971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.2129074971
Directory	/workspace/38.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/38.otp_ctrl_dai_errs.3877334769
Short name	T1042
Test name
Test status
Simulation time	582748643 ps
CPU time	15.01 seconds
Started	Apr 30 03:44:36 PM PDT 24
Finished	Apr 30 03:44:52 PM PDT 24
Peak memory	241344 kb
Host	smart-e238d7f5-2bf9-431a-830e-13625e644073
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3877334769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.3877334769
Directory	/workspace/38.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/38.otp_ctrl_dai_lock.4051379767
Short name	T105
Test name
Test status
Simulation time	1524492402 ps
CPU time	16.09 seconds
Started	Apr 30 03:44:34 PM PDT 24
Finished	Apr 30 03:44:50 PM PDT 24
Peak memory	241664 kb
Host	smart-9f9b619c-79fd-4a8b-9d00-5c7bd2894a73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4051379767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.4051379767
Directory	/workspace/38.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/38.otp_ctrl_macro_errs.3861859914
Short name	T472
Test name
Test status
Simulation time	8968712704 ps
CPU time	21.18 seconds
Started	Apr 30 03:44:35 PM PDT 24
Finished	Apr 30 03:44:57 PM PDT 24
Peak memory	241748 kb
Host	smart-f9030178-db0f-47e6-9dac-c04a9df5a7d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861859914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.3861859914
Directory	/workspace/38.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/38.otp_ctrl_parallel_key_req.4122727291
Short name	T947
Test name
Test status
Simulation time	1095205340 ps
CPU time	22.38 seconds
Started	Apr 30 03:44:37 PM PDT 24
Finished	Apr 30 03:45:00 PM PDT 24
Peak memory	241652 kb
Host	smart-a9cda6e8-a09c-4259-962a-61bdbc45c59c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4122727291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.4122727291
Directory	/workspace/38.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.2811615228
Short name	T226
Test name
Test status
Simulation time	257747606 ps
CPU time	13.25 seconds
Started	Apr 30 03:44:35 PM PDT 24
Finished	Apr 30 03:44:49 PM PDT 24
Peak memory	241696 kb
Host	smart-2827a434-3f28-46a4-b164-f68c52385327
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2811615228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2811615228
Directory	/workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/38.otp_ctrl_parallel_lc_req.2772305764
Short name	T659
Test name
Test status
Simulation time	536804052 ps
CPU time	15.62 seconds
Started	Apr 30 03:44:36 PM PDT 24
Finished	Apr 30 03:44:52 PM PDT 24
Peak memory	241252 kb
Host	smart-e77e9c63-2f9c-4afd-b598-f755ea51eb79
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2772305764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.2772305764
Directory	/workspace/38.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/38.otp_ctrl_regwen.3412330477
Short name	T234
Test name
Test status
Simulation time	1970041556 ps
CPU time	5.12 seconds
Started	Apr 30 03:44:38 PM PDT 24
Finished	Apr 30 03:44:44 PM PDT 24
Peak memory	247880 kb
Host	smart-e6adbd8f-0e8a-4add-9dfb-7d39a2a0ba99
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3412330477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.3412330477
Directory	/workspace/38.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/38.otp_ctrl_smoke.2335570366
Short name	T790
Test name
Test status
Simulation time	292748933 ps
CPU time	9.86 seconds
Started	Apr 30 03:44:35 PM PDT 24
Finished	Apr 30 03:44:45 PM PDT 24
Peak memory	241688 kb
Host	smart-7f63e854-d9a0-4f38-b48f-1a2072553ca7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335570366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.2335570366
Directory	/workspace/38.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.otp_ctrl_stress_all.429491779
Short name	T407
Test name
Test status
Simulation time	109530793765 ps
CPU time	163.51 seconds
Started	Apr 30 03:44:36 PM PDT 24
Finished	Apr 30 03:47:20 PM PDT 24
Peak memory	260332 kb
Host	smart-7ec18e7d-410a-4186-8eec-ce8d10711a05
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429491779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all. 429491779
Directory	/workspace/38.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.2065485213
Short name	T355
Test name
Test status
Simulation time	70390880117 ps
CPU time	1580.41 seconds
Started	Apr 30 03:44:37 PM PDT 24
Finished	Apr 30 04:10:59 PM PDT 24
Peak memory	353116 kb
Host	smart-6e5b31ff-4e3d-4193-9553-e6fc2ec416ce
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065485213 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.2065485213
Directory	/workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.otp_ctrl_test_access.3945459265
Short name	T580
Test name
Test status
Simulation time	1510062875 ps
CPU time	30.93 seconds
Started	Apr 30 03:44:37 PM PDT 24
Finished	Apr 30 03:45:09 PM PDT 24
Peak memory	241476 kb
Host	smart-7d2e89ce-e906-486e-9917-d3306458a21f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945459265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3945459265
Directory	/workspace/38.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/39.otp_ctrl_alert_test.3382626895
Short name	T436
Test name
Test status
Simulation time	586394622 ps
CPU time	1.9 seconds
Started	Apr 30 03:44:47 PM PDT 24
Finished	Apr 30 03:44:50 PM PDT 24
Peak memory	240088 kb
Host	smart-5f0fcadb-cf61-440a-8de0-2783fe3bb18c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382626895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.3382626895
Directory	/workspace/39.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.otp_ctrl_check_fail.3081802666
Short name	T125
Test name
Test status
Simulation time	1055751898 ps
CPU time	22.66 seconds
Started	Apr 30 03:44:41 PM PDT 24
Finished	Apr 30 03:45:04 PM PDT 24
Peak memory	241916 kb
Host	smart-03372817-2bb9-4327-a825-159b3b87353f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081802666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.3081802666
Directory	/workspace/39.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/39.otp_ctrl_dai_errs.2871449719
Short name	T1034
Test name
Test status
Simulation time	167888541 ps
CPU time	8.4 seconds
Started	Apr 30 03:44:45 PM PDT 24
Finished	Apr 30 03:44:54 PM PDT 24
Peak memory	241156 kb
Host	smart-80963518-3f42-4f6c-b255-6c0b17f10506
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2871449719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.2871449719
Directory	/workspace/39.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/39.otp_ctrl_dai_lock.2309279965
Short name	T501
Test name
Test status
Simulation time	584879914 ps
CPU time	10.42 seconds
Started	Apr 30 03:44:41 PM PDT 24
Finished	Apr 30 03:44:53 PM PDT 24
Peak memory	241604 kb
Host	smart-79806077-1056-44f5-bb79-1761753983ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2309279965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.2309279965
Directory	/workspace/39.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/39.otp_ctrl_init_fail.2822420578
Short name	T1012
Test name
Test status
Simulation time	322138916 ps
CPU time	3.08 seconds
Started	Apr 30 03:44:39 PM PDT 24
Finished	Apr 30 03:44:43 PM PDT 24
Peak memory	241644 kb
Host	smart-29bed2d2-b20c-42d8-b6f6-879e213ef2cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822420578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.2822420578
Directory	/workspace/39.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/39.otp_ctrl_macro_errs.2380338521
Short name	T920
Test name
Test status
Simulation time	4844506526 ps
CPU time	30.62 seconds
Started	Apr 30 03:44:44 PM PDT 24
Finished	Apr 30 03:45:15 PM PDT 24
Peak memory	256364 kb
Host	smart-f4062484-cecf-4a13-87f7-0799c8bc98e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380338521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.2380338521
Directory	/workspace/39.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/39.otp_ctrl_parallel_key_req.3952927701
Short name	T414
Test name
Test status
Simulation time	1802696395 ps
CPU time	27.62 seconds
Started	Apr 30 03:44:43 PM PDT 24
Finished	Apr 30 03:45:11 PM PDT 24
Peak memory	241636 kb
Host	smart-26ece96c-557a-4639-b275-ecedd70ec8a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3952927701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.3952927701
Directory	/workspace/39.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.3779191778
Short name	T747
Test name
Test status
Simulation time	560524689 ps
CPU time	7.64 seconds
Started	Apr 30 03:44:40 PM PDT 24
Finished	Apr 30 03:44:49 PM PDT 24
Peak memory	241224 kb
Host	smart-e7807336-b2e0-4951-a237-d1f71e699858
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779191778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3779191778
Directory	/workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/39.otp_ctrl_parallel_lc_req.3110347968
Short name	T461
Test name
Test status
Simulation time	746548219 ps
CPU time	7.3 seconds
Started	Apr 30 03:44:43 PM PDT 24
Finished	Apr 30 03:44:51 PM PDT 24
Peak memory	241348 kb
Host	smart-7b1e1e85-1c2e-4bf0-b6e1-d6aaa87cc335
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3110347968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.3110347968
Directory	/workspace/39.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/39.otp_ctrl_regwen.1046175857
Short name	T1178
Test name
Test status
Simulation time	246382850 ps
CPU time	4.68 seconds
Started	Apr 30 03:44:40 PM PDT 24
Finished	Apr 30 03:44:46 PM PDT 24
Peak memory	241268 kb
Host	smart-b4ae94c4-290d-4bb2-8e97-dd0d96a6885f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1046175857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.1046175857
Directory	/workspace/39.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/39.otp_ctrl_smoke.917495819
Short name	T591
Test name
Test status
Simulation time	127390723 ps
CPU time	5.1 seconds
Started	Apr 30 03:44:46 PM PDT 24
Finished	Apr 30 03:44:51 PM PDT 24
Peak memory	241396 kb
Host	smart-93652251-f18b-4617-b05c-2ed6c66519f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=917495819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.917495819
Directory	/workspace/39.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.otp_ctrl_stress_all.535408603
Short name	T1049
Test name
Test status
Simulation time	4833599714 ps
CPU time	62.63 seconds
Started	Apr 30 03:44:48 PM PDT 24
Finished	Apr 30 03:45:51 PM PDT 24
Peak memory	241380 kb
Host	smart-9c511db5-e823-4b94-8e67-6aa5b4ba2698
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535408603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all. 535408603
Directory	/workspace/39.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.450872372
Short name	T15
Test name
Test status
Simulation time	18315569403 ps
CPU time	447.1 seconds
Started	Apr 30 03:44:47 PM PDT 24
Finished	Apr 30 03:52:15 PM PDT 24
Peak memory	256424 kb
Host	smart-0923e7a9-3742-4bf5-86ee-05b0ee995ba6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450872372 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.450872372
Directory	/workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.otp_ctrl_test_access.703052093
Short name	T868
Test name
Test status
Simulation time	548782609 ps
CPU time	4.61 seconds
Started	Apr 30 03:44:51 PM PDT 24
Finished	Apr 30 03:44:56 PM PDT 24
Peak memory	241620 kb
Host	smart-2c54408a-3761-4325-9ab0-9d93070fc23d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=703052093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.703052093
Directory	/workspace/39.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/4.otp_ctrl_alert_test.4128637555
Short name	T822
Test name
Test status
Simulation time	143029114 ps
CPU time	1.86 seconds
Started	Apr 30 03:40:26 PM PDT 24
Finished	Apr 30 03:40:28 PM PDT 24
Peak memory	239968 kb
Host	smart-af9dd292-c4f2-4350-9adb-ee173eaec5ff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128637555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.4128637555
Directory	/workspace/4.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.otp_ctrl_background_chks.2947450764
Short name	T971
Test name
Test status
Simulation time	3430879600 ps
CPU time	29.72 seconds
Started	Apr 30 03:40:23 PM PDT 24
Finished	Apr 30 03:40:53 PM PDT 24
Peak memory	241836 kb
Host	smart-5a5c7476-1ce1-4ca3-823e-d84db63c805a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947450764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.2947450764
Directory	/workspace/4.otp_ctrl_background_chks/latest

Test location	/workspace/coverage/default/4.otp_ctrl_check_fail.706034072
Short name	T962
Test name
Test status
Simulation time	22750339285 ps
CPU time	138.55 seconds
Started	Apr 30 03:40:22 PM PDT 24
Finished	Apr 30 03:42:41 PM PDT 24
Peak memory	241600 kb
Host	smart-5960a93e-3c0a-4292-b453-1590f1fe0866
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=706034072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.706034072
Directory	/workspace/4.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/4.otp_ctrl_dai_errs.1302261641
Short name	T923
Test name
Test status
Simulation time	1346467564 ps
CPU time	20.67 seconds
Started	Apr 30 03:40:23 PM PDT 24
Finished	Apr 30 03:40:44 PM PDT 24
Peak memory	241404 kb
Host	smart-ef766842-d677-46dc-801e-847870da6247
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1302261641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.1302261641
Directory	/workspace/4.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/4.otp_ctrl_dai_lock.727244290
Short name	T771
Test name
Test status
Simulation time	1086103551 ps
CPU time	12.6 seconds
Started	Apr 30 03:40:21 PM PDT 24
Finished	Apr 30 03:40:35 PM PDT 24
Peak memory	241628 kb
Host	smart-87d6c725-9fec-4840-8e1f-87de162efc37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=727244290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.727244290
Directory	/workspace/4.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/4.otp_ctrl_init_fail.3639178902
Short name	T63
Test name
Test status
Simulation time	2353454037 ps
CPU time	4.69 seconds
Started	Apr 30 03:40:22 PM PDT 24
Finished	Apr 30 03:40:27 PM PDT 24
Peak memory	241456 kb
Host	smart-40a2e18b-6356-49bb-99c9-451ce335dcfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3639178902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.3639178902
Directory	/workspace/4.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/4.otp_ctrl_macro_errs.3339973439
Short name	T543
Test name
Test status
Simulation time	4315764499 ps
CPU time	22.76 seconds
Started	Apr 30 03:40:20 PM PDT 24
Finished	Apr 30 03:40:44 PM PDT 24
Peak memory	245008 kb
Host	smart-37324e9c-5d4d-4d75-ab62-5087c989c13f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3339973439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.3339973439
Directory	/workspace/4.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/4.otp_ctrl_parallel_key_req.1946665695
Short name	T965
Test name
Test status
Simulation time	1402629028 ps
CPU time	27.65 seconds
Started	Apr 30 03:40:21 PM PDT 24
Finished	Apr 30 03:40:50 PM PDT 24
Peak memory	241512 kb
Host	smart-6c593b18-f9ae-4349-bc43-0fe37d2fc5ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1946665695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.1946665695
Directory	/workspace/4.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.531045153
Short name	T559
Test name
Test status
Simulation time	433728554 ps
CPU time	6.37 seconds
Started	Apr 30 03:40:19 PM PDT 24
Finished	Apr 30 03:40:26 PM PDT 24
Peak memory	246956 kb
Host	smart-dc6c1776-6d74-4896-bb07-ffd57192867b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=531045153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.531045153
Directory	/workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/4.otp_ctrl_parallel_lc_req.2715371463
Short name	T774
Test name
Test status
Simulation time	2806000526 ps
CPU time	21.74 seconds
Started	Apr 30 03:40:22 PM PDT 24
Finished	Apr 30 03:40:44 PM PDT 24
Peak memory	241504 kb
Host	smart-f96dd968-eb42-49ef-b42c-fea451a90fe8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2715371463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2715371463
Directory	/workspace/4.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/4.otp_ctrl_regwen.1006920842
Short name	T388
Test name
Test status
Simulation time	264410193 ps
CPU time	10.15 seconds
Started	Apr 30 03:40:21 PM PDT 24
Finished	Apr 30 03:40:32 PM PDT 24
Peak memory	241404 kb
Host	smart-bec9d778-158e-4fb1-a496-e29ed45d24c6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1006920842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1006920842
Directory	/workspace/4.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/4.otp_ctrl_smoke.1459828980
Short name	T609
Test name
Test status
Simulation time	211933709 ps
CPU time	4.73 seconds
Started	Apr 30 03:40:21 PM PDT 24
Finished	Apr 30 03:40:26 PM PDT 24
Peak memory	241504 kb
Host	smart-26568ac4-eba0-446d-a809-d7d0d1734c95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1459828980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1459828980
Directory	/workspace/4.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.otp_ctrl_stress_all.3309692791
Short name	T190
Test name
Test status
Simulation time	6096864802 ps
CPU time	51.82 seconds
Started	Apr 30 03:40:25 PM PDT 24
Finished	Apr 30 03:41:17 PM PDT 24
Peak memory	243616 kb
Host	smart-e0f857a0-8fed-4d8f-9bce-77e4b32258dd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309692791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all. 3309692791
Directory	/workspace/4.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.1959627260
Short name	T303
Test name
Test status
Simulation time	257905368219 ps
CPU time	1563.41 seconds
Started	Apr 30 03:40:26 PM PDT 24
Finished	Apr 30 04:06:30 PM PDT 24
Peak memory	353004 kb
Host	smart-6fa2fd31-bd79-4330-ac46-03f3b79fe99c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959627260 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.1959627260
Directory	/workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.otp_ctrl_test_access.3731369628
Short name	T604
Test name
Test status
Simulation time	6630444533 ps
CPU time	16.7 seconds
Started	Apr 30 03:40:23 PM PDT 24
Finished	Apr 30 03:40:40 PM PDT 24
Peak memory	248060 kb
Host	smart-2ebfb50e-6c4b-447e-aefc-0aa2f44b000a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3731369628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.3731369628
Directory	/workspace/4.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/40.otp_ctrl_alert_test.242579170
Short name	T326
Test name
Test status
Simulation time	107716042 ps
CPU time	1.71 seconds
Started	Apr 30 03:44:54 PM PDT 24
Finished	Apr 30 03:44:56 PM PDT 24
Peak memory	239784 kb
Host	smart-b134bdb3-5f9b-4668-9999-c49467571090
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242579170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.242579170
Directory	/workspace/40.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.otp_ctrl_check_fail.852592907
Short name	T529
Test name
Test status
Simulation time	658904049 ps
CPU time	9.45 seconds
Started	Apr 30 03:44:50 PM PDT 24
Finished	Apr 30 03:45:00 PM PDT 24
Peak memory	241768 kb
Host	smart-1de22705-b347-4725-9353-856d619f4aef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852592907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.852592907
Directory	/workspace/40.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/40.otp_ctrl_dai_errs.2416699051
Short name	T485
Test name
Test status
Simulation time	865497829 ps
CPU time	21.94 seconds
Started	Apr 30 03:44:47 PM PDT 24
Finished	Apr 30 03:45:10 PM PDT 24
Peak memory	241352 kb
Host	smart-212a9e66-940a-41e5-a876-03ce75c2cd32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416699051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.2416699051
Directory	/workspace/40.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/40.otp_ctrl_dai_lock.3973945864
Short name	T416
Test name
Test status
Simulation time	733452052 ps
CPU time	22.86 seconds
Started	Apr 30 03:44:49 PM PDT 24
Finished	Apr 30 03:45:13 PM PDT 24
Peak memory	241448 kb
Host	smart-729a2766-8dd6-4e01-bbd4-83e1eecdb4b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3973945864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.3973945864
Directory	/workspace/40.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/40.otp_ctrl_init_fail.1651641711
Short name	T178
Test name
Test status
Simulation time	1464112802 ps
CPU time	5.13 seconds
Started	Apr 30 03:44:45 PM PDT 24
Finished	Apr 30 03:44:51 PM PDT 24
Peak memory	241480 kb
Host	smart-605ff059-caa6-4474-a151-5cd17ce9cc23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1651641711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.1651641711
Directory	/workspace/40.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/40.otp_ctrl_macro_errs.3121619195
Short name	T95
Test name
Test status
Simulation time	468563427 ps
CPU time	4.69 seconds
Started	Apr 30 03:44:48 PM PDT 24
Finished	Apr 30 03:44:53 PM PDT 24
Peak memory	241456 kb
Host	smart-5a95ca2f-8437-4a5d-8032-46be8f5e3171
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3121619195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3121619195
Directory	/workspace/40.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/40.otp_ctrl_parallel_key_req.3983810067
Short name	T403
Test name
Test status
Simulation time	976118349 ps
CPU time	26.02 seconds
Started	Apr 30 03:44:48 PM PDT 24
Finished	Apr 30 03:45:15 PM PDT 24
Peak memory	248132 kb
Host	smart-cf7066b2-38c6-4ea8-abcc-5cd963230ebb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3983810067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.3983810067
Directory	/workspace/40.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.2775870311
Short name	T558
Test name
Test status
Simulation time	1494044288 ps
CPU time	5.14 seconds
Started	Apr 30 03:44:48 PM PDT 24
Finished	Apr 30 03:44:53 PM PDT 24
Peak memory	241252 kb
Host	smart-4ac07f4d-838c-44c1-8aef-ca4f760ca3ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2775870311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.2775870311
Directory	/workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/40.otp_ctrl_parallel_lc_req.3218879661
Short name	T802
Test name
Test status
Simulation time	1292762610 ps
CPU time	15.04 seconds
Started	Apr 30 03:44:47 PM PDT 24
Finished	Apr 30 03:45:02 PM PDT 24
Peak memory	247872 kb
Host	smart-0252d41f-ad70-4603-9492-06ba3e0fb9fa
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3218879661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.3218879661
Directory	/workspace/40.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/40.otp_ctrl_smoke.1246706129
Short name	T770
Test name
Test status
Simulation time	333024876 ps
CPU time	7.74 seconds
Started	Apr 30 03:44:48 PM PDT 24
Finished	Apr 30 03:44:57 PM PDT 24
Peak memory	241320 kb
Host	smart-5cea8db9-98f3-4469-9f0c-8525335f863f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246706129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.1246706129
Directory	/workspace/40.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.otp_ctrl_stress_all.614910723
Short name	T1145
Test name
Test status
Simulation time	2846870075 ps
CPU time	41.71 seconds
Started	Apr 30 03:44:54 PM PDT 24
Finished	Apr 30 03:45:36 PM PDT 24
Peak memory	242112 kb
Host	smart-5f80d442-09c5-40b3-938d-22d90fad940a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614910723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all. 614910723
Directory	/workspace/40.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.otp_ctrl_test_access.1488179565
Short name	T733
Test name
Test status
Simulation time	6742190504 ps
CPU time	28.74 seconds
Started	Apr 30 03:44:57 PM PDT 24
Finished	Apr 30 03:45:27 PM PDT 24
Peak memory	242284 kb
Host	smart-f08a1c86-d22e-4f00-82a0-719d66a72164
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1488179565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.1488179565
Directory	/workspace/40.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/41.otp_ctrl_alert_test.485292973
Short name	T421
Test name
Test status
Simulation time	83983041 ps
CPU time	1.54 seconds
Started	Apr 30 03:44:59 PM PDT 24
Finished	Apr 30 03:45:01 PM PDT 24
Peak memory	239808 kb
Host	smart-375213b1-3bec-4608-b186-27a82543d947
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485292973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.485292973
Directory	/workspace/41.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.otp_ctrl_check_fail.277858981
Short name	T87
Test name
Test status
Simulation time	513518739 ps
CPU time	15.99 seconds
Started	Apr 30 03:44:55 PM PDT 24
Finished	Apr 30 03:45:11 PM PDT 24
Peak memory	241384 kb
Host	smart-cf52a256-6c02-44e8-8892-81c03a4849c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=277858981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.277858981
Directory	/workspace/41.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/41.otp_ctrl_dai_errs.2389003726
Short name	T1008
Test name
Test status
Simulation time	968016511 ps
CPU time	32.48 seconds
Started	Apr 30 03:44:53 PM PDT 24
Finished	Apr 30 03:45:26 PM PDT 24
Peak memory	241756 kb
Host	smart-b23f06a8-0722-4a6f-b7eb-e5769ccee78b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389003726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.2389003726
Directory	/workspace/41.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/41.otp_ctrl_dai_lock.1245440642
Short name	T812
Test name
Test status
Simulation time	1060033903 ps
CPU time	11.76 seconds
Started	Apr 30 03:44:53 PM PDT 24
Finished	Apr 30 03:45:05 PM PDT 24
Peak memory	241368 kb
Host	smart-51efd6a9-aa69-4dfd-83fc-9fa634d0cf83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1245440642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.1245440642
Directory	/workspace/41.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/41.otp_ctrl_init_fail.2589041767
Short name	T1047
Test name
Test status
Simulation time	495137759 ps
CPU time	3.66 seconds
Started	Apr 30 03:44:55 PM PDT 24
Finished	Apr 30 03:44:59 PM PDT 24
Peak memory	241724 kb
Host	smart-56a3d293-ebd2-4359-8405-f6e21f81b03b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2589041767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.2589041767
Directory	/workspace/41.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/41.otp_ctrl_macro_errs.441725507
Short name	T1160
Test name
Test status
Simulation time	1004528607 ps
CPU time	21.1 seconds
Started	Apr 30 03:45:01 PM PDT 24
Finished	Apr 30 03:45:23 PM PDT 24
Peak memory	245832 kb
Host	smart-4c1e73e1-fe97-44d1-8b09-67fed6c65c96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=441725507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.441725507
Directory	/workspace/41.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/41.otp_ctrl_parallel_key_req.2034346588
Short name	T713
Test name
Test status
Simulation time	578105998 ps
CPU time	25.58 seconds
Started	Apr 30 03:45:02 PM PDT 24
Finished	Apr 30 03:45:28 PM PDT 24
Peak memory	241376 kb
Host	smart-4b86570a-f479-4a09-bdab-d74395da7798
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034346588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.2034346588
Directory	/workspace/41.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.2774841774
Short name	T1146
Test name
Test status
Simulation time	259809859 ps
CPU time	8.87 seconds
Started	Apr 30 03:44:57 PM PDT 24
Finished	Apr 30 03:45:07 PM PDT 24
Peak memory	241340 kb
Host	smart-a8bc4db3-a75a-4c35-9d33-60104a79012a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2774841774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.2774841774
Directory	/workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/41.otp_ctrl_parallel_lc_req.3416401863
Short name	T462
Test name
Test status
Simulation time	813859996 ps
CPU time	23.37 seconds
Started	Apr 30 03:44:54 PM PDT 24
Finished	Apr 30 03:45:18 PM PDT 24
Peak memory	241316 kb
Host	smart-de5b8fd7-f2ef-4284-a2bd-42a627b9ce9f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3416401863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.3416401863
Directory	/workspace/41.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/41.otp_ctrl_regwen.1736996840
Short name	T884
Test name
Test status
Simulation time	1023300186 ps
CPU time	10.32 seconds
Started	Apr 30 03:45:01 PM PDT 24
Finished	Apr 30 03:45:12 PM PDT 24
Peak memory	241360 kb
Host	smart-ede2db84-1ca2-4d25-adeb-898d5c41c0c5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1736996840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.1736996840
Directory	/workspace/41.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/41.otp_ctrl_smoke.2869005131
Short name	T993
Test name
Test status
Simulation time	3839432381 ps
CPU time	10.94 seconds
Started	Apr 30 03:44:54 PM PDT 24
Finished	Apr 30 03:45:05 PM PDT 24
Peak memory	248108 kb
Host	smart-cf79f7e7-4278-4097-8c11-d1ad655c64ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2869005131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.2869005131
Directory	/workspace/41.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.otp_ctrl_stress_all.639550473
Short name	T772
Test name
Test status
Simulation time	64744525088 ps
CPU time	164.52 seconds
Started	Apr 30 03:45:01 PM PDT 24
Finished	Apr 30 03:47:46 PM PDT 24
Peak memory	255020 kb
Host	smart-54606ebc-e733-4318-9db8-93706cf0a15f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639550473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all. 639550473
Directory	/workspace/41.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.519979007
Short name	T252
Test name
Test status
Simulation time	86682982695 ps
CPU time	1152.64 seconds
Started	Apr 30 03:44:58 PM PDT 24
Finished	Apr 30 04:04:11 PM PDT 24
Peak memory	378156 kb
Host	smart-a01ee00e-58a2-42da-8295-3001e42a0336
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519979007 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.519979007
Directory	/workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.otp_ctrl_test_access.3561328758
Short name	T293
Test name
Test status
Simulation time	1775904597 ps
CPU time	25.77 seconds
Started	Apr 30 03:45:02 PM PDT 24
Finished	Apr 30 03:45:28 PM PDT 24
Peak memory	241328 kb
Host	smart-b88efd3b-f5da-41b0-9e2b-fc6e7528b1d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3561328758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.3561328758
Directory	/workspace/41.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/42.otp_ctrl_alert_test.2022708092
Short name	T663
Test name
Test status
Simulation time	106554347 ps
CPU time	2.09 seconds
Started	Apr 30 03:45:05 PM PDT 24
Finished	Apr 30 03:45:07 PM PDT 24
Peak memory	239776 kb
Host	smart-dad7289e-9b67-49ee-bde3-e91fb958f59e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022708092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.2022708092
Directory	/workspace/42.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.otp_ctrl_dai_errs.2989085433
Short name	T446
Test name
Test status
Simulation time	924684483 ps
CPU time	16.06 seconds
Started	Apr 30 03:45:08 PM PDT 24
Finished	Apr 30 03:45:24 PM PDT 24
Peak memory	241220 kb
Host	smart-e6c087fa-8fb0-4f2a-932f-16d0656e2ce9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2989085433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.2989085433
Directory	/workspace/42.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/42.otp_ctrl_dai_lock.1130672238
Short name	T651
Test name
Test status
Simulation time	1210782849 ps
CPU time	21.84 seconds
Started	Apr 30 03:45:03 PM PDT 24
Finished	Apr 30 03:45:26 PM PDT 24
Peak memory	241280 kb
Host	smart-5f1561f5-81f0-44be-a322-bdee64225c5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130672238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.1130672238
Directory	/workspace/42.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/42.otp_ctrl_init_fail.3745596686
Short name	T514
Test name
Test status
Simulation time	1969665618 ps
CPU time	5.14 seconds
Started	Apr 30 03:44:58 PM PDT 24
Finished	Apr 30 03:45:04 PM PDT 24
Peak memory	241680 kb
Host	smart-a9d84629-cbc2-4bc4-a783-bcafb8c39994
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745596686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.3745596686
Directory	/workspace/42.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/42.otp_ctrl_macro_errs.2730247700
Short name	T1186
Test name
Test status
Simulation time	6034886183 ps
CPU time	13.39 seconds
Started	Apr 30 03:45:07 PM PDT 24
Finished	Apr 30 03:45:21 PM PDT 24
Peak memory	248144 kb
Host	smart-ebf7572a-3469-42a5-869e-5893895dc706
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2730247700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.2730247700
Directory	/workspace/42.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/42.otp_ctrl_parallel_key_req.1491541700
Short name	T977
Test name
Test status
Simulation time	147057430 ps
CPU time	6.58 seconds
Started	Apr 30 03:45:03 PM PDT 24
Finished	Apr 30 03:45:10 PM PDT 24
Peak memory	241668 kb
Host	smart-33220b3a-306d-4f8e-95af-69cc853755d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1491541700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.1491541700
Directory	/workspace/42.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.3311877511
Short name	T500
Test name
Test status
Simulation time	586857651 ps
CPU time	16.03 seconds
Started	Apr 30 03:44:59 PM PDT 24
Finished	Apr 30 03:45:16 PM PDT 24
Peak memory	241536 kb
Host	smart-86ccc9cb-c306-4c15-9155-ae8411d40e86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3311877511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.3311877511
Directory	/workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/42.otp_ctrl_parallel_lc_req.2618887560
Short name	T723
Test name
Test status
Simulation time	1048449293 ps
CPU time	17.14 seconds
Started	Apr 30 03:45:00 PM PDT 24
Finished	Apr 30 03:45:18 PM PDT 24
Peak memory	241284 kb
Host	smart-85eaf41b-dfce-4b39-9589-8981d5c14e66
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2618887560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.2618887560
Directory	/workspace/42.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/42.otp_ctrl_regwen.305065931
Short name	T975
Test name
Test status
Simulation time	153133929 ps
CPU time	5.52 seconds
Started	Apr 30 03:45:08 PM PDT 24
Finished	Apr 30 03:45:14 PM PDT 24
Peak memory	241292 kb
Host	smart-771e5ed7-ebb9-443e-8e61-14c1601e6aed
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=305065931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.305065931
Directory	/workspace/42.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/42.otp_ctrl_smoke.2442949224
Short name	T1007
Test name
Test status
Simulation time	799252880 ps
CPU time	5.19 seconds
Started	Apr 30 03:44:59 PM PDT 24
Finished	Apr 30 03:45:05 PM PDT 24
Peak memory	241328 kb
Host	smart-2fe81517-0b96-49e6-9e34-f66b35c96cd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442949224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.2442949224
Directory	/workspace/42.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.otp_ctrl_stress_all.2558197203
Short name	T73
Test name
Test status
Simulation time	22972287273 ps
CPU time	114.33 seconds
Started	Apr 30 03:45:07 PM PDT 24
Finished	Apr 30 03:47:01 PM PDT 24
Peak memory	248208 kb
Host	smart-5c2adeff-b934-4794-abaa-2386331503cf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558197203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all .2558197203
Directory	/workspace/42.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.492375153
Short name	T246
Test name
Test status
Simulation time	141398971620 ps
CPU time	624.97 seconds
Started	Apr 30 03:45:05 PM PDT 24
Finished	Apr 30 03:55:30 PM PDT 24
Peak memory	332840 kb
Host	smart-b6aaf0f4-520f-49f5-af34-354a43a0e96c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492375153 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.492375153
Directory	/workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.otp_ctrl_test_access.1228744977
Short name	T826
Test name
Test status
Simulation time	7829664917 ps
CPU time	23.03 seconds
Started	Apr 30 03:45:05 PM PDT 24
Finished	Apr 30 03:45:29 PM PDT 24
Peak memory	242708 kb
Host	smart-124b2f39-20f5-4384-bb45-700279c3a3ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1228744977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.1228744977
Directory	/workspace/42.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/43.otp_ctrl_alert_test.3042827880
Short name	T233
Test name
Test status
Simulation time	80030734 ps
CPU time	1.67 seconds
Started	Apr 30 03:45:10 PM PDT 24
Finished	Apr 30 03:45:13 PM PDT 24
Peak memory	240056 kb
Host	smart-464c741c-5551-4776-a764-ca21162ca1c6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042827880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.3042827880
Directory	/workspace/43.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.otp_ctrl_check_fail.2354145081
Short name	T38
Test name
Test status
Simulation time	7037060171 ps
CPU time	20.41 seconds
Started	Apr 30 03:45:11 PM PDT 24
Finished	Apr 30 03:45:32 PM PDT 24
Peak memory	248092 kb
Host	smart-8df13352-114a-46e3-967e-1d08f4754aee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354145081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.2354145081
Directory	/workspace/43.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/43.otp_ctrl_dai_errs.1196934267
Short name	T1139
Test name
Test status
Simulation time	1828131478 ps
CPU time	29.24 seconds
Started	Apr 30 03:45:09 PM PDT 24
Finished	Apr 30 03:45:39 PM PDT 24
Peak memory	243116 kb
Host	smart-73b46577-7a33-452e-9194-73916863287e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1196934267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.1196934267
Directory	/workspace/43.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/43.otp_ctrl_dai_lock.4112256691
Short name	T922
Test name
Test status
Simulation time	6578117453 ps
CPU time	11.01 seconds
Started	Apr 30 03:45:10 PM PDT 24
Finished	Apr 30 03:45:22 PM PDT 24
Peak memory	241620 kb
Host	smart-83a142a2-68ee-499c-8542-46bb3eb1315b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4112256691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.4112256691
Directory	/workspace/43.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/43.otp_ctrl_init_fail.27194385
Short name	T719
Test name
Test status
Simulation time	544355958 ps
CPU time	3.93 seconds
Started	Apr 30 03:45:06 PM PDT 24
Finished	Apr 30 03:45:11 PM PDT 24
Peak memory	241724 kb
Host	smart-f79f23bf-b0cd-4fe4-8efb-5bac5cef18d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27194385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.27194385
Directory	/workspace/43.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/43.otp_ctrl_macro_errs.1279489740
Short name	T1000
Test name
Test status
Simulation time	2538383777 ps
CPU time	4.74 seconds
Started	Apr 30 03:45:12 PM PDT 24
Finished	Apr 30 03:45:18 PM PDT 24
Peak memory	241424 kb
Host	smart-519cd1d6-b349-4c35-91e3-b4e92f5b54f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1279489740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.1279489740
Directory	/workspace/43.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/43.otp_ctrl_parallel_key_req.1599403248
Short name	T181
Test name
Test status
Simulation time	1171100578 ps
CPU time	18.57 seconds
Started	Apr 30 03:45:11 PM PDT 24
Finished	Apr 30 03:45:31 PM PDT 24
Peak memory	241384 kb
Host	smart-12ad8417-04c9-45a7-9d08-319dbcb2ed6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1599403248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.1599403248
Directory	/workspace/43.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.1635843817
Short name	T185
Test name
Test status
Simulation time	142464006 ps
CPU time	6.3 seconds
Started	Apr 30 03:45:10 PM PDT 24
Finished	Apr 30 03:45:17 PM PDT 24
Peak memory	241328 kb
Host	smart-ea9f6445-a407-458e-b79e-2da43d56b61d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1635843817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.1635843817
Directory	/workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/43.otp_ctrl_parallel_lc_req.3937702566
Short name	T35
Test name
Test status
Simulation time	3139981691 ps
CPU time	25.73 seconds
Started	Apr 30 03:45:08 PM PDT 24
Finished	Apr 30 03:45:34 PM PDT 24
Peak memory	241368 kb
Host	smart-2164753a-4a93-4107-90a5-26885b8f63c0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3937702566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.3937702566
Directory	/workspace/43.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/43.otp_ctrl_regwen.448729268
Short name	T390
Test name
Test status
Simulation time	386690396 ps
CPU time	6.02 seconds
Started	Apr 30 03:45:10 PM PDT 24
Finished	Apr 30 03:45:17 PM PDT 24
Peak memory	247688 kb
Host	smart-c7dba704-1625-41fe-bc8b-62b0831d2b3c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=448729268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.448729268
Directory	/workspace/43.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/43.otp_ctrl_smoke.1530781953
Short name	T492
Test name
Test status
Simulation time	287078162 ps
CPU time	11.76 seconds
Started	Apr 30 03:45:05 PM PDT 24
Finished	Apr 30 03:45:17 PM PDT 24
Peak memory	241388 kb
Host	smart-48885be4-f2ff-4107-88c9-8c20cbcd12f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530781953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.1530781953
Directory	/workspace/43.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.otp_ctrl_stress_all.4041614127
Short name	T684
Test name
Test status
Simulation time	19292215746 ps
CPU time	111.93 seconds
Started	Apr 30 03:45:09 PM PDT 24
Finished	Apr 30 03:47:02 PM PDT 24
Peak memory	256340 kb
Host	smart-bab328d3-58cc-47bc-b918-c58c17f7a3d2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041614127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all .4041614127
Directory	/workspace/43.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.3324304686
Short name	T304
Test name
Test status
Simulation time	584683626974 ps
CPU time	2018.98 seconds
Started	Apr 30 03:45:10 PM PDT 24
Finished	Apr 30 04:18:50 PM PDT 24
Peak memory	334848 kb
Host	smart-2603455e-1d5e-4bf1-adda-c838acc55fe3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324304686 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.3324304686
Directory	/workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.otp_ctrl_test_access.1981097855
Short name	T1119
Test name
Test status
Simulation time	8797231780 ps
CPU time	15.83 seconds
Started	Apr 30 03:45:11 PM PDT 24
Finished	Apr 30 03:45:28 PM PDT 24
Peak memory	241768 kb
Host	smart-673a7159-9fc8-4b40-bd5e-761cc718c1e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1981097855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.1981097855
Directory	/workspace/43.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/44.otp_ctrl_alert_test.3154304864
Short name	T643
Test name
Test status
Simulation time	104542929 ps
CPU time	2.05 seconds
Started	Apr 30 03:45:18 PM PDT 24
Finished	Apr 30 03:45:21 PM PDT 24
Peak memory	239924 kb
Host	smart-ed385062-bb73-483a-8c1a-0df5f6793bfa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154304864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.3154304864
Directory	/workspace/44.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.otp_ctrl_check_fail.2291026201
Short name	T819
Test name
Test status
Simulation time	9625444957 ps
CPU time	25.38 seconds
Started	Apr 30 03:45:16 PM PDT 24
Finished	Apr 30 03:45:42 PM PDT 24
Peak memory	248144 kb
Host	smart-d936f293-99e9-47bd-9fcc-d9dd67bf0699
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2291026201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.2291026201
Directory	/workspace/44.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/44.otp_ctrl_dai_errs.1569054609
Short name	T194
Test name
Test status
Simulation time	1087860458 ps
CPU time	15.33 seconds
Started	Apr 30 03:45:17 PM PDT 24
Finished	Apr 30 03:45:33 PM PDT 24
Peak memory	241452 kb
Host	smart-d692555a-f233-4e5b-83ff-6390990e6d32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1569054609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.1569054609
Directory	/workspace/44.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/44.otp_ctrl_dai_lock.1156225535
Short name	T606
Test name
Test status
Simulation time	1572479016 ps
CPU time	33.93 seconds
Started	Apr 30 03:45:18 PM PDT 24
Finished	Apr 30 03:45:52 PM PDT 24
Peak memory	241384 kb
Host	smart-b1746293-4769-45a7-9d59-1e21825681a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1156225535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.1156225535
Directory	/workspace/44.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/44.otp_ctrl_macro_errs.2971729448
Short name	T369
Test name
Test status
Simulation time	497676272 ps
CPU time	7.6 seconds
Started	Apr 30 03:45:19 PM PDT 24
Finished	Apr 30 03:45:27 PM PDT 24
Peak memory	241288 kb
Host	smart-47182160-5038-48ac-930f-239ad0dd85c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2971729448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2971729448
Directory	/workspace/44.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/44.otp_ctrl_parallel_key_req.1613834703
Short name	T894
Test name
Test status
Simulation time	448724126 ps
CPU time	16.97 seconds
Started	Apr 30 03:45:19 PM PDT 24
Finished	Apr 30 03:45:37 PM PDT 24
Peak memory	241300 kb
Host	smart-b4550807-67bf-441a-959d-5fc4c798408b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1613834703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.1613834703
Directory	/workspace/44.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.120649833
Short name	T624
Test name
Test status
Simulation time	94320151 ps
CPU time	3.61 seconds
Started	Apr 30 03:45:18 PM PDT 24
Finished	Apr 30 03:45:22 PM PDT 24
Peak memory	241688 kb
Host	smart-e1a1589f-355a-4b9c-9f74-430ce2ee88a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=120649833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.120649833
Directory	/workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/44.otp_ctrl_parallel_lc_req.989310846
Short name	T1081
Test name
Test status
Simulation time	9328860511 ps
CPU time	21.69 seconds
Started	Apr 30 03:45:09 PM PDT 24
Finished	Apr 30 03:45:31 PM PDT 24
Peak memory	248104 kb
Host	smart-f6525b48-df18-4838-9c70-a48b6a24cf47
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=989310846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.989310846
Directory	/workspace/44.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/44.otp_ctrl_regwen.888471691
Short name	T385
Test name
Test status
Simulation time	338473407 ps
CPU time	5.59 seconds
Started	Apr 30 03:45:18 PM PDT 24
Finished	Apr 30 03:45:24 PM PDT 24
Peak memory	241300 kb
Host	smart-58579ee5-c984-4b7d-a011-50d8b973566b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=888471691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.888471691
Directory	/workspace/44.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/44.otp_ctrl_smoke.2469216344
Short name	T565
Test name
Test status
Simulation time	393279929 ps
CPU time	6.22 seconds
Started	Apr 30 03:45:09 PM PDT 24
Finished	Apr 30 03:45:16 PM PDT 24
Peak memory	241180 kb
Host	smart-072b6784-6628-468e-90c9-a11c5c4db0dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469216344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.2469216344
Directory	/workspace/44.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.otp_ctrl_test_access.3153478835
Short name	T1062
Test name
Test status
Simulation time	5751204684 ps
CPU time	37.21 seconds
Started	Apr 30 03:45:18 PM PDT 24
Finished	Apr 30 03:45:56 PM PDT 24
Peak memory	241752 kb
Host	smart-acf6af0d-f25f-45b5-b3fa-e6dd367f008e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153478835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.3153478835
Directory	/workspace/44.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/45.otp_ctrl_alert_test.2543084322
Short name	T454
Test name
Test status
Simulation time	42123782 ps
CPU time	1.57 seconds
Started	Apr 30 03:45:26 PM PDT 24
Finished	Apr 30 03:45:28 PM PDT 24
Peak memory	239812 kb
Host	smart-fdbfe6f4-fbfd-45f1-a284-5074cf55f37f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543084322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.2543084322
Directory	/workspace/45.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.otp_ctrl_check_fail.2715172587
Short name	T911
Test name
Test status
Simulation time	140941327 ps
CPU time	4.29 seconds
Started	Apr 30 03:45:20 PM PDT 24
Finished	Apr 30 03:45:25 PM PDT 24
Peak memory	241284 kb
Host	smart-d600cb38-6419-4c82-81da-24962c1279ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2715172587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.2715172587
Directory	/workspace/45.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/45.otp_ctrl_dai_errs.1394752539
Short name	T944
Test name
Test status
Simulation time	620983818 ps
CPU time	16.36 seconds
Started	Apr 30 03:45:24 PM PDT 24
Finished	Apr 30 03:45:41 PM PDT 24
Peak memory	241436 kb
Host	smart-bfdf7972-190b-4ef5-801e-bad7b7633cef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394752539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.1394752539
Directory	/workspace/45.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/45.otp_ctrl_dai_lock.1051099125
Short name	T1121
Test name
Test status
Simulation time	1271813112 ps
CPU time	31.5 seconds
Started	Apr 30 03:45:22 PM PDT 24
Finished	Apr 30 03:45:54 PM PDT 24
Peak memory	241316 kb
Host	smart-a664a45a-8f9c-4485-9359-29ff498135d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1051099125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.1051099125
Directory	/workspace/45.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/45.otp_ctrl_init_fail.3681521791
Short name	T486
Test name
Test status
Simulation time	153427043 ps
CPU time	3.87 seconds
Started	Apr 30 03:45:18 PM PDT 24
Finished	Apr 30 03:45:22 PM PDT 24
Peak memory	241432 kb
Host	smart-c7748389-5ea8-45e9-8c59-16fe69d607e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681521791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.3681521791
Directory	/workspace/45.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/45.otp_ctrl_macro_errs.3455755592
Short name	T865
Test name
Test status
Simulation time	4318272980 ps
CPU time	28.96 seconds
Started	Apr 30 03:45:20 PM PDT 24
Finished	Apr 30 03:45:50 PM PDT 24
Peak memory	247824 kb
Host	smart-39ea1332-4969-42c2-9eed-3b99ae41e9f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3455755592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.3455755592
Directory	/workspace/45.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/45.otp_ctrl_parallel_key_req.4270589586
Short name	T798
Test name
Test status
Simulation time	1310458991 ps
CPU time	19.34 seconds
Started	Apr 30 03:45:20 PM PDT 24
Finished	Apr 30 03:45:39 PM PDT 24
Peak memory	241852 kb
Host	smart-31a55928-70c6-4446-bda4-9f346866b13f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4270589586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.4270589586
Directory	/workspace/45.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.3528954249
Short name	T566
Test name
Test status
Simulation time	12714246968 ps
CPU time	25.83 seconds
Started	Apr 30 03:45:23 PM PDT 24
Finished	Apr 30 03:45:49 PM PDT 24
Peak memory	241440 kb
Host	smart-ef64ab9d-d67b-4797-90e8-42c4fcc8a6cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3528954249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.3528954249
Directory	/workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/45.otp_ctrl_parallel_lc_req.660895242
Short name	T515
Test name
Test status
Simulation time	466505615 ps
CPU time	6.27 seconds
Started	Apr 30 03:45:22 PM PDT 24
Finished	Apr 30 03:45:29 PM PDT 24
Peak memory	241340 kb
Host	smart-5bf3e869-2844-4617-8a94-4e6f9db7ac9a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=660895242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.660895242
Directory	/workspace/45.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/45.otp_ctrl_regwen.3300592637
Short name	T389
Test name
Test status
Simulation time	157955732 ps
CPU time	5.44 seconds
Started	Apr 30 03:45:20 PM PDT 24
Finished	Apr 30 03:45:26 PM PDT 24
Peak memory	241376 kb
Host	smart-5e0d033f-c986-418b-ba8f-c3706da32e2c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3300592637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.3300592637
Directory	/workspace/45.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/45.otp_ctrl_smoke.3090440760
Short name	T846
Test name
Test status
Simulation time	171263909 ps
CPU time	4.51 seconds
Started	Apr 30 03:45:18 PM PDT 24
Finished	Apr 30 03:45:23 PM PDT 24
Peak memory	241536 kb
Host	smart-3bc9b6ec-0783-4582-8402-cf92c462b6c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3090440760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.3090440760
Directory	/workspace/45.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.otp_ctrl_stress_all.2162268275
Short name	T1168
Test name
Test status
Simulation time	105410720410 ps
CPU time	362.38 seconds
Started	Apr 30 03:45:21 PM PDT 24
Finished	Apr 30 03:51:24 PM PDT 24
Peak memory	266276 kb
Host	smart-050ba8d4-96e5-404d-b7e0-27d413e3777e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162268275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all .2162268275
Directory	/workspace/45.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.otp_ctrl_test_access.1058398994
Short name	T447
Test name
Test status
Simulation time	659227540 ps
CPU time	11.18 seconds
Started	Apr 30 03:45:21 PM PDT 24
Finished	Apr 30 03:45:33 PM PDT 24
Peak memory	241644 kb
Host	smart-94d8b42a-7c1b-4f83-97c6-ee5801ee65f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1058398994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.1058398994
Directory	/workspace/45.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/46.otp_ctrl_alert_test.246355758
Short name	T567
Test name
Test status
Simulation time	792359072 ps
CPU time	1.7 seconds
Started	Apr 30 03:45:30 PM PDT 24
Finished	Apr 30 03:45:32 PM PDT 24
Peak memory	240228 kb
Host	smart-93ad29cf-1afc-46dc-a2e3-b9be80e6a852
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246355758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.246355758
Directory	/workspace/46.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.otp_ctrl_check_fail.3757334108
Short name	T44
Test name
Test status
Simulation time	2263921806 ps
CPU time	18.91 seconds
Started	Apr 30 03:45:30 PM PDT 24
Finished	Apr 30 03:45:50 PM PDT 24
Peak memory	241704 kb
Host	smart-1f3f9ebc-e5fb-48dd-ba79-3209b1ce907c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3757334108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.3757334108
Directory	/workspace/46.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/46.otp_ctrl_dai_errs.3085305723
Short name	T432
Test name
Test status
Simulation time	6043373611 ps
CPU time	32.44 seconds
Started	Apr 30 03:45:29 PM PDT 24
Finished	Apr 30 03:46:02 PM PDT 24
Peak memory	241560 kb
Host	smart-6bf6c618-ba5e-4b66-a65c-f3a50bca26b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085305723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.3085305723
Directory	/workspace/46.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/46.otp_ctrl_dai_lock.1800251485
Short name	T658
Test name
Test status
Simulation time	1796624320 ps
CPU time	26.53 seconds
Started	Apr 30 03:45:26 PM PDT 24
Finished	Apr 30 03:45:53 PM PDT 24
Peak memory	241720 kb
Host	smart-e3b359c6-95b2-4898-854b-4822361483ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800251485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.1800251485
Directory	/workspace/46.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/46.otp_ctrl_init_fail.2533086127
Short name	T740
Test name
Test status
Simulation time	91194718 ps
CPU time	3.14 seconds
Started	Apr 30 03:45:28 PM PDT 24
Finished	Apr 30 03:45:32 PM PDT 24
Peak memory	241332 kb
Host	smart-7aef96bd-49b6-4645-925e-f16f614576f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533086127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.2533086127
Directory	/workspace/46.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/46.otp_ctrl_macro_errs.3909201260
Short name	T881
Test name
Test status
Simulation time	11440548453 ps
CPU time	20.54 seconds
Started	Apr 30 03:45:29 PM PDT 24
Finished	Apr 30 03:45:50 PM PDT 24
Peak memory	242248 kb
Host	smart-bbd5259f-a3fe-4e96-80f1-ffb2b32c485c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3909201260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.3909201260
Directory	/workspace/46.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/46.otp_ctrl_parallel_key_req.4275749803
Short name	T110
Test name
Test status
Simulation time	242558962 ps
CPU time	11.4 seconds
Started	Apr 30 03:45:27 PM PDT 24
Finished	Apr 30 03:45:39 PM PDT 24
Peak memory	241332 kb
Host	smart-2b6a9e30-24c8-46fc-9335-5c18a752211e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275749803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.4275749803
Directory	/workspace/46.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.4091512890
Short name	T1123
Test name
Test status
Simulation time	334265786 ps
CPU time	5.93 seconds
Started	Apr 30 03:45:26 PM PDT 24
Finished	Apr 30 03:45:32 PM PDT 24
Peak memory	241256 kb
Host	smart-f3c30cbb-6252-4d31-aa3a-008991a88cd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091512890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.4091512890
Directory	/workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/46.otp_ctrl_parallel_lc_req.1773942840
Short name	T994
Test name
Test status
Simulation time	962494326 ps
CPU time	13.91 seconds
Started	Apr 30 03:45:27 PM PDT 24
Finished	Apr 30 03:45:41 PM PDT 24
Peak memory	247972 kb
Host	smart-84b52d5c-124c-4f28-9ef1-c970ab806245
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1773942840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.1773942840
Directory	/workspace/46.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/46.otp_ctrl_regwen.2749828593
Short name	T1102
Test name
Test status
Simulation time	3659217381 ps
CPU time	9.01 seconds
Started	Apr 30 03:45:32 PM PDT 24
Finished	Apr 30 03:45:41 PM PDT 24
Peak memory	241472 kb
Host	smart-299c4ee3-d29a-460f-b352-5ae28d8f8bcc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2749828593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.2749828593
Directory	/workspace/46.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/46.otp_ctrl_smoke.1456320627
Short name	T1027
Test name
Test status
Simulation time	482816621 ps
CPU time	5.96 seconds
Started	Apr 30 03:45:28 PM PDT 24
Finished	Apr 30 03:45:34 PM PDT 24
Peak memory	241568 kb
Host	smart-c5e89e97-8e32-4833-aef6-8aaeea4bd9b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1456320627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.1456320627
Directory	/workspace/46.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.3305856891
Short name	T1101
Test name
Test status
Simulation time	13739992338 ps
CPU time	383.42 seconds
Started	Apr 30 03:45:26 PM PDT 24
Finished	Apr 30 03:51:50 PM PDT 24
Peak memory	264588 kb
Host	smart-7b52b344-d993-47b4-8caa-20ba511198bc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305856891 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.3305856891
Directory	/workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.otp_ctrl_test_access.490526259
Short name	T279
Test name
Test status
Simulation time	4446045243 ps
CPU time	32.57 seconds
Started	Apr 30 03:45:30 PM PDT 24
Finished	Apr 30 03:46:02 PM PDT 24
Peak memory	242212 kb
Host	smart-e8927341-58d4-4c35-a84f-e2073f3223ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490526259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.490526259
Directory	/workspace/46.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/47.otp_ctrl_alert_test.3774390644
Short name	T321
Test name
Test status
Simulation time	742288673 ps
CPU time	2.16 seconds
Started	Apr 30 03:45:35 PM PDT 24
Finished	Apr 30 03:45:37 PM PDT 24
Peak memory	240068 kb
Host	smart-3bfee057-a9a9-49c5-a1ec-6a6cefdd50f0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774390644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.3774390644
Directory	/workspace/47.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.otp_ctrl_check_fail.3219577512
Short name	T880
Test name
Test status
Simulation time	380755299 ps
CPU time	5.66 seconds
Started	Apr 30 03:45:34 PM PDT 24
Finished	Apr 30 03:45:40 PM PDT 24
Peak memory	247932 kb
Host	smart-a0a87a78-160d-4dc1-83da-f15589c6d5f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3219577512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.3219577512
Directory	/workspace/47.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/47.otp_ctrl_dai_errs.1683003046
Short name	T727
Test name
Test status
Simulation time	647389829 ps
CPU time	18.86 seconds
Started	Apr 30 03:45:34 PM PDT 24
Finished	Apr 30 03:45:53 PM PDT 24
Peak memory	241428 kb
Host	smart-fa888780-777f-47db-958d-9e68459dba08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683003046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.1683003046
Directory	/workspace/47.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/47.otp_ctrl_dai_lock.3426559678
Short name	T699
Test name
Test status
Simulation time	1089371458 ps
CPU time	9.11 seconds
Started	Apr 30 03:45:34 PM PDT 24
Finished	Apr 30 03:45:44 PM PDT 24
Peak memory	241244 kb
Host	smart-f8366e9e-085c-405d-a8e7-4142870197c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426559678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.3426559678
Directory	/workspace/47.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/47.otp_ctrl_init_fail.531546949
Short name	T598
Test name
Test status
Simulation time	219497674 ps
CPU time	3.97 seconds
Started	Apr 30 03:45:29 PM PDT 24
Finished	Apr 30 03:45:33 PM PDT 24
Peak memory	241724 kb
Host	smart-71566086-b434-42b2-aa24-2ed582f09c30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=531546949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.531546949
Directory	/workspace/47.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/47.otp_ctrl_macro_errs.1929014033
Short name	T1129
Test name
Test status
Simulation time	4266520150 ps
CPU time	28.99 seconds
Started	Apr 30 03:45:33 PM PDT 24
Finished	Apr 30 03:46:02 PM PDT 24
Peak memory	244156 kb
Host	smart-6091a188-9e3b-4901-a897-1b82c583b19a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1929014033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.1929014033
Directory	/workspace/47.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/47.otp_ctrl_parallel_key_req.2921815268
Short name	T660
Test name
Test status
Simulation time	12542795766 ps
CPU time	25.46 seconds
Started	Apr 30 03:45:32 PM PDT 24
Finished	Apr 30 03:45:58 PM PDT 24
Peak memory	242296 kb
Host	smart-f512496b-92cc-4cd0-8749-8b824af4526c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921815268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.2921815268
Directory	/workspace/47.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.3348520759
Short name	T96
Test name
Test status
Simulation time	158692986 ps
CPU time	7.13 seconds
Started	Apr 30 03:45:34 PM PDT 24
Finished	Apr 30 03:45:41 PM PDT 24
Peak memory	241084 kb
Host	smart-75dffd8d-3e6a-495e-ac34-c26886709015
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348520759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.3348520759
Directory	/workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/47.otp_ctrl_parallel_lc_req.2066775532
Short name	T676
Test name
Test status
Simulation time	9812788839 ps
CPU time	23.15 seconds
Started	Apr 30 03:45:35 PM PDT 24
Finished	Apr 30 03:45:59 PM PDT 24
Peak memory	241532 kb
Host	smart-b8aedb5b-3edc-4bb8-b43b-c64ed5998a6a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2066775532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.2066775532
Directory	/workspace/47.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/47.otp_ctrl_regwen.173463877
Short name	T153
Test name
Test status
Simulation time	141324602 ps
CPU time	4.02 seconds
Started	Apr 30 03:45:35 PM PDT 24
Finished	Apr 30 03:45:39 PM PDT 24
Peak memory	241320 kb
Host	smart-03836152-3ef4-497f-8dfd-c12da8cdd89e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=173463877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.173463877
Directory	/workspace/47.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/47.otp_ctrl_smoke.1844366014
Short name	T427
Test name
Test status
Simulation time	951321205 ps
CPU time	11.33 seconds
Started	Apr 30 03:45:26 PM PDT 24
Finished	Apr 30 03:45:37 PM PDT 24
Peak memory	241324 kb
Host	smart-88ed92bb-c51d-4604-afc6-69f626665c08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1844366014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.1844366014
Directory	/workspace/47.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.otp_ctrl_stress_all.2087665068
Short name	T1095
Test name
Test status
Simulation time	14884428517 ps
CPU time	184.43 seconds
Started	Apr 30 03:45:34 PM PDT 24
Finished	Apr 30 03:48:39 PM PDT 24
Peak memory	272696 kb
Host	smart-e0673742-effd-4f00-8135-20616359b4c2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087665068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all .2087665068
Directory	/workspace/47.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.624198503
Short name	T294
Test name
Test status
Simulation time	1379010225267 ps
CPU time	1870.41 seconds
Started	Apr 30 03:45:37 PM PDT 24
Finished	Apr 30 04:16:48 PM PDT 24
Peak memory	499728 kb
Host	smart-2bbe5a94-85d0-4400-ac99-380a9f9ceca5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624198503 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.624198503
Directory	/workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.otp_ctrl_test_access.1636442569
Short name	T838
Test name
Test status
Simulation time	1168353249 ps
CPU time	18.22 seconds
Started	Apr 30 03:45:33 PM PDT 24
Finished	Apr 30 03:45:52 PM PDT 24
Peak memory	241276 kb
Host	smart-89ea8fc4-3a09-4c49-8fa0-2a23e9c047c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1636442569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.1636442569
Directory	/workspace/47.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/48.otp_ctrl_alert_test.1636252342
Short name	T596
Test name
Test status
Simulation time	243842844 ps
CPU time	1.99 seconds
Started	Apr 30 03:45:47 PM PDT 24
Finished	Apr 30 03:45:50 PM PDT 24
Peak memory	240184 kb
Host	smart-4cdba307-6a1f-4297-a20a-6852ff31015e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636252342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.1636252342
Directory	/workspace/48.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.otp_ctrl_check_fail.3844948310
Short name	T968
Test name
Test status
Simulation time	2652889010 ps
CPU time	15.77 seconds
Started	Apr 30 03:45:38 PM PDT 24
Finished	Apr 30 03:45:55 PM PDT 24
Peak memory	248100 kb
Host	smart-07f583de-fa77-4c4b-9d93-84ac662e01cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3844948310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.3844948310
Directory	/workspace/48.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/48.otp_ctrl_dai_errs.3795642967
Short name	T629
Test name
Test status
Simulation time	274714797 ps
CPU time	15.25 seconds
Started	Apr 30 03:45:40 PM PDT 24
Finished	Apr 30 03:45:56 PM PDT 24
Peak memory	241284 kb
Host	smart-587b58f8-7331-4125-8084-d1582c776ac0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795642967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.3795642967
Directory	/workspace/48.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/48.otp_ctrl_dai_lock.4153437900
Short name	T678
Test name
Test status
Simulation time	377406990 ps
CPU time	14.37 seconds
Started	Apr 30 03:45:39 PM PDT 24
Finished	Apr 30 03:45:54 PM PDT 24
Peak memory	241612 kb
Host	smart-43ffdb05-e285-4787-bba2-81111c0488b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4153437900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.4153437900
Directory	/workspace/48.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/48.otp_ctrl_init_fail.2517832764
Short name	T536
Test name
Test status
Simulation time	130961997 ps
CPU time	3.66 seconds
Started	Apr 30 03:45:42 PM PDT 24
Finished	Apr 30 03:45:46 PM PDT 24
Peak memory	241684 kb
Host	smart-b7344f9a-bc3f-474e-b165-87daba3c37f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2517832764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.2517832764
Directory	/workspace/48.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/48.otp_ctrl_macro_errs.4175306591
Short name	T1131
Test name
Test status
Simulation time	1278165055 ps
CPU time	17.32 seconds
Started	Apr 30 03:45:39 PM PDT 24
Finished	Apr 30 03:45:57 PM PDT 24
Peak memory	241796 kb
Host	smart-c066de6d-9df8-467e-9d93-5020c39651f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175306591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.4175306591
Directory	/workspace/48.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/48.otp_ctrl_parallel_key_req.3904756048
Short name	T845
Test name
Test status
Simulation time	871465425 ps
CPU time	21.4 seconds
Started	Apr 30 03:45:39 PM PDT 24
Finished	Apr 30 03:46:01 PM PDT 24
Peak memory	241416 kb
Host	smart-45da68c6-6ef3-4aa6-91b1-82350f2217e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3904756048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.3904756048
Directory	/workspace/48.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.4250068039
Short name	T4
Test name
Test status
Simulation time	1204455311 ps
CPU time	28.02 seconds
Started	Apr 30 03:45:39 PM PDT 24
Finished	Apr 30 03:46:07 PM PDT 24
Peak memory	241200 kb
Host	smart-423de861-29a7-4776-8e93-52aff2276998
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4250068039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.4250068039
Directory	/workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/48.otp_ctrl_parallel_lc_req.312112316
Short name	T597
Test name
Test status
Simulation time	1360492621 ps
CPU time	22.48 seconds
Started	Apr 30 03:45:41 PM PDT 24
Finished	Apr 30 03:46:04 PM PDT 24
Peak memory	247968 kb
Host	smart-67977016-7585-4eb8-b1f1-5203e8cc44b0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=312112316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.312112316
Directory	/workspace/48.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/48.otp_ctrl_regwen.2479659392
Short name	T689
Test name
Test status
Simulation time	342415168 ps
CPU time	5.62 seconds
Started	Apr 30 03:45:42 PM PDT 24
Finished	Apr 30 03:45:48 PM PDT 24
Peak memory	241352 kb
Host	smart-a063dca5-c8fb-4eea-ba8d-c0afe056cf7b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2479659392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.2479659392
Directory	/workspace/48.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/48.otp_ctrl_smoke.751419013
Short name	T439
Test name
Test status
Simulation time	385575627 ps
CPU time	4.79 seconds
Started	Apr 30 03:45:39 PM PDT 24
Finished	Apr 30 03:45:45 PM PDT 24
Peak memory	241172 kb
Host	smart-e919b5b5-ed03-416a-b1ba-de5dd5291b2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751419013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.751419013
Directory	/workspace/48.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.otp_ctrl_stress_all.4147940036
Short name	T253
Test name
Test status
Simulation time	21147784877 ps
CPU time	259.63 seconds
Started	Apr 30 03:45:41 PM PDT 24
Finished	Apr 30 03:50:01 PM PDT 24
Peak memory	256312 kb
Host	smart-51288813-65b8-42cb-900f-1b24177a8faa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147940036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all .4147940036
Directory	/workspace/48.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.1467735899
Short name	T810
Test name
Test status
Simulation time	84963690489 ps
CPU time	565.57 seconds
Started	Apr 30 03:45:38 PM PDT 24
Finished	Apr 30 03:55:05 PM PDT 24
Peak memory	261116 kb
Host	smart-2d0ca286-8b6d-4204-8375-c1f5e823dd2f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467735899 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.1467735899
Directory	/workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.otp_ctrl_test_access.1188098643
Short name	T503
Test name
Test status
Simulation time	1646124003 ps
CPU time	19.94 seconds
Started	Apr 30 03:45:38 PM PDT 24
Finished	Apr 30 03:45:59 PM PDT 24
Peak memory	247972 kb
Host	smart-12b105aa-f5ba-4df4-b9e0-8c64dfed6db9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188098643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1188098643
Directory	/workspace/48.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/49.otp_ctrl_alert_test.1579740642
Short name	T420
Test name
Test status
Simulation time	626185971 ps
CPU time	1.88 seconds
Started	Apr 30 03:45:53 PM PDT 24
Finished	Apr 30 03:45:55 PM PDT 24
Peak memory	239760 kb
Host	smart-04640be7-e9c7-4000-8e17-71e5c1eb809f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579740642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.1579740642
Directory	/workspace/49.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.otp_ctrl_check_fail.3325506764
Short name	T983
Test name
Test status
Simulation time	1315829499 ps
CPU time	12.87 seconds
Started	Apr 30 03:45:56 PM PDT 24
Finished	Apr 30 03:46:10 PM PDT 24
Peak memory	241356 kb
Host	smart-50ee2969-b9ac-4b70-81fd-94e3ad75cbd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325506764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.3325506764
Directory	/workspace/49.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/49.otp_ctrl_dai_errs.1193992786
Short name	T330
Test name
Test status
Simulation time	311716376 ps
CPU time	18.55 seconds
Started	Apr 30 03:45:46 PM PDT 24
Finished	Apr 30 03:46:05 PM PDT 24
Peak memory	241364 kb
Host	smart-c00a4a95-8062-4779-b157-6ae5497af532
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1193992786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.1193992786
Directory	/workspace/49.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/49.otp_ctrl_dai_lock.34516368
Short name	T647
Test name
Test status
Simulation time	1147318132 ps
CPU time	22.74 seconds
Started	Apr 30 03:45:45 PM PDT 24
Finished	Apr 30 03:46:08 PM PDT 24
Peak memory	247892 kb
Host	smart-3ebf74ed-9bf1-4cd5-a1c7-8ae7c2e87e53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34516368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.34516368
Directory	/workspace/49.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/49.otp_ctrl_init_fail.1629781977
Short name	T712
Test name
Test status
Simulation time	194943479 ps
CPU time	4.02 seconds
Started	Apr 30 03:45:47 PM PDT 24
Finished	Apr 30 03:45:51 PM PDT 24
Peak memory	241620 kb
Host	smart-85b104b1-59e6-4ab8-afac-5d4fa7f120b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629781977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.1629781977
Directory	/workspace/49.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/49.otp_ctrl_macro_errs.2594154360
Short name	T817
Test name
Test status
Simulation time	1351891777 ps
CPU time	25.13 seconds
Started	Apr 30 03:45:53 PM PDT 24
Finished	Apr 30 03:46:18 PM PDT 24
Peak memory	243112 kb
Host	smart-b8983187-83a6-4914-8954-93d322774b1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2594154360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.2594154360
Directory	/workspace/49.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/49.otp_ctrl_parallel_key_req.595487498
Short name	T946
Test name
Test status
Simulation time	4617818227 ps
CPU time	12.84 seconds
Started	Apr 30 03:45:56 PM PDT 24
Finished	Apr 30 03:46:09 PM PDT 24
Peak memory	242016 kb
Host	smart-841f75b3-2fdf-4fd5-863c-fa014017f59d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=595487498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.595487498
Directory	/workspace/49.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.539794709
Short name	T729
Test name
Test status
Simulation time	1254056850 ps
CPU time	11.16 seconds
Started	Apr 30 03:45:46 PM PDT 24
Finished	Apr 30 03:45:58 PM PDT 24
Peak memory	241324 kb
Host	smart-b4fc16f9-be53-498b-bb6a-dff9a6f80bd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=539794709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.539794709
Directory	/workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/49.otp_ctrl_parallel_lc_req.17962449
Short name	T521
Test name
Test status
Simulation time	408121613 ps
CPU time	6.24 seconds
Started	Apr 30 03:45:46 PM PDT 24
Finished	Apr 30 03:45:53 PM PDT 24
Peak memory	241356 kb
Host	smart-ca950bdc-8aae-4165-b94d-12c89ddaffc0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=17962449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.17962449
Directory	/workspace/49.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/49.otp_ctrl_regwen.1726421235
Short name	T396
Test name
Test status
Simulation time	144829348 ps
CPU time	5.16 seconds
Started	Apr 30 03:45:54 PM PDT 24
Finished	Apr 30 03:46:00 PM PDT 24
Peak memory	241276 kb
Host	smart-055fba23-bb22-4164-bc61-18818f4f3122
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1726421235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.1726421235
Directory	/workspace/49.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/49.otp_ctrl_smoke.2467503392
Short name	T471
Test name
Test status
Simulation time	2456568270 ps
CPU time	6.37 seconds
Started	Apr 30 03:45:49 PM PDT 24
Finished	Apr 30 03:45:56 PM PDT 24
Peak memory	241276 kb
Host	smart-3612a028-71d3-412d-be10-6520f9177b22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2467503392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2467503392
Directory	/workspace/49.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.otp_ctrl_stress_all.1534782265
Short name	T152
Test name
Test status
Simulation time	21750047537 ps
CPU time	65.79 seconds
Started	Apr 30 03:45:55 PM PDT 24
Finished	Apr 30 03:47:01 PM PDT 24
Peak memory	244332 kb
Host	smart-5406adc1-0244-4455-b708-10f2e86da3e3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534782265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all .1534782265
Directory	/workspace/49.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.192551254
Short name	T359
Test name
Test status
Simulation time	116214980355 ps
CPU time	1184.62 seconds
Started	Apr 30 03:45:54 PM PDT 24
Finished	Apr 30 04:05:39 PM PDT 24
Peak memory	261344 kb
Host	smart-6303e251-9929-4cb1-a6dc-1612c541ce6e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192551254 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.192551254
Directory	/workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.otp_ctrl_test_access.489798432
Short name	T13
Test name
Test status
Simulation time	1304959093 ps
CPU time	9.33 seconds
Started	Apr 30 03:45:54 PM PDT 24
Finished	Apr 30 03:46:04 PM PDT 24
Peak memory	241316 kb
Host	smart-09b20708-376b-4df4-a4e2-8187ac0dca0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=489798432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.489798432
Directory	/workspace/49.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/5.otp_ctrl_alert_test.2797146868
Short name	T696
Test name
Test status
Simulation time	78947000 ps
CPU time	1.83 seconds
Started	Apr 30 03:40:46 PM PDT 24
Finished	Apr 30 03:40:48 PM PDT 24
Peak memory	239508 kb
Host	smart-a0485a44-a97b-47c0-a31c-c9706eebd4c2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797146868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.2797146868
Directory	/workspace/5.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.otp_ctrl_background_chks.3494973439
Short name	T1039
Test name
Test status
Simulation time	1125921467 ps
CPU time	7.59 seconds
Started	Apr 30 03:40:35 PM PDT 24
Finished	Apr 30 03:40:43 PM PDT 24
Peak memory	241316 kb
Host	smart-42ec0601-5bf5-4667-8367-d9bb2350e107
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494973439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.3494973439
Directory	/workspace/5.otp_ctrl_background_chks/latest

Test location	/workspace/coverage/default/5.otp_ctrl_check_fail.2512250437
Short name	T912
Test name
Test status
Simulation time	1078092022 ps
CPU time	22.44 seconds
Started	Apr 30 03:40:43 PM PDT 24
Finished	Apr 30 03:41:06 PM PDT 24
Peak memory	248060 kb
Host	smart-03187536-e1ab-4c90-b60f-7215584994fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2512250437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.2512250437
Directory	/workspace/5.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/5.otp_ctrl_dai_errs.1080023613
Short name	T698
Test name
Test status
Simulation time	3601717334 ps
CPU time	15.02 seconds
Started	Apr 30 03:40:37 PM PDT 24
Finished	Apr 30 03:40:52 PM PDT 24
Peak memory	241628 kb
Host	smart-49b6def9-4582-4d46-a734-93474ec25e78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080023613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.1080023613
Directory	/workspace/5.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/5.otp_ctrl_dai_lock.4130267109
Short name	T1080
Test name
Test status
Simulation time	740805674 ps
CPU time	17.99 seconds
Started	Apr 30 03:40:37 PM PDT 24
Finished	Apr 30 03:40:56 PM PDT 24
Peak memory	241368 kb
Host	smart-4eaeb8bb-ec77-4419-af88-43346f3265ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4130267109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.4130267109
Directory	/workspace/5.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/5.otp_ctrl_init_fail.4235892048
Short name	T1011
Test name
Test status
Simulation time	140940730 ps
CPU time	3.84 seconds
Started	Apr 30 03:40:34 PM PDT 24
Finished	Apr 30 03:40:38 PM PDT 24
Peak memory	241476 kb
Host	smart-c8be513a-b16d-4447-b679-83d0760a0185
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235892048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.4235892048
Directory	/workspace/5.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/5.otp_ctrl_macro_errs.2631186170
Short name	T1083
Test name
Test status
Simulation time	6627130453 ps
CPU time	43.27 seconds
Started	Apr 30 03:40:41 PM PDT 24
Finished	Apr 30 03:41:25 PM PDT 24
Peak memory	246260 kb
Host	smart-7e0d2b28-d7bd-46fe-93aa-2a84c682b4c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2631186170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.2631186170
Directory	/workspace/5.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/5.otp_ctrl_parallel_key_req.4220038614
Short name	T848
Test name
Test status
Simulation time	16844787801 ps
CPU time	35.31 seconds
Started	Apr 30 03:40:44 PM PDT 24
Finished	Apr 30 03:41:20 PM PDT 24
Peak memory	242608 kb
Host	smart-502a9113-533a-474b-a48b-96dfca3fbaa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220038614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.4220038614
Directory	/workspace/5.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.2743481013
Short name	T215
Test name
Test status
Simulation time	735415817 ps
CPU time	10.51 seconds
Started	Apr 30 03:40:38 PM PDT 24
Finished	Apr 30 03:40:49 PM PDT 24
Peak memory	241392 kb
Host	smart-cf9ed4fa-4559-405d-bd43-cc50b6540cd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743481013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.2743481013
Directory	/workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/5.otp_ctrl_parallel_lc_req.2295728621
Short name	T9
Test name
Test status
Simulation time	129192903 ps
CPU time	4 seconds
Started	Apr 30 03:40:38 PM PDT 24
Finished	Apr 30 03:40:42 PM PDT 24
Peak memory	241228 kb
Host	smart-42eac65e-c596-48d1-bc9f-54991ccc4d2d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2295728621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.2295728621
Directory	/workspace/5.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/5.otp_ctrl_regwen.3836918268
Short name	T991
Test name
Test status
Simulation time	353213906 ps
CPU time	12.13 seconds
Started	Apr 30 03:40:43 PM PDT 24
Finished	Apr 30 03:40:56 PM PDT 24
Peak memory	241644 kb
Host	smart-e9eaa50c-4403-4d84-9b7b-83db5c76c88b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3836918268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.3836918268
Directory	/workspace/5.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/5.otp_ctrl_smoke.2204776286
Short name	T1015
Test name
Test status
Simulation time	373595038 ps
CPU time	10.19 seconds
Started	Apr 30 03:40:31 PM PDT 24
Finished	Apr 30 03:40:42 PM PDT 24
Peak memory	247896 kb
Host	smart-4270c711-8393-41a8-bf88-66524eb02d53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2204776286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.2204776286
Directory	/workspace/5.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.otp_ctrl_stress_all.413541052
Short name	T896
Test name
Test status
Simulation time	2315769045 ps
CPU time	6.07 seconds
Started	Apr 30 03:40:40 PM PDT 24
Finished	Apr 30 03:40:46 PM PDT 24
Peak memory	240716 kb
Host	smart-75ba0d33-f396-4468-8320-a657e66629e4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413541052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.413541052
Directory	/workspace/5.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.3348134462
Short name	T33
Test name
Test status
Simulation time	650853454413 ps
CPU time	1629.04 seconds
Started	Apr 30 03:40:43 PM PDT 24
Finished	Apr 30 04:07:53 PM PDT 24
Peak memory	441316 kb
Host	smart-a2a1c0dd-c245-477d-9107-617545df3753
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348134462 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.3348134462
Directory	/workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.otp_ctrl_test_access.1770803042
Short name	T954
Test name
Test status
Simulation time	2510834625 ps
CPU time	29.41 seconds
Started	Apr 30 03:40:42 PM PDT 24
Finished	Apr 30 03:41:11 PM PDT 24
Peak memory	248100 kb
Host	smart-e8509759-95e6-49ec-ae8b-d77b2a02eed9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770803042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.1770803042
Directory	/workspace/5.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/50.otp_ctrl_init_fail.389303911
Short name	T811
Test name
Test status
Simulation time	363097806 ps
CPU time	5.09 seconds
Started	Apr 30 03:45:53 PM PDT 24
Finished	Apr 30 03:45:59 PM PDT 24
Peak memory	241812 kb
Host	smart-758cab53-1d1d-4164-89a5-0e0bdf0fffa8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=389303911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.389303911
Directory	/workspace/50.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.627491036
Short name	T227
Test name
Test status
Simulation time	394464567 ps
CPU time	11.81 seconds
Started	Apr 30 03:45:53 PM PDT 24
Finished	Apr 30 03:46:05 PM PDT 24
Peak memory	241488 kb
Host	smart-1f2a1329-6934-486c-b336-2ec47ed2b312
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627491036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.627491036
Directory	/workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/51.otp_ctrl_init_fail.810477330
Short name	T91
Test name
Test status
Simulation time	112867347 ps
CPU time	3.88 seconds
Started	Apr 30 03:45:52 PM PDT 24
Finished	Apr 30 03:45:57 PM PDT 24
Peak memory	241844 kb
Host	smart-43c2284b-5cb0-4a99-b6ff-e6e0b1b64f22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=810477330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.810477330
Directory	/workspace/51.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.726244090
Short name	T1001
Test name
Test status
Simulation time	209616139 ps
CPU time	5.97 seconds
Started	Apr 30 03:45:57 PM PDT 24
Finished	Apr 30 03:46:04 PM PDT 24
Peak memory	241332 kb
Host	smart-a563aba6-8038-4387-9edc-7052d53050dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=726244090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.726244090
Directory	/workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.3668241915
Short name	T280
Test name
Test status
Simulation time	1039305146333 ps
CPU time	2798.75 seconds
Started	Apr 30 03:45:53 PM PDT 24
Finished	Apr 30 04:32:32 PM PDT 24
Peak memory	276620 kb
Host	smart-a77bd8e4-4744-4088-88ff-a54f95388e28
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668241915 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.3668241915
Directory	/workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/52.otp_ctrl_init_fail.44024093
Short name	T143
Test name
Test status
Simulation time	131787833 ps
CPU time	3.03 seconds
Started	Apr 30 03:45:54 PM PDT 24
Finished	Apr 30 03:45:58 PM PDT 24
Peak memory	241416 kb
Host	smart-420bdb53-1b40-4ce3-8225-c8e6d67c217a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44024093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.44024093
Directory	/workspace/52.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.2384738965
Short name	T709
Test name
Test status
Simulation time	3562215283 ps
CPU time	8.95 seconds
Started	Apr 30 03:45:53 PM PDT 24
Finished	Apr 30 03:46:03 PM PDT 24
Peak memory	241640 kb
Host	smart-751687b0-85bf-413f-aa00-e11359474298
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384738965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.2384738965
Directory	/workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/53.otp_ctrl_init_fail.3580794261
Short name	T873
Test name
Test status
Simulation time	2282784777 ps
CPU time	5.42 seconds
Started	Apr 30 03:45:57 PM PDT 24
Finished	Apr 30 03:46:03 PM PDT 24
Peak memory	241544 kb
Host	smart-0881aa7e-8a38-4c1d-9ab2-281efdebc88f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580794261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.3580794261
Directory	/workspace/53.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.679771206
Short name	T981
Test name
Test status
Simulation time	1293451326 ps
CPU time	11.46 seconds
Started	Apr 30 03:45:52 PM PDT 24
Finished	Apr 30 03:46:04 PM PDT 24
Peak memory	241536 kb
Host	smart-145ae95a-d18b-4bca-966a-b2a41c894489
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=679771206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.679771206
Directory	/workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.2664461151
Short name	T941
Test name
Test status
Simulation time	80383079508 ps
CPU time	566.99 seconds
Started	Apr 30 03:45:52 PM PDT 24
Finished	Apr 30 03:55:20 PM PDT 24
Peak memory	339792 kb
Host	smart-ff412803-09c0-47c3-9968-a58631d5bd38
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664461151 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.2664461151
Directory	/workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/54.otp_ctrl_init_fail.1483042632
Short name	T844
Test name
Test status
Simulation time	629642208 ps
CPU time	5.21 seconds
Started	Apr 30 03:45:56 PM PDT 24
Finished	Apr 30 03:46:02 PM PDT 24
Peak memory	241776 kb
Host	smart-30685dc1-5cdd-4876-b431-dc72bc158911
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483042632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.1483042632
Directory	/workspace/54.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.958387666
Short name	T829
Test name
Test status
Simulation time	114436088 ps
CPU time	3.88 seconds
Started	Apr 30 03:45:59 PM PDT 24
Finished	Apr 30 03:46:03 PM PDT 24
Peak memory	241592 kb
Host	smart-81879167-68c4-45c2-919b-c9d8a57a84bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958387666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.958387666
Directory	/workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.3830801185
Short name	T339
Test name
Test status
Simulation time	128293266463 ps
CPU time	656.81 seconds
Started	Apr 30 03:45:58 PM PDT 24
Finished	Apr 30 03:56:56 PM PDT 24
Peak memory	266684 kb
Host	smart-fd7b45a0-3b42-4d5f-9cdb-c77c2605b215
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830801185 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.3830801185
Directory	/workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/55.otp_ctrl_init_fail.3739594194
Short name	T135
Test name
Test status
Simulation time	228581293 ps
CPU time	4.61 seconds
Started	Apr 30 03:46:01 PM PDT 24
Finished	Apr 30 03:46:06 PM PDT 24
Peak memory	241668 kb
Host	smart-d3451bfd-d281-452c-b4b0-d8a133269345
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739594194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.3739594194
Directory	/workspace/55.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.2650068812
Short name	T358
Test name
Test status
Simulation time	140646246 ps
CPU time	4.05 seconds
Started	Apr 30 03:45:59 PM PDT 24
Finished	Apr 30 03:46:04 PM PDT 24
Peak memory	241276 kb
Host	smart-59951a5e-2ad9-4bf5-8bcb-efea0f858af8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2650068812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.2650068812
Directory	/workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.3179381104
Short name	T406
Test name
Test status
Simulation time	160207345868 ps
CPU time	2590.46 seconds
Started	Apr 30 03:46:02 PM PDT 24
Finished	Apr 30 04:29:13 PM PDT 24
Peak memory	556836 kb
Host	smart-6df09bca-3112-4e04-961f-e60d3ee3af34
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179381104 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.3179381104
Directory	/workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.2849840952
Short name	T220
Test name
Test status
Simulation time	135019511 ps
CPU time	4.46 seconds
Started	Apr 30 03:46:00 PM PDT 24
Finished	Apr 30 03:46:05 PM PDT 24
Peak memory	241208 kb
Host	smart-11cfccb0-9ea4-4a03-86ee-3bfdb27fba49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2849840952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.2849840952
Directory	/workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.4074542680
Short name	T411
Test name
Test status
Simulation time	906949356347 ps
CPU time	1709.59 seconds
Started	Apr 30 03:46:01 PM PDT 24
Finished	Apr 30 04:14:31 PM PDT 24
Peak memory	451008 kb
Host	smart-2af61957-5f7d-4955-accb-87ed40dabe6c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074542680 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.4074542680
Directory	/workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/57.otp_ctrl_init_fail.1445255443
Short name	T83
Test name
Test status
Simulation time	278404925 ps
CPU time	4.26 seconds
Started	Apr 30 03:46:01 PM PDT 24
Finished	Apr 30 03:46:05 PM PDT 24
Peak memory	241424 kb
Host	smart-a031e088-b58f-4022-91de-63145946eaae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1445255443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.1445255443
Directory	/workspace/57.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.1253819962
Short name	T554
Test name
Test status
Simulation time	474469049 ps
CPU time	11.34 seconds
Started	Apr 30 03:46:02 PM PDT 24
Finished	Apr 30 03:46:14 PM PDT 24
Peak memory	241516 kb
Host	smart-61957802-dad5-48d9-b218-9c2b998cc09d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1253819962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.1253819962
Directory	/workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.2459694285
Short name	T412
Test name
Test status
Simulation time	109830038006 ps
CPU time	1276.39 seconds
Started	Apr 30 03:46:07 PM PDT 24
Finished	Apr 30 04:07:24 PM PDT 24
Peak memory	324692 kb
Host	smart-ca6eb587-2507-415f-b6de-9a911577895f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459694285 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.2459694285
Directory	/workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/58.otp_ctrl_init_fail.4076587075
Short name	T933
Test name
Test status
Simulation time	1619753355 ps
CPU time	4.56 seconds
Started	Apr 30 03:46:06 PM PDT 24
Finished	Apr 30 03:46:11 PM PDT 24
Peak memory	241700 kb
Host	smart-e9ae104d-58bf-4025-babe-d6ea575a7d29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4076587075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.4076587075
Directory	/workspace/58.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.906190150
Short name	T932
Test name
Test status
Simulation time	3747950125 ps
CPU time	8.18 seconds
Started	Apr 30 03:46:05 PM PDT 24
Finished	Apr 30 03:46:14 PM PDT 24
Peak memory	241940 kb
Host	smart-b9cda5c9-4f93-4829-937b-16b657f28b13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=906190150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.906190150
Directory	/workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.309754957
Short name	T668
Test name
Test status
Simulation time	106182387736 ps
CPU time	1518.17 seconds
Started	Apr 30 03:46:07 PM PDT 24
Finished	Apr 30 04:11:26 PM PDT 24
Peak memory	297468 kb
Host	smart-c1aa0573-6930-40e4-b2b9-9b3af653da6b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309754957 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.309754957
Directory	/workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/59.otp_ctrl_init_fail.2442940101
Short name	T1099
Test name
Test status
Simulation time	230929010 ps
CPU time	3.23 seconds
Started	Apr 30 03:46:04 PM PDT 24
Finished	Apr 30 03:46:08 PM PDT 24
Peak memory	241736 kb
Host	smart-aa3ba997-391f-4d03-b233-a259363b7793
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442940101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.2442940101
Directory	/workspace/59.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/6.otp_ctrl_alert_test.3392666555
Short name	T1189
Test name
Test status
Simulation time	668055006 ps
CPU time	1.81 seconds
Started	Apr 30 03:40:54 PM PDT 24
Finished	Apr 30 03:40:57 PM PDT 24
Peak memory	239796 kb
Host	smart-c2b2bcf9-f36b-4bae-96ae-938d676fe73d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392666555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.3392666555
Directory	/workspace/6.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.otp_ctrl_background_chks.1333868136
Short name	T127
Test name
Test status
Simulation time	1509592808 ps
CPU time	28 seconds
Started	Apr 30 03:40:47 PM PDT 24
Finished	Apr 30 03:41:15 PM PDT 24
Peak memory	241164 kb
Host	smart-e9316972-a2d7-4f9a-8d54-eefada3088dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1333868136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.1333868136
Directory	/workspace/6.otp_ctrl_background_chks/latest

Test location	/workspace/coverage/default/6.otp_ctrl_check_fail.2462574796
Short name	T45
Test name
Test status
Simulation time	1184187280 ps
CPU time	19.95 seconds
Started	Apr 30 03:40:48 PM PDT 24
Finished	Apr 30 03:41:09 PM PDT 24
Peak memory	247980 kb
Host	smart-90936825-1dc9-4251-bdc4-340dbd13b9e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2462574796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.2462574796
Directory	/workspace/6.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/6.otp_ctrl_dai_errs.3778395579
Short name	T205
Test name
Test status
Simulation time	798831279 ps
CPU time	18.3 seconds
Started	Apr 30 03:40:45 PM PDT 24
Finished	Apr 30 03:41:04 PM PDT 24
Peak memory	241364 kb
Host	smart-6c5dcc2f-e0fa-45d3-a005-242cd155d966
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3778395579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.3778395579
Directory	/workspace/6.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/6.otp_ctrl_dai_lock.2503678487
Short name	T319
Test name
Test status
Simulation time	1254184387 ps
CPU time	11.51 seconds
Started	Apr 30 03:40:43 PM PDT 24
Finished	Apr 30 03:40:55 PM PDT 24
Peak memory	247936 kb
Host	smart-6a1405f9-178c-4688-9819-66e6d8c631f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2503678487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.2503678487
Directory	/workspace/6.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/6.otp_ctrl_init_fail.216104466
Short name	T196
Test name
Test status
Simulation time	416602412 ps
CPU time	4.02 seconds
Started	Apr 30 03:40:45 PM PDT 24
Finished	Apr 30 03:40:50 PM PDT 24
Peak memory	241312 kb
Host	smart-88075cd9-8541-4aae-8a93-02c36c11626e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216104466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.216104466
Directory	/workspace/6.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/6.otp_ctrl_parallel_key_req.4130998055
Short name	T892
Test name
Test status
Simulation time	522694435 ps
CPU time	20.6 seconds
Started	Apr 30 03:40:48 PM PDT 24
Finished	Apr 30 03:41:09 PM PDT 24
Peak memory	247928 kb
Host	smart-6029cd01-3320-4e3e-ba72-3e4a4191cfa9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4130998055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.4130998055
Directory	/workspace/6.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.252890881
Short name	T1163
Test name
Test status
Simulation time	156818544 ps
CPU time	6.57 seconds
Started	Apr 30 03:40:44 PM PDT 24
Finished	Apr 30 03:40:51 PM PDT 24
Peak memory	241376 kb
Host	smart-26f881cf-a460-462c-8c5f-25d55325d24f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=252890881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.252890881
Directory	/workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/6.otp_ctrl_parallel_lc_req.1010827555
Short name	T708
Test name
Test status
Simulation time	617600553 ps
CPU time	18.17 seconds
Started	Apr 30 03:40:47 PM PDT 24
Finished	Apr 30 03:41:06 PM PDT 24
Peak memory	247952 kb
Host	smart-f87c0fa4-0bc2-49ba-b3ea-d80e21f4c9dc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1010827555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.1010827555
Directory	/workspace/6.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/6.otp_ctrl_regwen.68566228
Short name	T381
Test name
Test status
Simulation time	190957115 ps
CPU time	4.54 seconds
Started	Apr 30 03:40:48 PM PDT 24
Finished	Apr 30 03:40:53 PM PDT 24
Peak memory	241380 kb
Host	smart-4564e5ef-db04-47a2-8ac9-775744c1d56f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=68566228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.68566228
Directory	/workspace/6.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/6.otp_ctrl_smoke.461943414
Short name	T929
Test name
Test status
Simulation time	304335085 ps
CPU time	7.31 seconds
Started	Apr 30 03:40:45 PM PDT 24
Finished	Apr 30 03:40:52 PM PDT 24
Peak memory	241576 kb
Host	smart-54a15b6c-e5f1-4875-9d39-6c6c1260ea3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461943414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.461943414
Directory	/workspace/6.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.1582838836
Short name	T353
Test name
Test status
Simulation time	892731314574 ps
CPU time	1622.49 seconds
Started	Apr 30 03:40:50 PM PDT 24
Finished	Apr 30 04:07:53 PM PDT 24
Peak memory	272804 kb
Host	smart-8d227292-3d0e-40ea-b869-ff6fb4d2481c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582838836 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.1582838836
Directory	/workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.otp_ctrl_test_access.2745993985
Short name	T477
Test name
Test status
Simulation time	4985967518 ps
CPU time	25.32 seconds
Started	Apr 30 03:40:49 PM PDT 24
Finished	Apr 30 03:41:15 PM PDT 24
Peak memory	241828 kb
Host	smart-da9ee30e-831d-4256-993f-48c522ce9340
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2745993985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.2745993985
Directory	/workspace/6.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/60.otp_ctrl_init_fail.3866517414
Short name	T39
Test name
Test status
Simulation time	318980046 ps
CPU time	4.25 seconds
Started	Apr 30 03:46:08 PM PDT 24
Finished	Apr 30 03:46:13 PM PDT 24
Peak memory	241388 kb
Host	smart-b0111bbb-ae92-4ddf-b65d-bf5e5721bbe7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866517414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.3866517414
Directory	/workspace/60.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.3984966366
Short name	T219
Test name
Test status
Simulation time	163998017 ps
CPU time	6.66 seconds
Started	Apr 30 03:46:06 PM PDT 24
Finished	Apr 30 03:46:13 PM PDT 24
Peak memory	241256 kb
Host	smart-bc16af3a-ffb7-436e-b260-58bf954abb01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3984966366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.3984966366
Directory	/workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.3460520801
Short name	T295
Test name
Test status
Simulation time	263897211848 ps
CPU time	1272.61 seconds
Started	Apr 30 03:46:08 PM PDT 24
Finished	Apr 30 04:07:21 PM PDT 24
Peak memory	266040 kb
Host	smart-205745dd-93ae-42a4-8b59-f170ba8aec10
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460520801 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.3460520801
Directory	/workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/61.otp_ctrl_init_fail.2938490178
Short name	T617
Test name
Test status
Simulation time	744187659 ps
CPU time	5.29 seconds
Started	Apr 30 03:46:06 PM PDT 24
Finished	Apr 30 03:46:12 PM PDT 24
Peak memory	241276 kb
Host	smart-dcceed25-bc23-429f-8060-d7ac94cf86ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2938490178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.2938490178
Directory	/workspace/61.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.870717367
Short name	T1109
Test name
Test status
Simulation time	542608257 ps
CPU time	16.21 seconds
Started	Apr 30 03:46:05 PM PDT 24
Finished	Apr 30 03:46:22 PM PDT 24
Peak memory	241348 kb
Host	smart-05af9eea-f19b-4fb4-80d0-7332e9f9152e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=870717367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.870717367
Directory	/workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/62.otp_ctrl_init_fail.2442402004
Short name	T140
Test name
Test status
Simulation time	2600937219 ps
CPU time	5.47 seconds
Started	Apr 30 03:46:06 PM PDT 24
Finished	Apr 30 03:46:12 PM PDT 24
Peak memory	241556 kb
Host	smart-1a4bcbe6-73d8-4285-b7a6-788849943921
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442402004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.2442402004
Directory	/workspace/62.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.2798043310
Short name	T611
Test name
Test status
Simulation time	8019471592 ps
CPU time	15.94 seconds
Started	Apr 30 03:46:05 PM PDT 24
Finished	Apr 30 03:46:22 PM PDT 24
Peak memory	241656 kb
Host	smart-e82b4219-9e18-4ee8-a5b2-e3faed74e918
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2798043310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.2798043310
Directory	/workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.121667952
Short name	T671
Test name
Test status
Simulation time	232798096659 ps
CPU time	543.3 seconds
Started	Apr 30 03:46:05 PM PDT 24
Finished	Apr 30 03:55:09 PM PDT 24
Peak memory	346548 kb
Host	smart-cbdf3417-92bd-4e75-afdf-2abba2d3d152
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121667952 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.121667952
Directory	/workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/63.otp_ctrl_init_fail.4079999333
Short name	T1118
Test name
Test status
Simulation time	194225056 ps
CPU time	3.77 seconds
Started	Apr 30 03:46:08 PM PDT 24
Finished	Apr 30 03:46:12 PM PDT 24
Peak memory	241712 kb
Host	smart-93eb68ae-229b-4700-b338-2f2e7a78caba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079999333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.4079999333
Directory	/workspace/63.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.277242127
Short name	T260
Test name
Test status
Simulation time	75252819424 ps
CPU time	850.5 seconds
Started	Apr 30 03:46:13 PM PDT 24
Finished	Apr 30 04:00:24 PM PDT 24
Peak memory	264652 kb
Host	smart-33627f05-c8dd-4f54-8a66-6b2be4d3942b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277242127 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.277242127
Directory	/workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/64.otp_ctrl_init_fail.2233481895
Short name	T1032
Test name
Test status
Simulation time	617853840 ps
CPU time	4.83 seconds
Started	Apr 30 03:46:13 PM PDT 24
Finished	Apr 30 03:46:19 PM PDT 24
Peak memory	241292 kb
Host	smart-aaedbf5b-aeef-4e1c-929c-92c45a81f312
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2233481895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.2233481895
Directory	/workspace/64.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.1282426922
Short name	T266
Test name
Test status
Simulation time	668961545 ps
CPU time	19.18 seconds
Started	Apr 30 03:46:21 PM PDT 24
Finished	Apr 30 03:46:40 PM PDT 24
Peak memory	241376 kb
Host	smart-beb0cd8f-6548-4eca-ae5d-8e17abf423be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1282426922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.1282426922
Directory	/workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/65.otp_ctrl_init_fail.2080138744
Short name	T118
Test name
Test status
Simulation time	2557385846 ps
CPU time	6.06 seconds
Started	Apr 30 03:46:19 PM PDT 24
Finished	Apr 30 03:46:26 PM PDT 24
Peak memory	241600 kb
Host	smart-f88773d8-e96b-428d-8501-eff6ad8a7fe3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2080138744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.2080138744
Directory	/workspace/65.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.416430368
Short name	T970
Test name
Test status
Simulation time	127661345650 ps
CPU time	1680.25 seconds
Started	Apr 30 03:46:15 PM PDT 24
Finished	Apr 30 04:14:16 PM PDT 24
Peak memory	518024 kb
Host	smart-1b6b70f0-bb08-4ebf-a019-39853db28623
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416430368 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.416430368
Directory	/workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/66.otp_ctrl_init_fail.680225621
Short name	T988
Test name
Test status
Simulation time	130452914 ps
CPU time	5.16 seconds
Started	Apr 30 03:46:13 PM PDT 24
Finished	Apr 30 03:46:19 PM PDT 24
Peak memory	241364 kb
Host	smart-a84aee8a-4112-45a4-9cc8-b334e64e7c60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=680225621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.680225621
Directory	/workspace/66.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.295001074
Short name	T926
Test name
Test status
Simulation time	225807313 ps
CPU time	4.23 seconds
Started	Apr 30 03:46:14 PM PDT 24
Finished	Apr 30 03:46:19 PM PDT 24
Peak memory	241644 kb
Host	smart-37f5c767-9353-4ce8-b56b-7a80bad4839e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=295001074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.295001074
Directory	/workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.2482850124
Short name	T527
Test name
Test status
Simulation time	114183444818 ps
CPU time	1596.59 seconds
Started	Apr 30 03:46:18 PM PDT 24
Finished	Apr 30 04:12:55 PM PDT 24
Peak memory	274276 kb
Host	smart-16705f2e-7d9d-4ae5-96ba-f7b94f11f1ca
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482850124 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.2482850124
Directory	/workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/67.otp_ctrl_init_fail.994205672
Short name	T765
Test name
Test status
Simulation time	1548491296 ps
CPU time	5.3 seconds
Started	Apr 30 03:46:13 PM PDT 24
Finished	Apr 30 03:46:19 PM PDT 24
Peak memory	241348 kb
Host	smart-5250ef9d-a31e-44c3-843b-291da859f1a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=994205672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.994205672
Directory	/workspace/67.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.1311339650
Short name	T357
Test name
Test status
Simulation time	219519976 ps
CPU time	3.17 seconds
Started	Apr 30 03:46:14 PM PDT 24
Finished	Apr 30 03:46:18 PM PDT 24
Peak memory	241376 kb
Host	smart-8a9a14a6-85c5-4dcc-ab0c-ca01bc3ade5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1311339650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.1311339650
Directory	/workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.170605740
Short name	T299
Test name
Test status
Simulation time	122953884983 ps
CPU time	1957.48 seconds
Started	Apr 30 03:46:16 PM PDT 24
Finished	Apr 30 04:18:54 PM PDT 24
Peak memory	417552 kb
Host	smart-11d6de2c-76f4-492a-aca3-38ddf2120001
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170605740 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.170605740
Directory	/workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/68.otp_ctrl_init_fail.3902544970
Short name	T751
Test name
Test status
Simulation time	1548044610 ps
CPU time	4.59 seconds
Started	Apr 30 03:46:19 PM PDT 24
Finished	Apr 30 03:46:24 PM PDT 24
Peak memory	241300 kb
Host	smart-47525367-090e-4a32-ac07-f967f6f1d2a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3902544970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.3902544970
Directory	/workspace/68.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.1687102071
Short name	T955
Test name
Test status
Simulation time	1128279055 ps
CPU time	24.68 seconds
Started	Apr 30 03:46:22 PM PDT 24
Finished	Apr 30 03:46:47 PM PDT 24
Peak memory	241372 kb
Host	smart-e9ebca1b-419d-4670-b246-bf3c4d9a4b41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1687102071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.1687102071
Directory	/workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.2853805731
Short name	T302
Test name
Test status
Simulation time	200690810344 ps
CPU time	702.76 seconds
Started	Apr 30 03:46:22 PM PDT 24
Finished	Apr 30 03:58:05 PM PDT 24
Peak memory	264628 kb
Host	smart-7fdc4a0b-4484-49a9-82af-8e07e92ee494
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853805731 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.2853805731
Directory	/workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/69.otp_ctrl_init_fail.2004581581
Short name	T872
Test name
Test status
Simulation time	343058174 ps
CPU time	4.17 seconds
Started	Apr 30 03:46:21 PM PDT 24
Finished	Apr 30 03:46:26 PM PDT 24
Peak memory	241356 kb
Host	smart-70e857a7-f556-4d85-a7eb-72e20e82ee8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2004581581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.2004581581
Directory	/workspace/69.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.3372018084
Short name	T834
Test name
Test status
Simulation time	386930738 ps
CPU time	10.23 seconds
Started	Apr 30 03:46:19 PM PDT 24
Finished	Apr 30 03:46:30 PM PDT 24
Peak memory	241212 kb
Host	smart-020d72fe-25f8-4da6-84ee-6f748bf3d4f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3372018084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.3372018084
Directory	/workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.1161136488
Short name	T1132
Test name
Test status
Simulation time	718223199379 ps
CPU time	2204.22 seconds
Started	Apr 30 03:46:20 PM PDT 24
Finished	Apr 30 04:23:05 PM PDT 24
Peak memory	455980 kb
Host	smart-d5934d4a-fc41-4583-84cf-4749c78f7305
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161136488 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.1161136488
Directory	/workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.otp_ctrl_alert_test.912331728
Short name	T1142
Test name
Test status
Simulation time	69437144 ps
CPU time	1.92 seconds
Started	Apr 30 03:40:59 PM PDT 24
Finished	Apr 30 03:41:01 PM PDT 24
Peak memory	240036 kb
Host	smart-fa8b466b-d3d6-40fa-ba55-e13f39dc77f9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912331728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.912331728
Directory	/workspace/7.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.otp_ctrl_background_chks.632191227
Short name	T814
Test name
Test status
Simulation time	1920017941 ps
CPU time	19.96 seconds
Started	Apr 30 03:40:56 PM PDT 24
Finished	Apr 30 03:41:17 PM PDT 24
Peak memory	247964 kb
Host	smart-47792b9b-1b23-4b3a-b839-6babe39225f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632191227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.632191227
Directory	/workspace/7.otp_ctrl_background_chks/latest

Test location	/workspace/coverage/default/7.otp_ctrl_check_fail.1564289529
Short name	T36
Test name
Test status
Simulation time	4142275974 ps
CPU time	19.25 seconds
Started	Apr 30 03:40:56 PM PDT 24
Finished	Apr 30 03:41:16 PM PDT 24
Peak memory	248152 kb
Host	smart-933d1ab4-9c5d-409e-8f4b-3be9b5a5e2bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1564289529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.1564289529
Directory	/workspace/7.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/7.otp_ctrl_dai_errs.2265520158
Short name	T1058
Test name
Test status
Simulation time	412034410 ps
CPU time	21.76 seconds
Started	Apr 30 03:40:58 PM PDT 24
Finished	Apr 30 03:41:20 PM PDT 24
Peak memory	241436 kb
Host	smart-bcc0298d-816c-42e2-a1bc-e1288c0f5836
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2265520158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.2265520158
Directory	/workspace/7.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/7.otp_ctrl_dai_lock.145965088
Short name	T155
Test name
Test status
Simulation time	2897769175 ps
CPU time	19.8 seconds
Started	Apr 30 03:40:55 PM PDT 24
Finished	Apr 30 03:41:15 PM PDT 24
Peak memory	241428 kb
Host	smart-0cef16f1-8f35-45c6-ab39-26e4ad078e4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=145965088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.145965088
Directory	/workspace/7.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/7.otp_ctrl_init_fail.280953274
Short name	T702
Test name
Test status
Simulation time	266294645 ps
CPU time	4.61 seconds
Started	Apr 30 03:40:55 PM PDT 24
Finished	Apr 30 03:41:00 PM PDT 24
Peak memory	241584 kb
Host	smart-3e34b4ca-d633-4523-a109-d72110ffd379
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=280953274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.280953274
Directory	/workspace/7.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/7.otp_ctrl_macro_errs.2949555480
Short name	T489
Test name
Test status
Simulation time	2543923196 ps
CPU time	30.06 seconds
Started	Apr 30 03:41:01 PM PDT 24
Finished	Apr 30 03:41:32 PM PDT 24
Peak memory	250388 kb
Host	smart-98aa181f-f7f7-4863-8179-b2894a2ba49d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2949555480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.2949555480
Directory	/workspace/7.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/7.otp_ctrl_parallel_key_req.2242192067
Short name	T505
Test name
Test status
Simulation time	2054037917 ps
CPU time	14.25 seconds
Started	Apr 30 03:41:00 PM PDT 24
Finished	Apr 30 03:41:15 PM PDT 24
Peak memory	241460 kb
Host	smart-dadd4cbb-93b9-48b1-90a3-e1be4cdcea9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2242192067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.2242192067
Directory	/workspace/7.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.4017832491
Short name	T284
Test name
Test status
Simulation time	210956257 ps
CPU time	5.41 seconds
Started	Apr 30 03:40:55 PM PDT 24
Finished	Apr 30 03:41:01 PM PDT 24
Peak memory	241716 kb
Host	smart-28e7d616-ad40-4a17-b0e9-ba3d15894eff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017832491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.4017832491
Directory	/workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/7.otp_ctrl_parallel_lc_req.124610975
Short name	T524
Test name
Test status
Simulation time	1315260661 ps
CPU time	21.67 seconds
Started	Apr 30 03:40:54 PM PDT 24
Finished	Apr 30 03:41:16 PM PDT 24
Peak memory	241312 kb
Host	smart-2bd69d5b-4580-4abb-8ab7-7651dcdcda8d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=124610975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.124610975
Directory	/workspace/7.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/7.otp_ctrl_regwen.1091964171
Short name	T797
Test name
Test status
Simulation time	3903889350 ps
CPU time	9.89 seconds
Started	Apr 30 03:40:58 PM PDT 24
Finished	Apr 30 03:41:09 PM PDT 24
Peak memory	241812 kb
Host	smart-330c4979-5bc9-4348-ac30-eca88fdcd695
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1091964171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.1091964171
Directory	/workspace/7.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/7.otp_ctrl_smoke.532524924
Short name	T635
Test name
Test status
Simulation time	248747529 ps
CPU time	8.37 seconds
Started	Apr 30 03:40:55 PM PDT 24
Finished	Apr 30 03:41:05 PM PDT 24
Peak memory	241164 kb
Host	smart-c34a7d9d-8a37-43c5-a38e-d4b9f1089696
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=532524924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.532524924
Directory	/workspace/7.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.otp_ctrl_stress_all.3486166784
Short name	T1112
Test name
Test status
Simulation time	1123043496 ps
CPU time	24.43 seconds
Started	Apr 30 03:40:59 PM PDT 24
Finished	Apr 30 03:41:24 PM PDT 24
Peak memory	241036 kb
Host	smart-cce25bc6-7f27-444a-b1f6-337b25d4acb6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486166784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all. 3486166784
Directory	/workspace/7.otp_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.3623422587
Short name	T821
Test name
Test status
Simulation time	229833345256 ps
CPU time	507.2 seconds
Started	Apr 30 03:41:00 PM PDT 24
Finished	Apr 30 03:49:28 PM PDT 24
Peak memory	256412 kb
Host	smart-298b5518-54d9-4f19-8100-3fd28c6e2028
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623422587 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.3623422587
Directory	/workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.otp_ctrl_test_access.2097614672
Short name	T726
Test name
Test status
Simulation time	621972029 ps
CPU time	4.1 seconds
Started	Apr 30 03:40:58 PM PDT 24
Finished	Apr 30 03:41:03 PM PDT 24
Peak memory	241152 kb
Host	smart-f2fa1c5c-6767-43e9-9e96-2748b2d13ff2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2097614672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2097614672
Directory	/workspace/7.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/70.otp_ctrl_init_fail.2358553471
Short name	T526
Test name
Test status
Simulation time	132644775 ps
CPU time	4.99 seconds
Started	Apr 30 03:46:23 PM PDT 24
Finished	Apr 30 03:46:28 PM PDT 24
Peak memory	241376 kb
Host	smart-6d5e7982-b7c2-4261-8dff-c641f4f2b2f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2358553471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.2358553471
Directory	/workspace/70.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.2883664797
Short name	T1019
Test name
Test status
Simulation time	221121068 ps
CPU time	6.84 seconds
Started	Apr 30 03:46:21 PM PDT 24
Finished	Apr 30 03:46:28 PM PDT 24
Peak memory	241152 kb
Host	smart-a12a045b-eb64-4be8-9947-9df2626edf52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2883664797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.2883664797
Directory	/workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.1287387235
Short name	T192
Test name
Test status
Simulation time	160514428292 ps
CPU time	1075.29 seconds
Started	Apr 30 03:46:21 PM PDT 24
Finished	Apr 30 04:04:17 PM PDT 24
Peak memory	295028 kb
Host	smart-10c9b9ef-4977-409b-b1d5-7501c0926bc5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287387235 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.1287387235
Directory	/workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.939704970
Short name	T745
Test name
Test status
Simulation time	4269769823 ps
CPU time	9.03 seconds
Started	Apr 30 03:46:21 PM PDT 24
Finished	Apr 30 03:46:30 PM PDT 24
Peak memory	241744 kb
Host	smart-664cddba-5ca6-40b8-8715-c02d43285fc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=939704970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.939704970
Directory	/workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2057285488
Short name	T789
Test name
Test status
Simulation time	111343765727 ps
CPU time	2077.19 seconds
Started	Apr 30 03:46:19 PM PDT 24
Finished	Apr 30 04:20:57 PM PDT 24
Peak memory	270808 kb
Host	smart-e4a345c0-6258-4650-ac74-9ec1e177ecfc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057285488 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.2057285488
Directory	/workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/72.otp_ctrl_init_fail.102836558
Short name	T711
Test name
Test status
Simulation time	487467455 ps
CPU time	4.73 seconds
Started	Apr 30 03:46:23 PM PDT 24
Finished	Apr 30 03:46:28 PM PDT 24
Peak memory	241324 kb
Host	smart-02b296af-366f-4938-b4dd-3ade88892f01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102836558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.102836558
Directory	/workspace/72.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.3768235092
Short name	T888
Test name
Test status
Simulation time	130490458 ps
CPU time	6.55 seconds
Started	Apr 30 03:46:23 PM PDT 24
Finished	Apr 30 03:46:30 PM PDT 24
Peak memory	241404 kb
Host	smart-427f7461-ae1c-4688-999d-2b16e40390be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3768235092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.3768235092
Directory	/workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.3352270071
Short name	T1136
Test name
Test status
Simulation time	189342533890 ps
CPU time	1147.87 seconds
Started	Apr 30 03:46:28 PM PDT 24
Finished	Apr 30 04:05:37 PM PDT 24
Peak memory	329152 kb
Host	smart-98dc2b24-39f8-4205-b9c3-46c1a5b719fd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352270071 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.3352270071
Directory	/workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/73.otp_ctrl_init_fail.3681101075
Short name	T90
Test name
Test status
Simulation time	214171930 ps
CPU time	3.58 seconds
Started	Apr 30 03:46:29 PM PDT 24
Finished	Apr 30 03:46:33 PM PDT 24
Peak memory	241744 kb
Host	smart-61213ce8-d373-4209-adb9-d7b1fdf4fc77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681101075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.3681101075
Directory	/workspace/73.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.3928626788
Short name	T245
Test name
Test status
Simulation time	529522339 ps
CPU time	14.28 seconds
Started	Apr 30 03:46:27 PM PDT 24
Finished	Apr 30 03:46:42 PM PDT 24
Peak memory	241684 kb
Host	smart-51abf489-0187-4804-b97f-2ca9f9efb15f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3928626788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.3928626788
Directory	/workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.1318935569
Short name	T931
Test name
Test status
Simulation time	678824245620 ps
CPU time	1835.53 seconds
Started	Apr 30 03:46:28 PM PDT 24
Finished	Apr 30 04:17:04 PM PDT 24
Peak memory	349648 kb
Host	smart-8d32e812-ac0c-408d-b4ab-a23f0ea20abe
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318935569 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.1318935569
Directory	/workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/74.otp_ctrl_init_fail.3408485267
Short name	T672
Test name
Test status
Simulation time	1759668720 ps
CPU time	5.87 seconds
Started	Apr 30 03:46:29 PM PDT 24
Finished	Apr 30 03:46:35 PM PDT 24
Peak memory	241304 kb
Host	smart-fc625713-a6d7-4dc9-848c-3142f7442d7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3408485267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.3408485267
Directory	/workspace/74.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.190993920
Short name	T80
Test name
Test status
Simulation time	234362361 ps
CPU time	12.35 seconds
Started	Apr 30 03:46:28 PM PDT 24
Finished	Apr 30 03:46:41 PM PDT 24
Peak memory	241356 kb
Host	smart-9f442ef4-da77-4cc8-81c7-aecab0927116
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=190993920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.190993920
Directory	/workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.1022210424
Short name	T354
Test name
Test status
Simulation time	68453215160 ps
CPU time	787.67 seconds
Started	Apr 30 03:46:28 PM PDT 24
Finished	Apr 30 03:59:37 PM PDT 24
Peak memory	284304 kb
Host	smart-906d36c4-0dc2-4286-ac77-6bc343d5cd5a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022210424 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.1022210424
Directory	/workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/75.otp_ctrl_init_fail.3608846835
Short name	T777
Test name
Test status
Simulation time	268447123 ps
CPU time	4.56 seconds
Started	Apr 30 03:46:29 PM PDT 24
Finished	Apr 30 03:46:34 PM PDT 24
Peak memory	241412 kb
Host	smart-df6b5fed-4b1b-4a91-85d5-716e36d66672
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3608846835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3608846835
Directory	/workspace/75.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.159147440
Short name	T899
Test name
Test status
Simulation time	7698133896 ps
CPU time	17.36 seconds
Started	Apr 30 03:46:28 PM PDT 24
Finished	Apr 30 03:46:46 PM PDT 24
Peak memory	241348 kb
Host	smart-7eb3566e-4755-446d-9d81-fa6f89515ace
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159147440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.159147440
Directory	/workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.4139366515
Short name	T1169
Test name
Test status
Simulation time	198630701378 ps
CPU time	1358.63 seconds
Started	Apr 30 03:46:28 PM PDT 24
Finished	Apr 30 04:09:08 PM PDT 24
Peak memory	349952 kb
Host	smart-037b8066-1ebc-456a-8415-bd320ea458c6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139366515 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.4139366515
Directory	/workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/76.otp_ctrl_init_fail.160098963
Short name	T876
Test name
Test status
Simulation time	126425020 ps
CPU time	3.78 seconds
Started	Apr 30 03:46:27 PM PDT 24
Finished	Apr 30 03:46:32 PM PDT 24
Peak memory	241632 kb
Host	smart-f9e6a300-82cc-4884-a1d9-3c1cc3221cda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=160098963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.160098963
Directory	/workspace/76.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.3446950032
Short name	T1111
Test name
Test status
Simulation time	332317921 ps
CPU time	10.28 seconds
Started	Apr 30 03:46:29 PM PDT 24
Finished	Apr 30 03:46:40 PM PDT 24
Peak memory	241184 kb
Host	smart-997fb314-cfb9-404a-8e5a-a1722d338dbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446950032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.3446950032
Directory	/workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.3790060948
Short name	T405
Test name
Test status
Simulation time	62740389986 ps
CPU time	415.58 seconds
Started	Apr 30 03:46:29 PM PDT 24
Finished	Apr 30 03:53:25 PM PDT 24
Peak memory	248252 kb
Host	smart-1da25c63-807a-4c42-847d-7cb36437894d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790060948 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.3790060948
Directory	/workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/77.otp_ctrl_init_fail.3688123599
Short name	T162
Test name
Test status
Simulation time	386432619 ps
CPU time	4.41 seconds
Started	Apr 30 03:46:29 PM PDT 24
Finished	Apr 30 03:46:34 PM PDT 24
Peak memory	241684 kb
Host	smart-efe90693-d9a0-4af4-a4ff-854f4c86408d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3688123599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.3688123599
Directory	/workspace/77.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.2907827879
Short name	T754
Test name
Test status
Simulation time	420105231 ps
CPU time	9.52 seconds
Started	Apr 30 03:46:34 PM PDT 24
Finished	Apr 30 03:46:44 PM PDT 24
Peak memory	241352 kb
Host	smart-b8112d72-941c-4586-8501-7fc44cc516ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907827879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.2907827879
Directory	/workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.3627761041
Short name	T366
Test name
Test status
Simulation time	271295114695 ps
CPU time	1815.63 seconds
Started	Apr 30 03:46:34 PM PDT 24
Finished	Apr 30 04:16:50 PM PDT 24
Peak memory	333244 kb
Host	smart-f525fad7-f5a2-41bc-b28c-a1c1af928616
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627761041 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.3627761041
Directory	/workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.3734264464
Short name	T636
Test name
Test status
Simulation time	159716757 ps
CPU time	7.74 seconds
Started	Apr 30 03:46:34 PM PDT 24
Finished	Apr 30 03:46:42 PM PDT 24
Peak memory	241668 kb
Host	smart-a54d7403-d388-4726-bb41-3bdcd56b2230
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3734264464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.3734264464
Directory	/workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/79.otp_ctrl_init_fail.2374418498
Short name	T171
Test name
Test status
Simulation time	457617815 ps
CPU time	3.1 seconds
Started	Apr 30 03:46:39 PM PDT 24
Finished	Apr 30 03:46:43 PM PDT 24
Peak memory	241392 kb
Host	smart-ce687450-d88b-4230-85e2-911bf3bcf886
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374418498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2374418498
Directory	/workspace/79.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/8.otp_ctrl_alert_test.4145192634
Short name	T1085
Test name
Test status
Simulation time	49098141 ps
CPU time	1.5 seconds
Started	Apr 30 03:41:09 PM PDT 24
Finished	Apr 30 03:41:11 PM PDT 24
Peak memory	240148 kb
Host	smart-09adb174-5d50-494b-a42b-51d5b6118108
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145192634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.4145192634
Directory	/workspace/8.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.otp_ctrl_background_chks.1857656007
Short name	T1183
Test name
Test status
Simulation time	23968051200 ps
CPU time	44.23 seconds
Started	Apr 30 03:41:05 PM PDT 24
Finished	Apr 30 03:41:49 PM PDT 24
Peak memory	241744 kb
Host	smart-90f5a366-4332-4284-8110-8b27e09c3508
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1857656007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.1857656007
Directory	/workspace/8.otp_ctrl_background_chks/latest

Test location	/workspace/coverage/default/8.otp_ctrl_check_fail.2683216875
Short name	T858
Test name
Test status
Simulation time	935625377 ps
CPU time	6.83 seconds
Started	Apr 30 03:41:04 PM PDT 24
Finished	Apr 30 03:41:11 PM PDT 24
Peak memory	247924 kb
Host	smart-1adcdea6-ae06-4c40-8c98-bcf6beb4e32e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2683216875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.2683216875
Directory	/workspace/8.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/8.otp_ctrl_dai_errs.1550666933
Short name	T483
Test name
Test status
Simulation time	756333076 ps
CPU time	25.3 seconds
Started	Apr 30 03:41:07 PM PDT 24
Finished	Apr 30 03:41:32 PM PDT 24
Peak memory	241296 kb
Host	smart-bb47dba8-9103-4242-a8fc-2962b3a5829f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550666933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.1550666933
Directory	/workspace/8.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/8.otp_ctrl_dai_lock.2132806548
Short name	T594
Test name
Test status
Simulation time	5471012267 ps
CPU time	42.92 seconds
Started	Apr 30 03:41:06 PM PDT 24
Finished	Apr 30 03:41:49 PM PDT 24
Peak memory	247988 kb
Host	smart-e665af62-6b12-4413-b22c-ef07d0a5d26e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132806548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.2132806548
Directory	/workspace/8.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/8.otp_ctrl_init_fail.1379186701
Short name	T847
Test name
Test status
Simulation time	283074889 ps
CPU time	4.03 seconds
Started	Apr 30 03:41:04 PM PDT 24
Finished	Apr 30 03:41:09 PM PDT 24
Peak memory	241756 kb
Host	smart-b92599bc-7559-40f8-a222-520a08a3a882
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1379186701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.1379186701
Directory	/workspace/8.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/8.otp_ctrl_macro_errs.1704164355
Short name	T1004
Test name
Test status
Simulation time	163424193 ps
CPU time	4.31 seconds
Started	Apr 30 03:41:05 PM PDT 24
Finished	Apr 30 03:41:10 PM PDT 24
Peak memory	241384 kb
Host	smart-109e1c8f-2299-463c-b28b-2628bec8e248
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704164355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.1704164355
Directory	/workspace/8.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/8.otp_ctrl_parallel_key_req.295254419
Short name	T1054
Test name
Test status
Simulation time	480485074 ps
CPU time	14.65 seconds
Started	Apr 30 03:41:04 PM PDT 24
Finished	Apr 30 03:41:19 PM PDT 24
Peak memory	241272 kb
Host	smart-6d8d345a-9da8-4e55-b744-0dd0500d05c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=295254419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.295254419
Directory	/workspace/8.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.2626987117
Short name	T818
Test name
Test status
Simulation time	398533575 ps
CPU time	6.35 seconds
Started	Apr 30 03:41:05 PM PDT 24
Finished	Apr 30 03:41:12 PM PDT 24
Peak memory	241232 kb
Host	smart-6b183ba8-7a17-438b-ab4a-d430e2da9357
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2626987117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.2626987117
Directory	/workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/8.otp_ctrl_parallel_lc_req.1850300601
Short name	T256
Test name
Test status
Simulation time	2087595572 ps
CPU time	23.59 seconds
Started	Apr 30 03:41:06 PM PDT 24
Finished	Apr 30 03:41:30 PM PDT 24
Peak memory	241308 kb
Host	smart-9abdea13-c3a7-4d44-8234-6e250d4f2151
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1850300601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.1850300601
Directory	/workspace/8.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/8.otp_ctrl_regwen.1953681028
Short name	T914
Test name
Test status
Simulation time	523047209 ps
CPU time	5.36 seconds
Started	Apr 30 03:41:06 PM PDT 24
Finished	Apr 30 03:41:11 PM PDT 24
Peak memory	241316 kb
Host	smart-ae4eb191-b0a4-4d6a-8c80-fcb998f1ee2c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1953681028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.1953681028
Directory	/workspace/8.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/8.otp_ctrl_smoke.4034422625
Short name	T1127
Test name
Test status
Simulation time	586996450 ps
CPU time	7.11 seconds
Started	Apr 30 03:40:59 PM PDT 24
Finished	Apr 30 03:41:06 PM PDT 24
Peak memory	247952 kb
Host	smart-0c53d23b-c164-4de6-b6c4-187fd512f71d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4034422625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.4034422625
Directory	/workspace/8.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.4285043295
Short name	T815
Test name
Test status
Simulation time	24814732661 ps
CPU time	629.7 seconds
Started	Apr 30 03:41:08 PM PDT 24
Finished	Apr 30 03:51:39 PM PDT 24
Peak memory	326648 kb
Host	smart-9e2b29f3-f481-4d61-9bce-117ec158489d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285043295 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.4285043295
Directory	/workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.otp_ctrl_test_access.2489885308
Short name	T949
Test name
Test status
Simulation time	7032382470 ps
CPU time	14.2 seconds
Started	Apr 30 03:41:10 PM PDT 24
Finished	Apr 30 03:41:24 PM PDT 24
Peak memory	242336 kb
Host	smart-69edb6bf-74e5-4c0c-84cb-1d305764297c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2489885308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.2489885308
Directory	/workspace/8.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/80.otp_ctrl_init_fail.3863448027
Short name	T318
Test name
Test status
Simulation time	242358355 ps
CPU time	3.92 seconds
Started	Apr 30 03:46:34 PM PDT 24
Finished	Apr 30 03:46:39 PM PDT 24
Peak memory	241860 kb
Host	smart-a9627da3-8e41-41ff-b803-9f23903ca5fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3863448027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.3863448027
Directory	/workspace/80.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.1768641603
Short name	T1014
Test name
Test status
Simulation time	92829475 ps
CPU time	3.5 seconds
Started	Apr 30 03:46:34 PM PDT 24
Finished	Apr 30 03:46:38 PM PDT 24
Peak memory	241228 kb
Host	smart-8e71d8ca-c76e-4a62-8a73-390e31193c96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1768641603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.1768641603
Directory	/workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.1575002729
Short name	T1117
Test name
Test status
Simulation time	1613502567502 ps
CPU time	2903.57 seconds
Started	Apr 30 03:46:35 PM PDT 24
Finished	Apr 30 04:34:59 PM PDT 24
Peak memory	361744 kb
Host	smart-f4fbf0d1-00a5-4337-9d76-5c9534515f5b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575002729 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.1575002729
Directory	/workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.789184883
Short name	T633
Test name
Test status
Simulation time	187668128 ps
CPU time	4.44 seconds
Started	Apr 30 03:46:35 PM PDT 24
Finished	Apr 30 03:46:40 PM PDT 24
Peak memory	241228 kb
Host	smart-d83663e3-1e89-4917-a76c-d93b0265d126
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789184883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.789184883
Directory	/workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1412519138
Short name	T161
Test name
Test status
Simulation time	530823175652 ps
CPU time	1758.55 seconds
Started	Apr 30 03:46:35 PM PDT 24
Finished	Apr 30 04:15:54 PM PDT 24
Peak memory	274084 kb
Host	smart-1a317c97-cac9-4cfc-bfff-cef714f50570
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412519138 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.1412519138
Directory	/workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/82.otp_ctrl_init_fail.899352593
Short name	T1167
Test name
Test status
Simulation time	1719179934 ps
CPU time	4.58 seconds
Started	Apr 30 03:46:34 PM PDT 24
Finished	Apr 30 03:46:40 PM PDT 24
Peak memory	241204 kb
Host	smart-e7f889a7-8fa2-4a61-9d0e-11867d9c1fbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=899352593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.899352593
Directory	/workspace/82.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.2000893159
Short name	T673
Test name
Test status
Simulation time	5994625862 ps
CPU time	9.64 seconds
Started	Apr 30 03:46:33 PM PDT 24
Finished	Apr 30 03:46:43 PM PDT 24
Peak memory	241920 kb
Host	smart-5c83eeda-633c-4ea2-94a2-dba34f364f44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000893159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.2000893159
Directory	/workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.3925040378
Short name	T995
Test name
Test status
Simulation time	992158806452 ps
CPU time	1868.14 seconds
Started	Apr 30 03:46:34 PM PDT 24
Finished	Apr 30 04:17:43 PM PDT 24
Peak memory	316248 kb
Host	smart-c77b23ab-6c96-41ba-ae7a-3b182aeae0dd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925040378 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.3925040378
Directory	/workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/83.otp_ctrl_init_fail.443343673
Short name	T584
Test name
Test status
Simulation time	122131744 ps
CPU time	3.29 seconds
Started	Apr 30 03:46:39 PM PDT 24
Finished	Apr 30 03:46:43 PM PDT 24
Peak memory	241660 kb
Host	smart-994b1481-12b1-41ec-9c0f-8d3b3779208f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443343673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.443343673
Directory	/workspace/83.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.3533067345
Short name	T187
Test name
Test status
Simulation time	547723541 ps
CPU time	8.17 seconds
Started	Apr 30 03:46:34 PM PDT 24
Finished	Apr 30 03:46:42 PM PDT 24
Peak memory	241760 kb
Host	smart-15dd367e-a9ce-40b2-bcf3-57797644bd7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3533067345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3533067345
Directory	/workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/84.otp_ctrl_init_fail.1551189079
Short name	T1037
Test name
Test status
Simulation time	286038228 ps
CPU time	4.38 seconds
Started	Apr 30 03:46:34 PM PDT 24
Finished	Apr 30 03:46:39 PM PDT 24
Peak memory	241500 kb
Host	smart-8290482e-e537-4f8e-8671-5bd7472ae968
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1551189079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.1551189079
Directory	/workspace/84.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.1320165535
Short name	T413
Test name
Test status
Simulation time	193825397 ps
CPU time	4.35 seconds
Started	Apr 30 03:46:42 PM PDT 24
Finished	Apr 30 03:46:47 PM PDT 24
Peak memory	241120 kb
Host	smart-761cb539-3154-4202-a88e-8d0ca0302ec0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320165535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1320165535
Directory	/workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.3279462677
Short name	T16
Test name
Test status
Simulation time	402169303781 ps
CPU time	1749.66 seconds
Started	Apr 30 03:46:40 PM PDT 24
Finished	Apr 30 04:15:50 PM PDT 24
Peak memory	321788 kb
Host	smart-f0ddfedd-c2c1-40ba-9e0d-7ec8c916b720
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279462677 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.3279462677
Directory	/workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/85.otp_ctrl_init_fail.2070749088
Short name	T853
Test name
Test status
Simulation time	142794373 ps
CPU time	3.13 seconds
Started	Apr 30 03:46:43 PM PDT 24
Finished	Apr 30 03:46:47 PM PDT 24
Peak memory	241436 kb
Host	smart-df36e8e3-53e1-4c13-9f8f-705eb2a8ac41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070749088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.2070749088
Directory	/workspace/85.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.4005750402
Short name	T154
Test name
Test status
Simulation time	161159676 ps
CPU time	3.47 seconds
Started	Apr 30 03:46:41 PM PDT 24
Finished	Apr 30 03:46:46 PM PDT 24
Peak memory	241756 kb
Host	smart-d0607e64-ffd4-4071-96d3-0f95204e75b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4005750402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.4005750402
Directory	/workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.3050652244
Short name	T1025
Test name
Test status
Simulation time	235180061227 ps
CPU time	3058.87 seconds
Started	Apr 30 03:46:42 PM PDT 24
Finished	Apr 30 04:37:42 PM PDT 24
Peak memory	269724 kb
Host	smart-b1cee265-0c03-475d-b7b2-d8508b25d574
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050652244 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.3050652244
Directory	/workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/86.otp_ctrl_init_fail.537801580
Short name	T714
Test name
Test status
Simulation time	157073519 ps
CPU time	4.05 seconds
Started	Apr 30 03:46:44 PM PDT 24
Finished	Apr 30 03:46:48 PM PDT 24
Peak memory	241492 kb
Host	smart-6555b447-b3fc-46d1-a13f-e3c359db42b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537801580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.537801580
Directory	/workspace/86.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.227012901
Short name	T910
Test name
Test status
Simulation time	5291397561 ps
CPU time	11.45 seconds
Started	Apr 30 03:46:44 PM PDT 24
Finished	Apr 30 03:46:56 PM PDT 24
Peak memory	241516 kb
Host	smart-da7ee6e1-7e0a-4a25-9149-8c42dcf1056c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=227012901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.227012901
Directory	/workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.555927869
Short name	T296
Test name
Test status
Simulation time	174481124735 ps
CPU time	2872.76 seconds
Started	Apr 30 03:46:43 PM PDT 24
Finished	Apr 30 04:34:37 PM PDT 24
Peak memory	399020 kb
Host	smart-91d3f647-4fb9-4215-ab70-20b388eb4dde
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555927869 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.555927869
Directory	/workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/87.otp_ctrl_init_fail.1495482612
Short name	T564
Test name
Test status
Simulation time	486210954 ps
CPU time	3.95 seconds
Started	Apr 30 03:46:42 PM PDT 24
Finished	Apr 30 03:46:46 PM PDT 24
Peak memory	241392 kb
Host	smart-318d37b1-9e17-47bc-bf31-6edfefc18bdf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1495482612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.1495482612
Directory	/workspace/87.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.918505080
Short name	T212
Test name
Test status
Simulation time	442001588 ps
CPU time	4.94 seconds
Started	Apr 30 03:46:42 PM PDT 24
Finished	Apr 30 03:46:48 PM PDT 24
Peak memory	241612 kb
Host	smart-2f37d68d-3e45-4dbb-906d-bd2ce23c82ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918505080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.918505080
Directory	/workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.3407147502
Short name	T291
Test name
Test status
Simulation time	151068040383 ps
CPU time	1455.78 seconds
Started	Apr 30 03:46:40 PM PDT 24
Finished	Apr 30 04:10:56 PM PDT 24
Peak memory	258264 kb
Host	smart-f7438d40-74d9-4b34-b80b-a1edb76e2fcd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407147502 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.3407147502
Directory	/workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/88.otp_ctrl_init_fail.3714068683
Short name	T467
Test name
Test status
Simulation time	387288984 ps
CPU time	4.1 seconds
Started	Apr 30 03:46:38 PM PDT 24
Finished	Apr 30 03:46:42 PM PDT 24
Peak memory	241752 kb
Host	smart-bdc7f31f-3dea-4373-b960-f71dbf469fb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714068683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.3714068683
Directory	/workspace/88.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.3989845316
Short name	T236
Test name
Test status
Simulation time	1213230655 ps
CPU time	10.38 seconds
Started	Apr 30 03:46:41 PM PDT 24
Finished	Apr 30 03:46:51 PM PDT 24
Peak memory	241312 kb
Host	smart-a98726ac-d407-4a1a-8875-9e4841b84449
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3989845316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.3989845316
Directory	/workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.1535493413
Short name	T511
Test name
Test status
Simulation time	100505230886 ps
CPU time	412.14 seconds
Started	Apr 30 03:46:40 PM PDT 24
Finished	Apr 30 03:53:33 PM PDT 24
Peak memory	248124 kb
Host	smart-9582cf04-180b-466e-a0ad-0ea98564a4e2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535493413 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.1535493413
Directory	/workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/89.otp_ctrl_init_fail.757369138
Short name	T548
Test name
Test status
Simulation time	122828616 ps
CPU time	3.68 seconds
Started	Apr 30 03:46:39 PM PDT 24
Finished	Apr 30 03:46:43 PM PDT 24
Peak memory	241432 kb
Host	smart-c86ab87c-1c25-4162-96da-17f12e7d5e06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=757369138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.757369138
Directory	/workspace/89.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.4153132115
Short name	T688
Test name
Test status
Simulation time	949947876 ps
CPU time	27.02 seconds
Started	Apr 30 03:46:40 PM PDT 24
Finished	Apr 30 03:47:08 PM PDT 24
Peak memory	241308 kb
Host	smart-dff445d9-86de-4e91-ac77-59d4abeb1fc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4153132115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.4153132115
Directory	/workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.1655434736
Short name	T12
Test name
Test status
Simulation time	36017104469 ps
CPU time	619.74 seconds
Started	Apr 30 03:46:43 PM PDT 24
Finished	Apr 30 03:57:04 PM PDT 24
Peak memory	346304 kb
Host	smart-44d5a9e1-2a7c-44cb-936c-0429e6bea630
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655434736 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.1655434736
Directory	/workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.otp_ctrl_alert_test.2448350867
Short name	T423
Test name
Test status
Simulation time	153149158 ps
CPU time	1.6 seconds
Started	Apr 30 03:41:20 PM PDT 24
Finished	Apr 30 03:41:22 PM PDT 24
Peak memory	239820 kb
Host	smart-80d641c9-daa6-4b05-8653-596fd824dd9b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448350867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.2448350867
Directory	/workspace/9.otp_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.otp_ctrl_background_chks.1877805169
Short name	T340
Test name
Test status
Simulation time	5828851424 ps
CPU time	21.53 seconds
Started	Apr 30 03:41:11 PM PDT 24
Finished	Apr 30 03:41:33 PM PDT 24
Peak memory	248184 kb
Host	smart-b4b9fe58-f525-4388-8906-1b3990f7431e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1877805169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1877805169
Directory	/workspace/9.otp_ctrl_background_chks/latest

Test location	/workspace/coverage/default/9.otp_ctrl_check_fail.2240798592
Short name	T67
Test name
Test status
Simulation time	334552443 ps
CPU time	8.33 seconds
Started	Apr 30 03:41:15 PM PDT 24
Finished	Apr 30 03:41:24 PM PDT 24
Peak memory	241452 kb
Host	smart-2d2bac67-bfee-4bda-acea-465f74e7fad3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2240798592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2240798592
Directory	/workspace/9.otp_ctrl_check_fail/latest

Test location	/workspace/coverage/default/9.otp_ctrl_dai_errs.2139437326
Short name	T628
Test name
Test status
Simulation time	6543932915 ps
CPU time	29.13 seconds
Started	Apr 30 03:41:17 PM PDT 24
Finished	Apr 30 03:41:47 PM PDT 24
Peak memory	241880 kb
Host	smart-d15af3ed-aafc-4988-9223-84ed2ddb0357
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139437326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.2139437326
Directory	/workspace/9.otp_ctrl_dai_errs/latest

Test location	/workspace/coverage/default/9.otp_ctrl_dai_lock.1008444341
Short name	T418
Test name
Test status
Simulation time	8954945093 ps
CPU time	27.92 seconds
Started	Apr 30 03:41:15 PM PDT 24
Finished	Apr 30 03:41:44 PM PDT 24
Peak memory	241368 kb
Host	smart-5e40781d-24e2-4954-a7ab-4e7d5d5d4af4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008444341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.1008444341
Directory	/workspace/9.otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/9.otp_ctrl_init_fail.217881694
Short name	T1184
Test name
Test status
Simulation time	157207979 ps
CPU time	3.96 seconds
Started	Apr 30 03:41:10 PM PDT 24
Finished	Apr 30 03:41:15 PM PDT 24
Peak memory	241500 kb
Host	smart-609f59d2-fc26-4e02-ba87-ff62396b6eff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=217881694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.217881694
Directory	/workspace/9.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/9.otp_ctrl_macro_errs.4289250228
Short name	T1174
Test name
Test status
Simulation time	1447904764 ps
CPU time	21.62 seconds
Started	Apr 30 03:41:17 PM PDT 24
Finished	Apr 30 03:41:39 PM PDT 24
Peak memory	248012 kb
Host	smart-fafafca0-7dc6-42bf-adf7-0952db188b5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4289250228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.4289250228
Directory	/workspace/9.otp_ctrl_macro_errs/latest

Test location	/workspace/coverage/default/9.otp_ctrl_parallel_key_req.2973494746
Short name	T916
Test name
Test status
Simulation time	511974562 ps
CPU time	20.55 seconds
Started	Apr 30 03:41:15 PM PDT 24
Finished	Apr 30 03:41:36 PM PDT 24
Peak memory	247920 kb
Host	smart-2cb392ee-40ef-46fa-9637-f9af9d6465ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2973494746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.2973494746
Directory	/workspace/9.otp_ctrl_parallel_key_req/latest

Test location	/workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.3763793877
Short name	T286
Test name
Test status
Simulation time	1116510191 ps
CPU time	26.8 seconds
Started	Apr 30 03:41:15 PM PDT 24
Finished	Apr 30 03:41:42 PM PDT 24
Peak memory	241328 kb
Host	smart-4c3eccaa-4798-49fb-9950-8cd136a670fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3763793877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.3763793877
Directory	/workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/9.otp_ctrl_parallel_lc_req.3708621906
Short name	T781
Test name
Test status
Simulation time	1390580317 ps
CPU time	15 seconds
Started	Apr 30 03:41:10 PM PDT 24
Finished	Apr 30 03:41:26 PM PDT 24
Peak memory	241332 kb
Host	smart-63e82d4d-5bde-4024-811f-7bd2f4257a8c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3708621906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3708621906
Directory	/workspace/9.otp_ctrl_parallel_lc_req/latest

Test location	/workspace/coverage/default/9.otp_ctrl_regwen.1067151715
Short name	T393
Test name
Test status
Simulation time	307956888 ps
CPU time	2.88 seconds
Started	Apr 30 03:41:14 PM PDT 24
Finished	Apr 30 03:41:18 PM PDT 24
Peak memory	241276 kb
Host	smart-9f83350c-66d5-4182-bdac-9b22e32a872b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1067151715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.1067151715
Directory	/workspace/9.otp_ctrl_regwen/latest

Test location	/workspace/coverage/default/9.otp_ctrl_smoke.3146891171
Short name	T112
Test name
Test status
Simulation time	214542261 ps
CPU time	4.51 seconds
Started	Apr 30 03:41:10 PM PDT 24
Finished	Apr 30 03:41:15 PM PDT 24
Peak memory	241200 kb
Host	smart-f91d69c9-9b70-4048-ac22-025c09fb2f01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3146891171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.3146891171
Directory	/workspace/9.otp_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.otp_ctrl_test_access.3968705141
Short name	T1148
Test name
Test status
Simulation time	4948595770 ps
CPU time	16.22 seconds
Started	Apr 30 03:41:26 PM PDT 24
Finished	Apr 30 03:41:42 PM PDT 24
Peak memory	241320 kb
Host	smart-e8ae54f0-e4ba-45cb-acd9-791147bfc0dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968705141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.3968705141
Directory	/workspace/9.otp_ctrl_test_access/latest

Test location	/workspace/coverage/default/90.otp_ctrl_init_fail.3302251662
Short name	T608
Test name
Test status
Simulation time	1762557724 ps
CPU time	5.95 seconds
Started	Apr 30 03:46:40 PM PDT 24
Finished	Apr 30 03:46:46 PM PDT 24
Peak memory	241436 kb
Host	smart-6a3d3009-2a0a-4972-be57-688f3de87934
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3302251662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.3302251662
Directory	/workspace/90.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.4154613250
Short name	T193
Test name
Test status
Simulation time	711518896 ps
CPU time	18.81 seconds
Started	Apr 30 03:46:41 PM PDT 24
Finished	Apr 30 03:47:01 PM PDT 24
Peak memory	241264 kb
Host	smart-524af76e-7c97-45db-abcf-28abea15ffd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4154613250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.4154613250
Directory	/workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.3292417166
Short name	T890
Test name
Test status
Simulation time	23807134595 ps
CPU time	566.16 seconds
Started	Apr 30 03:46:41 PM PDT 24
Finished	Apr 30 03:56:08 PM PDT 24
Peak memory	287460 kb
Host	smart-0a426c64-0b67-40d0-a730-a7b72b5b00f8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292417166 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.3292417166
Directory	/workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/91.otp_ctrl_init_fail.691581861
Short name	T475
Test name
Test status
Simulation time	117061287 ps
CPU time	4.14 seconds
Started	Apr 30 03:46:44 PM PDT 24
Finished	Apr 30 03:46:48 PM PDT 24
Peak memory	241324 kb
Host	smart-413502ac-0e59-4983-825c-6ce55d41af35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=691581861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.691581861
Directory	/workspace/91.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.3847103342
Short name	T886
Test name
Test status
Simulation time	1011975292 ps
CPU time	6.93 seconds
Started	Apr 30 03:46:40 PM PDT 24
Finished	Apr 30 03:46:47 PM PDT 24
Peak memory	241828 kb
Host	smart-9e4929c9-99d9-4139-8534-57210733dabe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3847103342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.3847103342
Directory	/workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.75145056
Short name	T1154
Test name
Test status
Simulation time	410069383978 ps
CPU time	2145.89 seconds
Started	Apr 30 03:46:44 PM PDT 24
Finished	Apr 30 04:22:31 PM PDT 24
Peak memory	543132 kb
Host	smart-539251ee-083e-4784-8f3b-33eca15191c4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75145056 -assert nopos tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.75145056
Directory	/workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.1527731579
Short name	T861
Test name
Test status
Simulation time	420541249 ps
CPU time	6.4 seconds
Started	Apr 30 03:46:48 PM PDT 24
Finished	Apr 30 03:46:55 PM PDT 24
Peak memory	241404 kb
Host	smart-13c7a85d-548b-4f05-8cfb-e081c9aa41d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1527731579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.1527731579
Directory	/workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/93.otp_ctrl_init_fail.1329186915
Short name	T882
Test name
Test status
Simulation time	1939144129 ps
CPU time	4.71 seconds
Started	Apr 30 03:46:47 PM PDT 24
Finished	Apr 30 03:46:52 PM PDT 24
Peak memory	241704 kb
Host	smart-cfa548fb-11a4-4b42-95f3-2a1b20a80ff4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1329186915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.1329186915
Directory	/workspace/93.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.2963398191
Short name	T433
Test name
Test status
Simulation time	2998732172 ps
CPU time	24.37 seconds
Started	Apr 30 03:46:49 PM PDT 24
Finished	Apr 30 03:47:15 PM PDT 24
Peak memory	241452 kb
Host	smart-88876e6f-9b9a-4a39-94cc-19545c48575e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963398191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2963398191
Directory	/workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1341712331
Short name	T887
Test name
Test status
Simulation time	42132878996 ps
CPU time	303.15 seconds
Started	Apr 30 03:46:47 PM PDT 24
Finished	Apr 30 03:51:51 PM PDT 24
Peak memory	283524 kb
Host	smart-3e40b220-0a22-4355-9f63-cba4fc9cef9a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341712331 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.1341712331
Directory	/workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/94.otp_ctrl_init_fail.2078319181
Short name	T1134
Test name
Test status
Simulation time	324457875 ps
CPU time	3.33 seconds
Started	Apr 30 03:46:46 PM PDT 24
Finished	Apr 30 03:46:50 PM PDT 24
Peak memory	241316 kb
Host	smart-c7beb245-1ebb-467c-9953-3d0212809c39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078319181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.2078319181
Directory	/workspace/94.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.3281034648
Short name	T583
Test name
Test status
Simulation time	652518373 ps
CPU time	10.49 seconds
Started	Apr 30 03:46:46 PM PDT 24
Finished	Apr 30 03:46:57 PM PDT 24
Peak memory	241288 kb
Host	smart-2a3ddb64-69d3-4423-b895-4b2fa7f380c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281034648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.3281034648
Directory	/workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.157685318
Short name	T837
Test name
Test status
Simulation time	63943200855 ps
CPU time	534.36 seconds
Started	Apr 30 03:46:47 PM PDT 24
Finished	Apr 30 03:55:42 PM PDT 24
Peak memory	257844 kb
Host	smart-9bcdb4e8-7b22-4d31-8926-da94731df057
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157685318 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.157685318
Directory	/workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/95.otp_ctrl_init_fail.4234100312
Short name	T478
Test name
Test status
Simulation time	220316825 ps
CPU time	3.41 seconds
Started	Apr 30 03:46:48 PM PDT 24
Finished	Apr 30 03:46:52 PM PDT 24
Peak memory	241336 kb
Host	smart-f2008420-c2ec-4287-8dc1-ddd9152d083f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4234100312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.4234100312
Directory	/workspace/95.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.177263544
Short name	T1003
Test name
Test status
Simulation time	652424699 ps
CPU time	8.85 seconds
Started	Apr 30 03:46:53 PM PDT 24
Finished	Apr 30 03:47:03 PM PDT 24
Peak memory	241828 kb
Host	smart-c6047131-8c8c-4626-98da-cfff767f17d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177263544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.177263544
Directory	/workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.948787119
Short name	T675
Test name
Test status
Simulation time	412274401958 ps
CPU time	863.79 seconds
Started	Apr 30 03:46:50 PM PDT 24
Finished	Apr 30 04:01:15 PM PDT 24
Peak memory	279916 kb
Host	smart-9f841b5d-01b2-47fc-9ad1-982c020154a7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948787119 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.948787119
Directory	/workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/96.otp_ctrl_init_fail.2279542640
Short name	T784
Test name
Test status
Simulation time	523693582 ps
CPU time	3.4 seconds
Started	Apr 30 03:46:49 PM PDT 24
Finished	Apr 30 03:46:53 PM PDT 24
Peak memory	241672 kb
Host	smart-64524e7f-b909-4ec3-8d07-f0c67617ef77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279542640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2279542640
Directory	/workspace/96.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.345921625
Short name	T638
Test name
Test status
Simulation time	174132209 ps
CPU time	7.01 seconds
Started	Apr 30 03:46:48 PM PDT 24
Finished	Apr 30 03:46:55 PM PDT 24
Peak memory	241420 kb
Host	smart-bb220ac4-ed48-4a0d-8ab3-81ad4fb9c07f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345921625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.345921625
Directory	/workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.2917606917
Short name	T300
Test name
Test status
Simulation time	245026511571 ps
CPU time	1523.14 seconds
Started	Apr 30 03:46:52 PM PDT 24
Finished	Apr 30 04:12:16 PM PDT 24
Peak memory	264080 kb
Host	smart-49968924-28c5-42c1-bf9e-9acbcc2f1a6d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917606917 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.2917606917
Directory	/workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/97.otp_ctrl_init_fail.3425588614
Short name	T768
Test name
Test status
Simulation time	300727990 ps
CPU time	4.33 seconds
Started	Apr 30 03:46:54 PM PDT 24
Finished	Apr 30 03:46:59 PM PDT 24
Peak memory	241668 kb
Host	smart-1588f6e0-e733-4fa7-82d9-029214b989a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3425588614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.3425588614
Directory	/workspace/97.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.1049605793
Short name	T956
Test name
Test status
Simulation time	2071456475 ps
CPU time	26.21 seconds
Started	Apr 30 03:46:52 PM PDT 24
Finished	Apr 30 03:47:19 PM PDT 24
Peak memory	241428 kb
Host	smart-e3f7e64f-c624-4a57-b26e-3904ead6acf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1049605793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.1049605793
Directory	/workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.3956189148
Short name	T292
Test name
Test status
Simulation time	244277983195 ps
CPU time	898.09 seconds
Started	Apr 30 03:46:54 PM PDT 24
Finished	Apr 30 04:01:53 PM PDT 24
Peak memory	272788 kb
Host	smart-14f86e58-0baa-441d-87ec-baf753e9b79a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956189148 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.3956189148
Directory	/workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/98.otp_ctrl_init_fail.1920230527
Short name	T924
Test name
Test status
Simulation time	132344221 ps
CPU time	4.28 seconds
Started	Apr 30 03:46:54 PM PDT 24
Finished	Apr 30 03:46:59 PM PDT 24
Peak memory	241688 kb
Host	smart-c0c9abef-174e-44ae-a618-e0ee0679bae9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1920230527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.1920230527
Directory	/workspace/98.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.2091105176
Short name	T519
Test name
Test status
Simulation time	1628759530 ps
CPU time	5.5 seconds
Started	Apr 30 03:46:54 PM PDT 24
Finished	Apr 30 03:47:01 PM PDT 24
Peak memory	241368 kb
Host	smart-0e30c997-902f-497a-9747-585f36e791d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2091105176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.2091105176
Directory	/workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location	/workspace/coverage/default/99.otp_ctrl_init_fail.3548304017
Short name	T945
Test name
Test status
Simulation time	576378538 ps
CPU time	5.05 seconds
Started	Apr 30 03:46:54 PM PDT 24
Finished	Apr 30 03:47:00 PM PDT 24
Peak memory	241340 kb
Host	smart-9080596d-26de-4f40-9489-9c3e832e621a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3548304017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.3548304017
Directory	/workspace/99.otp_ctrl_init_fail/latest

Test location	/workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.1063239734
Short name	T915
Test name
Test status
Simulation time	156520076 ps
CPU time	8.26 seconds
Started	Apr 30 03:46:55 PM PDT 24
Finished	Apr 30 03:47:04 PM PDT 24
Peak memory	241396 kb
Host	smart-1971ae64-e870-47d1-bc9c-248a60fe411d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063239734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.1063239734
Directory	/workspace/99.otp_ctrl_parallel_lc_esc/latest