Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24394267

1

T1

4690

T2

524

T3

6899

full_word

8061319

1

T1

924

T2

206

T3

1507

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32455246	1			T1	5614		T2	730		T3	8406
auto[TlIntgErrCmd]	114	1			T257	4		T258	1		T259	9
auto[TlIntgErrData]	134	1			T257	2		T258	6		T259	3
auto[TlIntgErrBoth]	92	1			T257	4		T258	3		T259	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9513922

1

T1

5020

T2

664

T3

7919

auto[1]

22941664

1

T1

594

T2

66

T3

487

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5988711	1			T1	4359		T2	483		T3	6609
auto[TlIntgErrNone]	partial	auto[1]	18405262	1			T1	331		T2	41		T3	290
auto[TlIntgErrNone]	full_word	auto[0]	3525055	1			T1	661		T2	181		T3	1310
auto[TlIntgErrNone]	full_word	auto[1]	4536218	1			T1	263		T2	25		T3	197
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T257	1		T259	2		T266	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T257	2		T258	1		T259	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T259	2		T349	1		T347	3
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T257	1		T259	1		T348	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T258	3		T259	2		T266	5
auto[TlIntgErrData]	partial	auto[1]	62	1			T257	2		T258	1		T259	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T258	1		T345	1		T348	2
auto[TlIntgErrData]	full_word	auto[1]	12	1			T258	1		T266	1		T350	3
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T258	2		T259	3		T266	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T257	4		T258	1		T259	5
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T345	3		T346	1		T351	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T352	1		T353	1		T354	1