Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24855630

1

T1

997

T2

3032

T3

261667

full_word

8111378

1

T1

267

T2

1274

T3

75217

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32966748	1			T1	1264		T2	4306		T3	336884
auto[TlIntgErrCmd]	82	1			T249	6		T250	3		T251	3
auto[TlIntgErrData]	83	1			T249	9		T250	6		T251	2
auto[TlIntgErrBoth]	95	1			T249	5		T250	1		T251	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9860181

1

T1

967

T2

3982

T3

53976

auto[1]

23106827

1

T1

297

T2

324

T3

282908

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6305468	1			T1	824		T2	2848		T3	32777
auto[TlIntgErrNone]	partial	auto[1]	18549917	1			T1	173		T2	184		T3	228890
auto[TlIntgErrNone]	full_word	auto[0]	3554591	1			T1	143		T2	1134		T3	21199
auto[TlIntgErrNone]	full_word	auto[1]	4556772	1			T1	124		T2	140		T3	54018
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T249	3		T250	2		T251	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T249	3		T250	1		T251	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T251	1		T253	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T355	1		T353	1		-	-
auto[TlIntgErrData]	partial	auto[0]	37	1			T249	4		T250	3		T251	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T249	3		T250	3		T251	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T249	1		T356	1		T253	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T249	1		T352	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T249	2		T251	4		T255	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T249	3		T250	1		T251	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T357	1		T351	1		T257	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T351	2		T355	1		-	-