Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.58	96.10	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	470691378	7844653	0	0
check_regwen_rd_A	470691378	3605	0	0
check_timeout_rd_A	470691378	2625	0	0
check_trigger_regwen_rd_A	470691378	3462	0	0
consistency_check_period_rd_A	470691378	3779	0	0
creator_sw_cfg_read_lock_rd_A	470691378	2819	0	0
direct_access_address_rd_A	470691378	2366	0	0
direct_access_wdata_0_rd_A	470691378	1478	0	0
direct_access_wdata_1_rd_A	470691378	1820	0	0
integrity_check_period_rd_A	470691378	3429	0	0
intr_enable_rd_A	470691378	4544	0	0
owner_sw_cfg_read_lock_rd_A	470691378	2385	0	0
rot_creator_auth_codesign_read_lock_rd_A	470691378	2663	0	0
rot_creator_auth_state_read_lock_rd_A	470691378	2560	0	0
vendor_test_read_lock_rd_A	470691378	2481	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	7844653	0	0
T3	484294	99203	0	0
T5	10189	0	0	0
T6	99520	0	0	0
T7	78249	0	0	0
T8	77372	0	0	0
T9	0	383114	0	0
T10	4528	0	0	0
T11	16448	0	0	0
T12	22226	0	0	0
T13	0	68955	0	0
T15	0	31866	0	0
T19	86488	0	0	0
T68	26251	0	0	0
T106	0	36943	0	0
T128	0	31539	0	0
T130	0	59774	0	0
T198	0	39300	0	0
T259	0	117533	0	0
T260	0	73822	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	3605	0	0
T13	390910	98	0	0
T14	444609	0	0	0
T15	0	18	0	0
T90	57546	0	0	0
T106	0	48	0	0
T112	28611	0	0	0
T130	0	75	0	0
T136	54612	0	0	0
T139	111370	0	0	0
T142	12358	0	0	0
T181	56707	0	0	0
T199	0	116	0	0
T222	6694	0	0	0
T235	13573	0	0	0
T237	0	113	0	0
T259	0	106	0	0
T260	0	83	0	0
T334	0	85	0	0
T335	0	33	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	2625	0	0
T13	390910	71	0	0
T14	444609	0	0	0
T15	0	28	0	0
T90	57546	0	0	0
T106	0	55	0	0
T112	28611	0	0	0
T130	0	117	0	0
T136	54612	0	0	0
T139	111370	0	0	0
T142	12358	0	0	0
T181	56707	0	0	0
T199	0	122	0	0
T222	6694	0	0	0
T235	13573	0	0	0
T237	0	122	0	0
T259	0	80	0	0
T260	0	78	0	0
T334	0	45	0	0
T335	0	32	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	3462	0	0
T13	390910	113	0	0
T14	444609	0	0	0
T15	0	35	0	0
T90	57546	0	0	0
T106	0	70	0	0
T112	28611	0	0	0
T130	0	84	0	0
T136	54612	0	0	0
T139	111370	0	0	0
T142	12358	0	0	0
T181	56707	0	0	0
T199	0	117	0	0
T222	6694	0	0	0
T235	13573	0	0	0
T237	0	138	0	0
T259	0	79	0	0
T260	0	98	0	0
T334	0	50	0	0
T335	0	49	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	3779	0	0
T13	390910	106	0	0
T14	444609	0	0	0
T15	0	29	0	0
T90	57546	0	0	0
T106	0	88	0	0
T112	28611	0	0	0
T130	0	137	0	0
T136	54612	0	0	0
T139	111370	0	0	0
T142	12358	0	0	0
T181	56707	0	0	0
T199	0	105	0	0
T222	6694	0	0	0
T235	13573	0	0	0
T237	0	131	0	0
T259	0	65	0	0
T260	0	50	0	0
T334	0	29	0	0
T335	0	70	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	2819	0	0
T13	390910	84	0	0
T14	444609	0	0	0
T15	0	55	0	0
T90	57546	0	0	0
T106	0	59	0	0
T112	28611	0	0	0
T130	0	94	0	0
T136	54612	0	0	0
T139	111370	0	0	0
T142	12358	0	0	0
T181	56707	0	0	0
T199	0	130	0	0
T222	6694	0	0	0
T235	13573	0	0	0
T237	0	84	0	0
T259	0	87	0	0
T260	0	95	0	0
T334	0	37	0	0
T335	0	42	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	2366	0	0
T13	390910	116	0	0
T14	444609	0	0	0
T15	0	65	0	0
T90	57546	0	0	0
T106	0	101	0	0
T112	28611	0	0	0
T130	0	71	0	0
T136	54612	0	0	0
T139	111370	0	0	0
T142	12358	0	0	0
T181	56707	0	0	0
T199	0	131	0	0
T222	6694	0	0	0
T235	13573	0	0	0
T237	0	88	0	0
T259	0	86	0	0
T260	0	81	0	0
T334	0	47	0	0
T335	0	32	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	1478	0	0
T13	390910	53	0	0
T14	444609	0	0	0
T15	0	31	0	0
T90	57546	0	0	0
T106	0	24	0	0
T112	28611	0	0	0
T130	0	69	0	0
T136	54612	0	0	0
T139	111370	0	0	0
T142	12358	0	0	0
T181	56707	0	0	0
T199	0	79	0	0
T222	6694	0	0	0
T235	13573	0	0	0
T237	0	81	0	0
T259	0	53	0	0
T260	0	67	0	0
T334	0	33	0	0
T335	0	24	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	1820	0	0
T13	390910	98	0	0
T14	444609	0	0	0
T15	0	19	0	0
T90	57546	0	0	0
T106	0	29	0	0
T112	28611	0	0	0
T130	0	74	0	0
T136	54612	0	0	0
T139	111370	0	0	0
T142	12358	0	0	0
T181	56707	0	0	0
T199	0	70	0	0
T222	6694	0	0	0
T235	13573	0	0	0
T237	0	95	0	0
T259	0	84	0	0
T260	0	96	0	0
T334	0	45	0	0
T335	0	39	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	3429	0	0
T13	390910	95	0	0
T14	444609	0	0	0
T15	0	32	0	0
T90	57546	0	0	0
T106	0	64	0	0
T112	28611	0	0	0
T130	0	114	0	0
T136	54612	0	0	0
T139	111370	0	0	0
T142	12358	0	0	0
T181	56707	0	0	0
T199	0	104	0	0
T222	6694	0	0	0
T235	13573	0	0	0
T237	0	138	0	0
T259	0	68	0	0
T260	0	71	0	0
T334	0	48	0	0
T335	0	68	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	4544	0	0
T13	390910	115	0	0
T14	444609	0	0	0
T15	0	30	0	0
T90	57546	0	0	0
T106	0	90	0	0
T112	28611	0	0	0
T130	0	117	0	0
T136	54612	0	0	0
T139	111370	0	0	0
T142	12358	0	0	0
T178	0	25	0	0
T181	56707	0	0	0
T199	0	142	0	0
T217	0	5	0	0
T222	6694	0	0	0
T235	13573	0	0	0
T259	0	81	0	0
T260	0	120	0	0
T336	0	20	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	2385	0	0
T13	390910	71	0	0
T14	444609	0	0	0
T15	0	48	0	0
T90	57546	0	0	0
T106	0	40	0	0
T112	28611	0	0	0
T130	0	87	0	0
T136	54612	0	0	0
T139	111370	0	0	0
T142	12358	0	0	0
T181	56707	0	0	0
T199	0	119	0	0
T222	6694	0	0	0
T235	13573	0	0	0
T237	0	84	0	0
T259	0	49	0	0
T260	0	81	0	0
T334	0	50	0	0
T335	0	56	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	2663	0	0
T13	390910	109	0	0
T14	444609	0	0	0
T15	0	52	0	0
T90	57546	0	0	0
T106	0	108	0	0
T112	28611	0	0	0
T130	0	74	0	0
T136	54612	0	0	0
T139	111370	0	0	0
T142	12358	0	0	0
T181	56707	0	0	0
T199	0	129	0	0
T222	6694	0	0	0
T235	13573	0	0	0
T237	0	116	0	0
T259	0	84	0	0
T260	0	98	0	0
T334	0	38	0	0
T335	0	54	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	2560	0	0
T13	390910	78	0	0
T14	444609	0	0	0
T15	0	32	0	0
T90	57546	0	0	0
T106	0	109	0	0
T112	28611	0	0	0
T130	0	110	0	0
T136	54612	0	0	0
T139	111370	0	0	0
T142	12358	0	0	0
T181	56707	0	0	0
T199	0	101	0	0
T222	6694	0	0	0
T235	13573	0	0	0
T237	0	90	0	0
T259	0	84	0	0
T260	0	102	0	0
T334	0	29	0	0
T335	0	77	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470691378	2481	0	0
T13	390910	64	0	0
T14	444609	0	0	0
T15	0	44	0	0
T90	57546	0	0	0
T106	0	50	0	0
T112	28611	0	0	0
T130	0	68	0	0
T136	54612	0	0	0
T139	111370	0	0	0
T142	12358	0	0	0
T181	56707	0	0	0
T199	0	111	0	0
T222	6694	0	0	0
T235	13573	0	0	0
T237	0	91	0	0
T259	0	75	0	0
T260	0	55	0	0
T334	0	27	0	0
T335	0	57	0	0