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Module Instance : tb.dut.u_edn_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.35 92.31 87.76 100.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.35 92.31 87.76 100.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.58 96.10 96.15 97.04 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instances:
tb.dut.u_edn_arb
Line Coverage for Instance : tb.dut.u_edn_arb
Line No.TotalCoveredPercent
TOTAL262492.31
CONT_ASSIGN6211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
112 2 2
118 2 2
122 0 2
126 2 2
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
174 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_edn_arb
TotalCoveredPercent
Conditions494387.76
Logical494387.76
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01Excluded vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T6,T7
10Not Covered
11CoveredT4

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTestsExclude Annotation
011Excluded vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
101Not Covered
110CoveredT5,T6,T7
111CoveredT5,T6,T7

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT4
111CoveredT4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT5,T6,T7
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT4
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT4
01CoveredT4
10CoveredT5,T6,T7

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT4
11CoveredT4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT5,T6,T7
01Not Covered
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT4

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4
10CoveredT5,T6,T7

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T7
10CoveredT4

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT5,T6,T7

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT5,T6,T7
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T7
10Unreachable

Branch Coverage for Instance : tb.dut.u_edn_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T6,T7


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T6,T7


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 468048268 467164347 0 0
CheckNGreaterZero_A 1149 1149 0 0
GntImpliesReady_A 468048268 281651 0 0
GntImpliesValid_A 468048268 281651 0 0
GrantKnown_A 468048268 467164347 0 0
IdxKnown_A 468048268 467164347 0 0
IndexIsCorrect_A 468048268 281651 0 0
LockArbDecision_A 468048268 22765745 0 0
NoReadyValidNoGrant_A 468048268 444099141 0 0
ReadyAndValidImplyGrant_A 468048268 281651 0 0
ReqAndReadyImplyGrant_A 468048268 281651 0 0
ReqImpliesValid_A 468048268 23065206 0 0
ReqStaysHighUntilGranted0_M 468048268 22765745 0 0
RoundRobin_A 468048268 0 0 1149
ValidKnown_A 468048268 467164347 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468048268 467164347 0 0
T1 10618 10374 0 0
T2 22997 22412 0 0
T3 484294 484281 0 0
T5 10189 9967 0 0
T6 99520 98704 0 0
T7 78249 76783 0 0
T8 77372 77163 0 0
T10 4528 4451 0 0
T11 16448 16247 0 0
T12 22226 21935 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1149 1149 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468048268 281651 0 0
T5 10189 49 0 0
T6 99520 430 0 0
T7 78249 360 0 0
T9 136888 851 0 0
T19 86488 211 0 0
T20 0 2439 0 0
T38 19098 91 0 0
T41 29036 94 0 0
T64 15569 0 0 0
T68 26251 0 0 0
T93 24473 0 0 0
T99 0 97 0 0
T100 0 217 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468048268 281651 0 0
T5 10189 49 0 0
T6 99520 430 0 0
T7 78249 360 0 0
T9 136888 851 0 0
T19 86488 211 0 0
T20 0 2439 0 0
T38 19098 91 0 0
T41 29036 94 0 0
T64 15569 0 0 0
T68 26251 0 0 0
T93 24473 0 0 0
T99 0 97 0 0
T100 0 217 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468048268 467164347 0 0
T1 10618 10374 0 0
T2 22997 22412 0 0
T3 484294 484281 0 0
T5 10189 9967 0 0
T6 99520 98704 0 0
T7 78249 76783 0 0
T8 77372 77163 0 0
T10 4528 4451 0 0
T11 16448 16247 0 0
T12 22226 21935 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468048268 467164347 0 0
T1 10618 10374 0 0
T2 22997 22412 0 0
T3 484294 484281 0 0
T5 10189 9967 0 0
T6 99520 98704 0 0
T7 78249 76783 0 0
T8 77372 77163 0 0
T10 4528 4451 0 0
T11 16448 16247 0 0
T12 22226 21935 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468048268 281651 0 0
T5 10189 49 0 0
T6 99520 430 0 0
T7 78249 360 0 0
T9 136888 851 0 0
T19 86488 211 0 0
T20 0 2439 0 0
T38 19098 91 0 0
T41 29036 94 0 0
T64 15569 0 0 0
T68 26251 0 0 0
T93 24473 0 0 0
T99 0 97 0 0
T100 0 217 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468048268 22765745 0 0
T5 10189 456 0 0
T6 99520 5424 0 0
T7 78249 12954 0 0
T9 136888 7658 0 0
T19 86488 34923 0 0
T20 0 30724 0 0
T38 19098 1082 0 0
T41 29036 844 0 0
T64 15569 0 0 0
T68 26251 0 0 0
T93 24473 0 0 0
T99 0 1498 0 0
T100 0 3356 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468048268 444099141 0 0
T1 10618 10374 0 0
T2 22997 22412 0 0
T3 484294 484281 0 0
T5 10189 9462 0 0
T6 99520 92850 0 0
T7 78249 63469 0 0
T8 77372 77163 0 0
T10 4528 4451 0 0
T11 16448 16247 0 0
T12 22226 21935 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468048268 281651 0 0
T5 10189 49 0 0
T6 99520 430 0 0
T7 78249 360 0 0
T9 136888 851 0 0
T19 86488 211 0 0
T20 0 2439 0 0
T38 19098 91 0 0
T41 29036 94 0 0
T64 15569 0 0 0
T68 26251 0 0 0
T93 24473 0 0 0
T99 0 97 0 0
T100 0 217 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468048268 281651 0 0
T5 10189 49 0 0
T6 99520 430 0 0
T7 78249 360 0 0
T9 136888 851 0 0
T19 86488 211 0 0
T20 0 2439 0 0
T38 19098 91 0 0
T41 29036 94 0 0
T64 15569 0 0 0
T68 26251 0 0 0
T93 24473 0 0 0
T99 0 97 0 0
T100 0 217 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468048268 23065206 0 0
T5 10189 505 0 0
T6 99520 5854 0 0
T7 78249 13314 0 0
T9 136888 8510 0 0
T19 86488 35134 0 0
T20 0 33167 0 0
T38 19098 1174 0 0
T41 29036 938 0 0
T64 15569 0 0 0
T68 26251 0 0 0
T93 24473 0 0 0
T99 0 1596 0 0
T100 0 3574 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 468048268 22765745 0 0
T5 10189 456 0 0
T6 99520 5424 0 0
T7 78249 12954 0 0
T9 136888 7658 0 0
T19 86488 34923 0 0
T20 0 30724 0 0
T38 19098 1082 0 0
T41 29036 844 0 0
T64 15569 0 0 0
T68 26251 0 0 0
T93 24473 0 0 0
T99 0 1498 0 0
T100 0 3356 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468048268 0 0 1149

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468048268 467164347 0 0
T1 10618 10374 0 0
T2 22997 22412 0 0
T3 484294 484281 0 0
T5 10189 9967 0 0
T6 99520 98704 0 0
T7 78249 76783 0 0
T8 77372 77163 0 0
T10 4528 4451 0 0
T11 16448 16247 0 0
T12 22226 21935 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%