Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

26219926

1

T1

3378

T2

13813

T3

2756

full_word

8495699

1

T1

696

T2

5012

T3

1562

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34715335	1			T1	4074		T2	18825		T3	4318
auto[TlIntgErrCmd]	100	1			T260	8		T261	6		T262	6
auto[TlIntgErrData]	98	1			T260	6		T261	9		T262	9
auto[TlIntgErrBoth]	92	1			T260	6		T261	5		T262	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9796298

1

T1

3880

T2

17660

T3

3858

auto[1]

24919327

1

T1

194

T2

1165

T3

460

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6218531	1			T1	3273		T2	13108		T3	2491
auto[TlIntgErrNone]	partial	auto[1]	20001130	1			T1	105		T2	705		T3	265
auto[TlIntgErrNone]	full_word	auto[0]	3577634	1			T1	607		T2	4552		T3	1367
auto[TlIntgErrNone]	full_word	auto[1]	4918040	1			T1	89		T2	460		T3	195
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T260	3		T261	4		T262	3
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T260	4		T261	1		T262	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T262	1		T367	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T260	1		T261	1		T262	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T260	1		T261	3		T262	5
auto[TlIntgErrData]	partial	auto[1]	52	1			T260	4		T261	5		T262	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T371	1		T372	1		T373	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T260	1		T261	1		T374	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T260	4		T261	3		T262	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T260	2		T261	2		T262	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T366	1		T375	1		T376	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T367	1		T373	2		T377	1