Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg
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Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 59.38 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

16 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
lockable_field_cov_of_otp_ctrl_core_reg_block.check_timeout.check_timeout 0.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.creator_sw_cfg_read_lock.creator_sw_cfg_read_lock 50.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_address.direct_access_address 50.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_cmd.digest 50.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_cmd.rd 50.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_cmd.wr 50.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_wdata_0.direct_access_wdata_0 50.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_wdata_1.direct_access_wdata_0 50.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.owner_sw_cfg_read_lock.owner_sw_cfg_read_lock 50.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.rot_creator_auth_codesign_read_lock.rot_creator_auth_codesign_read_lock 50.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.rot_creator_auth_state_read_lock.rot_creator_auth_state_read_lock 50.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.vendor_test_read_lock.vendor_test_read_lock 50.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.check_trigger.consistency 100.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.check_trigger.integrity 100.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.consistency_check_period.consistency_check_period 100.00 1 100 1 64 64
lockable_field_cov_of_otp_ctrl_core_reg_block.integrity_check_period.integrity_check_period 100.00 1 100 1 64 64




Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.check_timeout.check_timeout
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.check_timeout.check_timeout

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 2 0 0.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.check_timeout.check_timeout
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 2 0 0.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.creator_sw_cfg_read_lock.creator_sw_cfg_read_lock
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.creator_sw_cfg_read_lock.creator_sw_cfg_read_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.creator_sw_cfg_read_lock.creator_sw_cfg_read_lock
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_address.direct_access_address
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_address.direct_access_address

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_address.direct_access_address
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_cmd.digest
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_cmd.digest

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_cmd.digest
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_cmd.rd
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_cmd.rd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_cmd.rd
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_cmd.wr
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_cmd.wr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_cmd.wr
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_wdata_0.direct_access_wdata_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_wdata_0.direct_access_wdata_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_wdata_0.direct_access_wdata_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_wdata_1.direct_access_wdata_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_wdata_1.direct_access_wdata_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.direct_access_wdata_1.direct_access_wdata_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.owner_sw_cfg_read_lock.owner_sw_cfg_read_lock
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.owner_sw_cfg_read_lock.owner_sw_cfg_read_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.owner_sw_cfg_read_lock.owner_sw_cfg_read_lock
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.rot_creator_auth_codesign_read_lock.rot_creator_auth_codesign_read_lock
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.rot_creator_auth_codesign_read_lock.rot_creator_auth_codesign_read_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.rot_creator_auth_codesign_read_lock.rot_creator_auth_codesign_read_lock
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.rot_creator_auth_state_read_lock.rot_creator_auth_state_read_lock
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.rot_creator_auth_state_read_lock.rot_creator_auth_state_read_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.rot_creator_auth_state_read_lock.rot_creator_auth_state_read_lock
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.vendor_test_read_lock.vendor_test_read_lock
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.vendor_test_read_lock.vendor_test_read_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.vendor_test_read_lock.vendor_test_read_lock
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.check_trigger.consistency
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.check_trigger.consistency

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.check_trigger.consistency
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.check_trigger.integrity
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.check_trigger.integrity

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.check_trigger.integrity
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.consistency_check_period.consistency_check_period
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.consistency_check_period.consistency_check_period

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.consistency_check_period.consistency_check_period
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_otp_ctrl_core_reg_block.integrity_check_period.integrity_check_period
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.integrity_check_period.integrity_check_period

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_otp_ctrl_core_reg_block.integrity_check_period.integrity_check_period
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6 1 T1 1 T378 1 T379 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 15 1 T1 2 T272 2 T274 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 15 1 T1 1 T272 1 T274 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 17 1 T274 1 T133 1 T380 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 18 1 T274 1 T381 1 T382 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 16 1 T159 1 T383 3 T384 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12 1 T273 1 T133 1 T383 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8 1 T272 1 T382 1 T385 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7 1 T386 2 T387 1 T388 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8 1 T1 2 T389 1 T390 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9 1 T382 2 T388 1 T391 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 317 1 T260 1 T261 4 T295 2
auto[1] 360 1 T263 1 T260 6 T261 5


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 304 1 T260 4 T261 4 T262 1
auto[1] 311 1 T264 1 T260 4 T261 6


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 523 1 T263 1 T260 4 T261 5
auto[1] 470 1 T264 1 T260 12 T392 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 538 1 T263 1 T260 3 T261 5
auto[1] 404 1 T264 1 T260 15 T392 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%