Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.74	96.75	96.15	97.20		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	473582816	8481187	0	0
check_regwen_rd_A	473582816	3697	0	0
check_timeout_rd_A	473582816	2897	0	0
check_trigger_regwen_rd_A	473582816	3156	0	0
consistency_check_period_rd_A	473582816	3712	0	0
creator_sw_cfg_read_lock_rd_A	473582816	2907	0	0
direct_access_address_rd_A	473582816	2742	0	0
direct_access_wdata_0_rd_A	473582816	1758	0	0
direct_access_wdata_1_rd_A	473582816	1989	0	0
integrity_check_period_rd_A	473582816	3367	0	0
intr_enable_rd_A	473582816	4510	0	0
owner_sw_cfg_read_lock_rd_A	473582816	2675	0	0
rot_creator_auth_codesign_read_lock_rd_A	473582816	2850	0	0
rot_creator_auth_state_read_lock_rd_A	473582816	2769	0	0
vendor_test_read_lock_rd_A	473582816	2856	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	8481187	0	0
T5	115711	21615	0	0
T14	0	111262	0	0
T15	0	83900	0	0
T21	0	24060	0	0
T34	18911	0	0	0
T38	0	156501	0	0
T39	11474	0	0	0
T62	0	84241	0	0
T77	14793	0	0	0
T93	108368	0	0	0
T94	75616	0	0	0
T96	44018	0	0	0
T101	10207	0	0	0
T166	20136	0	0	0
T202	0	28681	0	0
T225	0	155341	0	0
T266	0	54556	0	0
T267	0	154456	0	0
T268	20886	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	3697	0	0
T5	115711	22	0	0
T15	0	89	0	0
T21	0	44	0	0
T34	18911	0	0	0
T39	11474	0	0	0
T77	14793	0	0	0
T93	108368	0	0	0
T94	75616	0	0	0
T96	44018	0	0	0
T101	10207	0	0	0
T139	0	48	0	0
T166	20136	0	0	0
T267	0	154	0	0
T268	20886	0	0	0
T276	0	113	0	0
T348	0	54	0	0
T349	0	37	0	0
T350	0	31	0	0
T351	0	84	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	2897	0	0
T5	115711	24	0	0
T15	0	68	0	0
T21	0	28	0	0
T34	18911	0	0	0
T39	11474	0	0	0
T77	14793	0	0	0
T93	108368	0	0	0
T94	75616	0	0	0
T96	44018	0	0	0
T101	10207	0	0	0
T139	0	44	0	0
T166	20136	0	0	0
T267	0	191	0	0
T268	20886	0	0	0
T276	0	62	0	0
T348	0	65	0	0
T349	0	21	0	0
T350	0	46	0	0
T351	0	98	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	3156	0	0
T5	115711	22	0	0
T15	0	44	0	0
T21	0	26	0	0
T34	18911	0	0	0
T39	11474	0	0	0
T77	14793	0	0	0
T93	108368	0	0	0
T94	75616	0	0	0
T96	44018	0	0	0
T101	10207	0	0	0
T139	0	70	0	0
T166	20136	0	0	0
T267	0	161	0	0
T268	20886	0	0	0
T276	0	55	0	0
T348	0	65	0	0
T349	0	11	0	0
T350	0	50	0	0
T351	0	53	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	3712	0	0
T5	115711	11	0	0
T15	0	30	0	0
T21	0	58	0	0
T34	18911	0	0	0
T39	11474	0	0	0
T77	14793	0	0	0
T93	108368	0	0	0
T94	75616	0	0	0
T96	44018	0	0	0
T101	10207	0	0	0
T139	0	52	0	0
T166	20136	0	0	0
T267	0	117	0	0
T268	20886	0	0	0
T276	0	113	0	0
T348	0	88	0	0
T349	0	31	0	0
T350	0	53	0	0
T351	0	69	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	2907	0	0
T5	115711	16	0	0
T15	0	46	0	0
T21	0	37	0	0
T34	18911	0	0	0
T39	11474	0	0	0
T77	14793	0	0	0
T93	108368	0	0	0
T94	75616	0	0	0
T96	44018	0	0	0
T101	10207	0	0	0
T139	0	63	0	0
T166	20136	0	0	0
T267	0	168	0	0
T268	20886	0	0	0
T276	0	41	0	0
T348	0	95	0	0
T349	0	33	0	0
T350	0	38	0	0
T351	0	93	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	2742	0	0
T5	115711	26	0	0
T15	0	86	0	0
T21	0	74	0	0
T34	18911	0	0	0
T39	11474	0	0	0
T77	14793	0	0	0
T93	108368	0	0	0
T94	75616	0	0	0
T96	44018	0	0	0
T101	10207	0	0	0
T139	0	73	0	0
T166	20136	0	0	0
T267	0	154	0	0
T268	20886	0	0	0
T276	0	58	0	0
T348	0	61	0	0
T349	0	45	0	0
T350	0	37	0	0
T351	0	66	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	1758	0	0
T5	115711	12	0	0
T15	0	35	0	0
T21	0	46	0	0
T34	18911	0	0	0
T39	11474	0	0	0
T77	14793	0	0	0
T93	108368	0	0	0
T94	75616	0	0	0
T96	44018	0	0	0
T101	10207	0	0	0
T139	0	26	0	0
T166	20136	0	0	0
T267	0	155	0	0
T268	20886	0	0	0
T276	0	74	0	0
T348	0	54	0	0
T349	0	3	0	0
T350	0	5	0	0
T351	0	79	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	1989	0	0
T5	115711	26	0	0
T15	0	68	0	0
T21	0	1	0	0
T34	18911	0	0	0
T39	11474	0	0	0
T77	14793	0	0	0
T93	108368	0	0	0
T94	75616	0	0	0
T96	44018	0	0	0
T101	10207	0	0	0
T139	0	39	0	0
T166	20136	0	0	0
T267	0	160	0	0
T268	20886	0	0	0
T276	0	74	0	0
T348	0	84	0	0
T349	0	18	0	0
T350	0	27	0	0
T351	0	48	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	3367	0	0
T5	115711	25	0	0
T15	0	86	0	0
T21	0	50	0	0
T34	18911	0	0	0
T39	11474	0	0	0
T77	14793	0	0	0
T93	108368	0	0	0
T94	75616	0	0	0
T96	44018	0	0	0
T101	10207	0	0	0
T139	0	38	0	0
T166	20136	0	0	0
T267	0	199	0	0
T268	20886	0	0	0
T276	0	55	0	0
T348	0	43	0	0
T349	0	41	0	0
T350	0	41	0	0
T351	0	59	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	4510	0	0
T4	495875	11	0	0
T5	115711	45	0	0
T15	0	78	0	0
T20	28907	0	0	0
T21	0	21	0	0
T44	12634	0	0	0
T91	74546	0	0	0
T92	154080	0	0	0
T118	0	23	0	0
T139	0	66	0	0
T166	20136	0	0	0
T185	4869	0	0	0
T229	43046	0	0	0
T230	4463	0	0	0
T267	0	183	0	0
T348	0	63	0	0
T349	0	47	0	0
T352	0	25	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	2675	0	0
T5	115711	19	0	0
T15	0	58	0	0
T21	0	49	0	0
T34	18911	0	0	0
T39	11474	0	0	0
T77	14793	0	0	0
T93	108368	0	0	0
T94	75616	0	0	0
T96	44018	0	0	0
T101	10207	0	0	0
T139	0	34	0	0
T166	20136	0	0	0
T267	0	153	0	0
T268	20886	0	0	0
T276	0	87	0	0
T348	0	65	0	0
T349	0	57	0	0
T350	0	47	0	0
T351	0	117	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	2850	0	0
T5	115711	45	0	0
T15	0	75	0	0
T21	0	30	0	0
T34	18911	0	0	0
T39	11474	0	0	0
T77	14793	0	0	0
T93	108368	0	0	0
T94	75616	0	0	0
T96	44018	0	0	0
T101	10207	0	0	0
T139	0	77	0	0
T166	20136	0	0	0
T267	0	187	0	0
T268	20886	0	0	0
T276	0	99	0	0
T348	0	63	0	0
T349	0	51	0	0
T350	0	37	0	0
T351	0	66	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	2769	0	0
T5	115711	11	0	0
T15	0	85	0	0
T21	0	26	0	0
T34	18911	0	0	0
T39	11474	0	0	0
T77	14793	0	0	0
T93	108368	0	0	0
T94	75616	0	0	0
T96	44018	0	0	0
T101	10207	0	0	0
T139	0	49	0	0
T166	20136	0	0	0
T267	0	204	0	0
T268	20886	0	0	0
T276	0	76	0	0
T348	0	66	0	0
T349	0	14	0	0
T350	0	37	0	0
T351	0	66	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473582816	2856	0	0
T5	115711	38	0	0
T15	0	89	0	0
T21	0	59	0	0
T34	18911	0	0	0
T39	11474	0	0	0
T77	14793	0	0	0
T93	108368	0	0	0
T94	75616	0	0	0
T96	44018	0	0	0
T101	10207	0	0	0
T139	0	46	0	0
T166	20136	0	0	0
T267	0	149	0	0
T268	20886	0	0	0
T276	0	62	0	0
T348	0	62	0	0
T349	0	51	0	0
T350	0	37	0	0
T351	0	108	0	0