Module Definition
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Module : prim_generic_otp
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.81 97.27 96.67 100.00 95.12 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_otp.gen_generic.u_impl_generic 99.45 97.27 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.45 97.27 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.90 93.58 99.81 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_otp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_dec 100.00 100.00 100.00
u_enc 100.00 100.00
u_prim_ram_1p_adv 99.58 98.31 100.00 100.00 100.00
u_reg_top 98.32 91.84 99.74 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_generic_otp
Line No.TotalCoveredPercent
TOTAL11010797.27
CONT_ASSIGN7611100.00
CONT_ASSIGN80100.00
CONT_ASSIGN84100.00
CONT_ASSIGN86100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
ALWAYS1807171100.00
CONT_ASSIGN32911100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35311100.00
CONT_ASSIGN35811100.00
ALWAYS36200
ALWAYS36233100.00
ALWAYS39533100.00
ALWAYS3981919100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
76 1 1
80 0 1
84 0 1
86 0 1
89 1 1
92 1 1
115 1 1
172 1 1
175 1 1
176 1 1
180 1 1
181 1 1
182 1 1
183 1 1
184 1 1
185 1 1
186 1 1
187 1 1
188 1 1
189 1 1
190 1 1
191 1 1
193 1 1
196 1 1
197 1 1
198 1 1
199 1 1
200 1 1
==> MISSING_ELSE
MISSING_ELSE
206 1 1
207 1 1
208 1 1
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
219 1 1
220 1 1
223 1 1
224 1 1
227 1 1
228 1 1
231 1 1
232 1 1
MISSING_ELSE
240 1 1
241 1 1
243 1 1
248 1 1
249 1 1
250 1 1
252 1 1
253 1 1
254 1 1
255 1 1
257 1 1
258 1 1
259 1 1
261 1 1
264 1 1
265 1 1
MISSING_ELSE
MISSING_ELSE
273 1 1
274 1 1
277 1 1
283 1 1
284 1 1
285 1 1
287 1 1
288 1 1
289 1 1
291 1 1
MISSING_ELSE
298 1 1
299 1 1
300 1 1
302 1 1
304 1 1
305 1 1
MISSING_ELSE
308 1 1
309 1 1
310 1 1
MISSING_ELSE
315 1 1
329 1 1
349 1 1
353 1 1
358 1 1
362 1 1
363 1 1
365 1 1
395 3 3
398 1 1
399 1 1
400 1 1
401 1 1
402 1 1
403 1 1
404 1 1
405 1 1
406 1 1
408 1 1
409 1 1
410 1 1
411 1 1
412 1 1
413 1 1
414 1 1
415 1 1
MISSING_ELSE
417 1 1
418 1 1
MISSING_ELSE


Cond Coverage for Module : prim_generic_otp
TotalCoveredPercent
Conditions302996.67
Logical302996.67
Non-Logical00
Event00

 LINE       92
 EXPRESSION (intg_err || fsm_err)
             ----1---    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT25,T26,T27
10CoveredT25,T26,T27

 LINE       172
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       172
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (cmd_i == Init)
            -------1-------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       252
 EXPRESSION (rerror[1] && integrity_en_q)
             ----1----    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT10,T13,T47

 LINE       257
 EXPRESSION (cnt_q == size_q)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       264
 EXPRESSION (rerror[0] && integrity_en_q)
             ----1----    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT47,T4,T166

 LINE       287
 EXPRESSION (cnt_q == size_q)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       308
 EXPRESSION (cnt_q == size_q)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       349
 EXPRESSION (read_ecc_on ? ({{EccWidth {1'b0}}, rdata_corr}) : rdata_ecc)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       353
 EXPRESSION (write_ecc_on ? ((wdata_ecc | rdata_q[cnt_q])) : (({{EccWidth {1'b0}}, wdata_q[cnt_q]} | rdata_q[cnt_q])))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION ((rdata_q[cnt_q] & wdata_ecc) != rdata_q[cnt_q])
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       412
 EXPRESSION (ready_o && valid_i)
             ---1---    ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

FSM Coverage for Module : prim_generic_otp
Summary for FSM :: state_q
TotalCoveredPercent
States 9 9 100.00 (Not included in score)
Transitions 11 11 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
ErrorSt 314 Covered T25,T26,T27
IdleSt 206 Covered T1,T2,T3
InitSt 200 Covered T1,T2,T3
ReadSt 219 Covered T1,T2,T3
ReadWaitSt 240 Covered T1,T2,T3
ResetSt 195 Covered T1,T2,T3
WriteCheckSt 223 Covered T1,T2,T3
WriteSt 289 Covered T1,T2,T3
WriteWaitSt 273 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
IdleSt->ReadSt 219 Covered T1,T2,T3
IdleSt->WriteCheckSt 223 Covered T1,T2,T3
InitSt->IdleSt 206 Covered T1,T2,T3
ReadSt->ReadWaitSt 240 Covered T1,T2,T3
ReadWaitSt->IdleSt 253 Covered T1,T2,T3
ReadWaitSt->ReadSt 261 Covered T1,T2,T3
ResetSt->InitSt 200 Covered T1,T2,T3
WriteCheckSt->WriteWaitSt 273 Covered T1,T2,T3
WriteSt->IdleSt 310 Covered T1,T2,T3
WriteWaitSt->WriteCheckSt 291 Covered T1,T2,T3
WriteWaitSt->WriteSt 289 Covered T1,T2,T3



Branch Coverage for Module : prim_generic_otp
Line No.TotalCoveredPercent
Branches 41 39 95.12
TERNARY 172 3 3 100.00
TERNARY 349 2 2 100.00
TERNARY 353 2 2 100.00
CASE 193 27 25 92.59
IF 395 2 2 100.00
IF 398 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 172 (cnt_clr) ? -2-: 172 (cnt_en) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 349 (read_ecc_on) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 353 (write_ecc_on) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 193 case (state_q) -2-: 198 if (valid_i) -3-: 199 if ((cmd_i == Init)) -4-: 214 if (valid_i) -5-: 217 case (cmd_i) -6-: 249 if (rvalid) -7-: 252 if ((rerror[1] && integrity_en_q)) -8-: 257 if ((cnt_q == size_q)) -9-: 264 if ((rerror[0] && integrity_en_q)) -10-: 284 if (rvalid) -11-: 287 if ((cnt_q == size_q)) -12-: 304 if (wdata_inconsistent) -13-: 308 if ((cnt_q == size_q))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTests
ResetSt 1 1 - - - - - - - - - - Covered T1,T2,T3
ResetSt 1 0 - - - - - - - - - - Not Covered
ResetSt 0 - - - - - - - - - - - Covered T1,T2,T3
InitSt - - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - 1 Read - - - - - - - - Covered T1,T2,T3
IdleSt - - 1 Write - - - - - - - - Covered T1,T2,T3
IdleSt - - 1 ReadRaw - - - - - - - - Covered T1,T2,T3
IdleSt - - 1 WriteRaw - - - - - - - - Covered T1,T2,T3
IdleSt - - 1 default - - - - - - - - Not Covered
IdleSt - - 0 - - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - - - - - - Covered T1,T2,T3
ReadWaitSt - - - - 1 1 - - - - - - Covered T10,T13,T47
ReadWaitSt - - - - 1 0 1 - - - - - Covered T1,T2,T3
ReadWaitSt - - - - 1 0 0 - - - - - Covered T1,T2,T3
ReadWaitSt - - - - 1 0 - 1 - - - - Covered T47,T4,T166
ReadWaitSt - - - - 1 0 - 0 - - - - Covered T1,T2,T3
ReadWaitSt - - - - 0 - - - - - - - Covered T1,T2,T3
WriteCheckSt - - - - - - - - - - - - Covered T1,T2,T3
WriteWaitSt - - - - - - - - 1 1 - - Covered T1,T2,T3
WriteWaitSt - - - - - - - - 1 0 - - Covered T1,T2,T3
WriteWaitSt - - - - - - - - 0 - - - Covered T1,T2,T3
WriteSt - - - - - - - - - - 1 - Covered T4,T6,T16
WriteSt - - - - - - - - - - 0 - Covered T1,T2,T3
WriteSt - - - - - - - - - - - 1 Covered T1,T2,T3
WriteSt - - - - - - - - - - - 0 Covered T1,T2,T3
ErrorSt - - - - - - - - - - - - Covered T25,T26,T27
default - - - - - - - - - - - - Covered T25,T26,T27


LineNo. Expression -1-: 395 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 398 if ((!rst_ni)) -2-: 412 if ((ready_o && valid_i)) -3-: 417 if (rvalid)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


Assert Coverage for Module : prim_generic_otp
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CheckCommands0_A 470757263 12042 0 0
CheckCommands1_A 470757263 1427505 0 0
NoWrapArounds_A 470757263 4290648 0 0
SecDecWidth_A 1150 1150 0 0
u_state_regs_A 470757263 469877569 0 0


CheckCommands0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470757263 12042 0 0
T1 26015 8 0 0
T2 77003 16 0 0
T3 89819 13 0 0
T7 72111 17 0 0
T8 34081 7 0 0
T9 62025 20 0 0
T10 13625 2 0 0
T11 55720 7 0 0
T12 47628 8 0 0
T13 14711 3 0 0

CheckCommands1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470757263 1427505 0 0
T1 26015 609 0 0
T2 77003 1526 0 0
T3 89819 1158 0 0
T7 72111 3224 0 0
T8 34081 543 0 0
T9 62025 2874 0 0
T10 13625 160 0 0
T11 55720 532 0 0
T12 47628 574 0 0
T13 14711 181 0 0

NoWrapArounds_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470757263 4290648 0 0
T1 26015 2066 0 0
T2 77003 4803 0 0
T3 89819 3904 0 0
T7 72111 8372 0 0
T8 34081 1896 0 0
T9 62025 7647 0 0
T10 13625 581 0 0
T11 55720 1848 0 0
T12 47628 1962 0 0
T13 14711 703 0 0

SecDecWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470757263 469877569 0 0
T1 26015 25482 0 0
T2 77003 75762 0 0
T3 89819 88785 0 0
T7 72111 70888 0 0
T8 34081 33503 0 0
T9 62025 60711 0 0
T10 13625 13409 0 0
T11 55720 55218 0 0
T12 47628 47091 0 0
T13 14711 14428 0 0

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11010797.27
CONT_ASSIGN7611100.00
CONT_ASSIGN80100.00
CONT_ASSIGN84100.00
CONT_ASSIGN86100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
ALWAYS1807171100.00
CONT_ASSIGN32911100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35311100.00
CONT_ASSIGN35811100.00
ALWAYS36200
ALWAYS36233100.00
ALWAYS39533100.00
ALWAYS3981919100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
76 1 1
80 0 1
84 0 1
86 0 1
89 1 1
92 1 1
115 1 1
172 1 1
175 1 1
176 1 1
180 1 1
181 1 1
182 1 1
183 1 1
184 1 1
185 1 1
186 1 1
187 1 1
188 1 1
189 1 1
190 1 1
191 1 1
193 1 1
196 1 1
197 1 1
198 1 1
199 1 1
200 1 1
==> MISSING_ELSE
MISSING_ELSE
206 1 1
207 1 1
208 1 1
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
219 1 1
220 1 1
223 1 1
224 1 1
227 1 1
228 1 1
231 1 1
232 1 1
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
240 1 1
241 1 1
243 1 1
248 1 1
249 1 1
250 1 1
252 1 1
253 1 1
254 1 1
255 1 1
257 1 1
258 1 1
259 1 1
261 1 1
264 1 1
265 1 1
MISSING_ELSE
MISSING_ELSE
273 1 1
274 1 1
277 1 1
283 1 1
284 1 1
285 1 1
287 1 1
288 1 1
289 1 1
291 1 1
MISSING_ELSE
298 1 1
299 1 1
300 1 1
302 1 1
304 1 1
305 1 1
MISSING_ELSE
308 1 1
309 1 1
310 1 1
MISSING_ELSE
315 1 1
329 1 1
349 1 1
353 1 1
358 1 1
362 1 1
363 1 1
365 1 1
395 3 3
398 1 1
399 1 1
400 1 1
401 1 1
402 1 1
403 1 1
404 1 1
405 1 1
406 1 1
408 1 1
409 1 1
410 1 1
411 1 1
412 1 1
413 1 1
414 1 1
415 1 1
MISSING_ELSE
417 1 1
418 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions2929100.00
Logical2929100.00
Non-Logical00
Event00

 LINE       92
 EXPRESSION (intg_err || fsm_err)
             ----1---    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT25,T26,T27
10CoveredT25,T26,T27

 LINE       172
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       172
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (cmd_i == Init)
            -------1-------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT1,T2,T3

 LINE       252
 EXPRESSION (rerror[1] && integrity_en_q)
             ----1----    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT10,T13,T47

 LINE       257
 EXPRESSION (cnt_q == size_q)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       264
 EXPRESSION (rerror[0] && integrity_en_q)
             ----1----    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT47,T4,T166

 LINE       287
 EXPRESSION (cnt_q == size_q)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       308
 EXPRESSION (cnt_q == size_q)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       349
 EXPRESSION (read_ecc_on ? ({{EccWidth {1'b0}}, rdata_corr}) : rdata_ecc)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       353
 EXPRESSION (write_ecc_on ? ((wdata_ecc | rdata_q[cnt_q])) : (({{EccWidth {1'b0}}, wdata_q[cnt_q]} | rdata_q[cnt_q])))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION ((rdata_q[cnt_q] & wdata_ecc) != rdata_q[cnt_q])
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       412
 EXPRESSION (ready_o && valid_i)
             ---1---    ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic
Summary for FSM :: state_q
TotalCoveredPercent
States 9 9 100.00 (Not included in score)
Transitions 11 11 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
ErrorSt 314 Covered T25,T26,T27
IdleSt 206 Covered T1,T2,T3
InitSt 200 Covered T1,T2,T3
ReadSt 219 Covered T1,T2,T3
ReadWaitSt 240 Covered T1,T2,T3
ResetSt 195 Covered T1,T2,T3
WriteCheckSt 223 Covered T1,T2,T3
WriteSt 289 Covered T1,T2,T3
WriteWaitSt 273 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
IdleSt->ReadSt 219 Covered T1,T2,T3
IdleSt->WriteCheckSt 223 Covered T1,T2,T3
InitSt->IdleSt 206 Covered T1,T2,T3
ReadSt->ReadWaitSt 240 Covered T1,T2,T3
ReadWaitSt->IdleSt 253 Covered T1,T2,T3
ReadWaitSt->ReadSt 261 Covered T1,T2,T3
ResetSt->InitSt 200 Covered T1,T2,T3
WriteCheckSt->WriteWaitSt 273 Covered T1,T2,T3
WriteSt->IdleSt 310 Covered T1,T2,T3
WriteWaitSt->WriteCheckSt 291 Covered T1,T2,T3
WriteWaitSt->WriteSt 289 Covered T1,T2,T3



Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 39 39 100.00
TERNARY 172 3 3 100.00
TERNARY 349 2 2 100.00
TERNARY 353 2 2 100.00
CASE 193 25 25 100.00
IF 395 2 2 100.00
IF 398 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 172 (cnt_clr) ? -2-: 172 (cnt_en) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 349 (read_ecc_on) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 353 (write_ecc_on) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 193 case (state_q) -2-: 198 if (valid_i) -3-: 199 if ((cmd_i == Init)) -4-: 214 if (valid_i) -5-: 217 case (cmd_i) -6-: 249 if (rvalid) -7-: 252 if ((rerror[1] && integrity_en_q)) -8-: 257 if ((cnt_q == size_q)) -9-: 264 if ((rerror[0] && integrity_en_q)) -10-: 284 if (rvalid) -11-: 287 if ((cnt_q == size_q)) -12-: 304 if (wdata_inconsistent) -13-: 308 if ((cnt_q == size_q))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTestsExclude Annotation
ResetSt 1 1 - - - - - - - - - - Covered T1,T2,T3
ResetSt 1 0 - - - - - - - - - - Excluded VC_COV_UNR
ResetSt 0 - - - - - - - - - - - Covered T1,T2,T3
InitSt - - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - 1 Read - - - - - - - - Covered T1,T2,T3
IdleSt - - 1 Write - - - - - - - - Covered T1,T2,T3
IdleSt - - 1 ReadRaw - - - - - - - - Covered T1,T2,T3
IdleSt - - 1 WriteRaw - - - - - - - - Covered T1,T2,T3
IdleSt - - 1 default - - - - - - - - Excluded VC_COV_UNR
IdleSt - - 0 - - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - - - - - - Covered T1,T2,T3
ReadWaitSt - - - - 1 1 - - - - - - Covered T10,T13,T47
ReadWaitSt - - - - 1 0 1 - - - - - Covered T1,T2,T3
ReadWaitSt - - - - 1 0 0 - - - - - Covered T1,T2,T3
ReadWaitSt - - - - 1 0 - 1 - - - - Covered T47,T4,T166
ReadWaitSt - - - - 1 0 - 0 - - - - Covered T1,T2,T3
ReadWaitSt - - - - 0 - - - - - - - Covered T1,T2,T3
WriteCheckSt - - - - - - - - - - - - Covered T1,T2,T3
WriteWaitSt - - - - - - - - 1 1 - - Covered T1,T2,T3
WriteWaitSt - - - - - - - - 1 0 - - Covered T1,T2,T3
WriteWaitSt - - - - - - - - 0 - - - Covered T1,T2,T3
WriteSt - - - - - - - - - - 1 - Covered T4,T6,T16
WriteSt - - - - - - - - - - 0 - Covered T1,T2,T3
WriteSt - - - - - - - - - - - 1 Covered T1,T2,T3
WriteSt - - - - - - - - - - - 0 Covered T1,T2,T3
ErrorSt - - - - - - - - - - - - Covered T25,T26,T27
default - - - - - - - - - - - - Covered T25,T26,T27


LineNo. Expression -1-: 395 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 398 if ((!rst_ni)) -2-: 412 if ((ready_o && valid_i)) -3-: 417 if (rvalid)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CheckCommands0_A 470757263 12042 0 0
CheckCommands1_A 470757263 1427505 0 0
NoWrapArounds_A 470757263 4290648 0 0
SecDecWidth_A 1150 1150 0 0
u_state_regs_A 470757263 469877569 0 0


CheckCommands0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470757263 12042 0 0
T1 26015 8 0 0
T2 77003 16 0 0
T3 89819 13 0 0
T7 72111 17 0 0
T8 34081 7 0 0
T9 62025 20 0 0
T10 13625 2 0 0
T11 55720 7 0 0
T12 47628 8 0 0
T13 14711 3 0 0

CheckCommands1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470757263 1427505 0 0
T1 26015 609 0 0
T2 77003 1526 0 0
T3 89819 1158 0 0
T7 72111 3224 0 0
T8 34081 543 0 0
T9 62025 2874 0 0
T10 13625 160 0 0
T11 55720 532 0 0
T12 47628 574 0 0
T13 14711 181 0 0

NoWrapArounds_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470757263 4290648 0 0
T1 26015 2066 0 0
T2 77003 4803 0 0
T3 89819 3904 0 0
T7 72111 8372 0 0
T8 34081 1896 0 0
T9 62025 7647 0 0
T10 13625 581 0 0
T11 55720 1848 0 0
T12 47628 1962 0 0
T13 14711 703 0 0

SecDecWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 470757263 469877569 0 0
T1 26015 25482 0 0
T2 77003 75762 0 0
T3 89819 88785 0 0
T7 72111 70888 0 0
T8 34081 33503 0 0
T9 62025 60711 0 0
T10 13625 13409 0 0
T11 55720 55218 0 0
T12 47628 47091 0 0
T13 14711 14428 0 0