dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 62.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 62.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 62.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 62.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 62.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 62.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 62.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 62.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 62.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 62.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 62.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 62.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 62.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00


Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 62.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00

Go back
Module Instances:
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3
Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T19,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T19,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3
Line No.TotalCoveredPercent
TOTAL6583.33
ALWAYS5633100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4
Line No.TotalCoveredPercent
TOTAL6583.33
ALWAYS5633100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5
Line No.TotalCoveredPercent
TOTAL6583.33
ALWAYS5633100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6
Line No.TotalCoveredPercent
TOTAL6583.33
ALWAYS5633100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7
Line No.TotalCoveredPercent
TOTAL6583.33
ALWAYS5633100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8
Line No.TotalCoveredPercent
TOTAL6583.33
ALWAYS5633100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T19,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T19,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T19,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T19,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T19,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T19,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2
Line No.TotalCoveredPercent
TOTAL6583.33
ALWAYS5633100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3
Line No.TotalCoveredPercent
TOTAL6583.33
ALWAYS5633100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4
Line No.TotalCoveredPercent
TOTAL6583.33
ALWAYS5633100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5
Line No.TotalCoveredPercent
TOTAL6583.33
ALWAYS5633100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T19,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T19,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T19,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T19,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T19,T20

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T19,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0
Line No.TotalCoveredPercent
TOTAL6583.33
ALWAYS5633100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1
Line No.TotalCoveredPercent
TOTAL6583.33
ALWAYS5633100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2
Line No.TotalCoveredPercent
TOTAL6583.33
ALWAYS5633100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3
Line No.TotalCoveredPercent
TOTAL6583.33
ALWAYS5633100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%