Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.74	96.75	96.15	97.20		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.74	96.75	96.15	97.20		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.74	96.75	96.15	97.20		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T10,T13
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T121,T123,T124
1	Covered	T121,T123,T124

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T10,T13
1	Covered	T3,T10,T13

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T10,T13
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T10,T13
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T172,T173,T174
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T175,T176,T177
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T3,T9
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T2,T3,T9
CheckFailError	317	Covered	T121,T123,T124
FsmStateError	289	Covered	T3,T10,T13
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T14,T16,T38
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T2,T3,T9
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T121,T123,T124
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T3,T10,T13
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T2,T3,T9
NoError->CheckFailError	317	Covered	T121,T123,T124
NoError->FsmStateError	289	Covered	T3,T10,T13
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T9,T96,T6
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T27
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T10,T13
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T47,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T47,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T10,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T121,T123,T124
1	0	Covered	T121,T123,T124
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T10,T13
1	0	Covered	T3,T10,T13
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T10,T13,T47
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	470757263	469877569	0	0
DigestKnown_A	470757263	469877569	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	470757263	12806	0	0
ErrorKnown_A	470757263	469877569	0	0
FsmStateKnown_A	470757263	469877569	0	0
InitDoneKnown_A	470757263	469877569	0	0
InitReadLocksPartition_A	470757263	103437591	0	0
InitWriteLocksPartition_A	470757263	103437591	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	470757263	469877569	0	0
OtpCmdKnown_A	470757263	469877569	0	0
OtpErrorState_A	470757263	0	0	0
OtpReqKnown_A	470757263	469877569	0	0
OtpSizeKnown_A	470757263	469877569	0	0
OtpWdataKnown_A	470757263	469877569	0	0
ReadLockPropagation_A	470757263	201676159	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	470757263	469877569	0	0
TlulRdataKnown_A	470757263	469877569	0	0
TlulReadOnReadLock_A	470757263	7476	0	0
TlulRerrorKnown_A	470757263	469877569	0	0
TlulRvalidKnown_A	470757263	469877569	0	0
WriteLockPropagation_A	470757263	2332096	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	470757263	27713276	0	0
u_state_regs_A	470757263	469877569	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	12806	0	0
T29	10730	0	0	0
T31	318179	0	0	0
T68	27648	0	0	0
T79	17988	0	0	0
T121	11414	2791	0	0
T123	0	3533	0	0
T124	0	3988	0	0
T131	0	2494	0	0
T141	10581	0	0	0
T142	93327	0	0	0
T143	67995	0	0	0
T144	38343	0	0	0
T145	76516	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	103437591	0	0
T1	26015	643	0	0
T2	77003	779	0	0
T3	89819	1359	0	0
T7	72111	5057	0	0
T8	34081	350	0	0
T9	62025	927	0	0
T10	13625	5134	0	0
T11	55720	2007	0	0
T12	47628	329	0	0
T13	14711	4828	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	103437591	0	0
T1	26015	643	0	0
T2	77003	779	0	0
T3	89819	1359	0	0
T7	72111	5057	0	0
T8	34081	350	0	0
T9	62025	927	0	0
T10	13625	5134	0	0
T11	55720	2007	0	0
T12	47628	329	0	0
T13	14711	4828	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	201676159	0	0
T2	77003	15116	0	0
T3	89819	9746	0	0
T4	0	22678	0	0
T7	72111	401	0	0
T8	34081	853	0	0
T9	62025	5213	0	0
T10	13625	0	0	0
T11	55720	0	0	0
T12	47628	0	0	0
T13	14711	0	0	0
T18	79829	2765	0	0
T19	0	2946	0	0
T95	0	22086	0	0
T99	0	14097	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	7476	0	0
T2	77003	8	0	0
T3	89819	4	0	0
T4	0	7	0	0
T7	72111	0	0	0
T8	34081	0	0	0
T9	62025	5	0	0
T10	13625	0	0	0
T11	55720	0	0	0
T12	47628	0	0	0
T13	14711	0	0	0
T18	79829	0	0	0
T19	0	1	0	0
T47	0	1	0	0
T91	0	2	0	0
T92	0	11	0	0
T95	0	2	0	0
T99	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	2332096	0	0
T4	0	28362	0	0
T6	0	26087	0	0
T7	72111	3716	0	0
T8	34081	0	0	0
T9	62025	6272	0	0
T10	13625	0	0	0
T11	55720	0	0	0
T12	47628	0	0	0
T13	14711	0	0	0
T17	50485	0	0	0
T18	79829	976	0	0
T19	60453	0	0	0
T91	0	13685	0	0
T94	0	2777	0	0
T95	0	27069	0	0
T96	0	4944	0	0
T97	0	7832	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	27713276	0	0
T2	77003	64052	0	0
T3	89819	77135	0	0
T7	72111	35757	0	0
T8	34081	25210	0	0
T9	62025	53723	0	0
T10	13625	3859	0	0
T11	55720	0	0	0
T12	47628	0	0	0
T13	14711	0	0	0
T18	79829	64372	0	0
T19	0	28250	0	0
T95	0	115442	0	0
T99	0	12563	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T125,T126,T85

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T47,T41,T42

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T10,T13
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T121,T123,T124
1	Covered	T121,T123,T124

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T10,T13
1	Covered	T3,T10,T13

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T10,T13
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T10,T13
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T175,T172,T176
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T100,T127,T146
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T3,T9
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T90,T128,T178
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T3,T9
CheckFailError	317	Covered	T121,T123,T124
FsmStateError	289	Covered	T3,T10,T13
MacroEccCorrError	221	Covered	T47,T41,T125
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T14,T163
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T3,T9
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T121,T123,T124
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T10,T13
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T47,T125,T126
MacroEccCorrError->NoError	235	Covered	T41,T42,T71
NoError->AccessError	256	Covered	T2,T3,T9
NoError->CheckFailError	317	Covered	T121,T123,T124
NoError->FsmStateError	289	Covered	T3,T10,T13
NoError->MacroEccCorrError	221	Covered	T47,T41,T125

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T125,T126,T85
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T100,T127,T146
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T7,T9,T4
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T47,T41,T42
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T90,T128,T178
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T27
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T10,T13
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T47,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T47,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T10,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T121,T123,T124
1	0	Covered	T121,T123,T124
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T10,T13
1	0	Covered	T3,T10,T13
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	470757263	469877569	0	0
DigestKnown_A	470757263	469877569	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	470757263	12806	0	0
ErrorKnown_A	470757263	469877569	0	0
FsmStateKnown_A	470757263	469877569	0	0
InitDoneKnown_A	470757263	469877569	0	0
InitReadLocksPartition_A	470757263	103622084	0	0
InitWriteLocksPartition_A	470757263	103622084	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	470757263	469877569	0	0
OtpCmdKnown_A	470757263	469877569	0	0
OtpErrorState_A	470757263	65	0	0
OtpReqKnown_A	470757263	469877569	0	0
OtpSizeKnown_A	470757263	469877569	0	0
OtpWdataKnown_A	470757263	469877569	0	0
ReadLockPropagation_A	470757263	198001294	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	470757263	469877569	0	0
TlulRdataKnown_A	470757263	469877569	0	0
TlulReadOnReadLock_A	470757263	7786	0	0
TlulRerrorKnown_A	470757263	469877569	0	0
TlulRvalidKnown_A	470757263	469877569	0	0
WriteLockPropagation_A	470757263	2064581	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	470757263	27145056	0	0
u_state_regs_A	470757263	469877569	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	12806	0	0
T29	10730	0	0	0
T31	318179	0	0	0
T68	27648	0	0	0
T79	17988	0	0	0
T121	11414	2791	0	0
T123	0	3533	0	0
T124	0	3988	0	0
T131	0	2494	0	0
T141	10581	0	0	0
T142	93327	0	0	0
T143	67995	0	0	0
T144	38343	0	0	0
T145	76516	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	103622084	0	0
T1	26015	745	0	0
T2	77003	1000	0	0
T3	89819	1563	0	0
T7	72111	5329	0	0
T8	34081	452	0	0
T9	62025	1182	0	0
T10	13625	5168	0	0
T11	55720	2092	0	0
T12	47628	448	0	0
T13	14711	4879	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	103622084	0	0
T1	26015	745	0	0
T2	77003	1000	0	0
T3	89819	1563	0	0
T7	72111	5329	0	0
T8	34081	452	0	0
T9	62025	1182	0	0
T10	13625	5168	0	0
T11	55720	2092	0	0
T12	47628	448	0	0
T13	14711	4879	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	65	0	0
T14	372261	0	0	0
T41	73775	0	0	0
T90	0	1	0	0
T97	69840	0	0	0
T100	12641	1	0	0
T125	10220	0	0	0
T127	0	1	0	0
T128	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T152	0	1	0	0
T155	0	1	0	0
T157	89223	0	0	0
T158	16753	0	0	0
T159	9199	0	0	0
T160	10452	0	0	0
T161	12019	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	198001294	0	0
T2	77003	17237	0	0
T3	89819	9480	0	0
T4	0	30383	0	0
T7	72111	910	0	0
T8	34081	969	0	0
T9	62025	4526	0	0
T10	13625	0	0	0
T11	55720	0	0	0
T12	47628	0	0	0
T13	14711	0	0	0
T18	79829	2208	0	0
T19	0	2187	0	0
T95	0	22077	0	0
T99	0	14085	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	7786	0	0
T2	77003	5	0	0
T3	89819	1	0	0
T4	0	6	0	0
T7	72111	0	0	0
T8	34081	0	0	0
T9	62025	7	0	0
T10	13625	0	0	0
T11	55720	0	0	0
T12	47628	0	0	0
T13	14711	0	0	0
T18	79829	0	0	0
T19	0	2	0	0
T47	0	4	0	0
T91	0	3	0	0
T92	0	12	0	0
T95	0	1	0	0
T99	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	2064581	0	0
T3	89819	6415	0	0
T4	0	4219	0	0
T6	0	15412	0	0
T7	72111	0	0	0
T8	34081	0	0	0
T9	62025	6947	0	0
T10	13625	0	0	0
T11	55720	0	0	0
T12	47628	0	0	0
T13	14711	0	0	0
T18	79829	5374	0	0
T19	60453	0	0	0
T91	0	7624	0	0
T92	0	57563	0	0
T93	0	7158	0	0
T94	0	4279	0	0
T96	0	1106	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	27145056	0	0
T2	77003	63865	0	0
T3	89819	76948	0	0
T4	0	140362	0	0
T7	72111	35604	0	0
T8	34081	18639	0	0
T9	62025	53502	0	0
T10	13625	0	0	0
T11	55720	0	0	0
T12	47628	0	0	0
T13	14711	0	0	0
T18	79829	64134	0	0
T19	0	28182	0	0
T95	0	115408	0	0
T99	0	12546	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T101,T105,T40

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T42,T71

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T10,T13
1	Covered	T25,T26,T27

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T74
1	Covered	T74

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T10,T13
1	Covered	T3,T10,T13

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T99

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T99

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T10,T13
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T10,T13
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T98,T175,T172
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T100,T125,T127
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T3,T9
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T90,T128,T179
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T3,T9
CheckFailError	317	Covered	T74
FsmStateError	289	Covered	T3,T10,T13
MacroEccCorrError	221	Covered	T101,T41,T42
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T14,T16
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T3,T9
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T74
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T10,T13
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T101,T105,T128
MacroEccCorrError->NoError	235	Covered	T41,T42,T71
NoError->AccessError	256	Covered	T2,T3,T9
NoError->CheckFailError	317	Covered	T74
NoError->FsmStateError	289	Covered	T3,T10,T13
NoError->MacroEccCorrError	221	Covered	T101,T41,T42

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T99
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T101,T105,T40
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T125,T85,T150
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T9,T4,T6
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T41,T42,T71
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T90,T128,T179
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T27
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T10,T13
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T47,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T47,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T10,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T74
1	0	Covered	T74
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T10,T13
1	0	Covered	T3,T10,T13
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	470757263	469877569	0	0
DigestKnown_A	470757263	469877569	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	470757263	3230	0	0
ErrorKnown_A	470757263	469877569	0	0
FsmStateKnown_A	470757263	469877569	0	0
InitDoneKnown_A	470757263	469877569	0	0
InitReadLocksPartition_A	470757263	103805427	0	0
InitWriteLocksPartition_A	470757263	103805427	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	470757263	469877569	0	0
OtpCmdKnown_A	470757263	469877569	0	0
OtpErrorState_A	470757263	61	0	0
OtpReqKnown_A	470757263	469877569	0	0
OtpSizeKnown_A	470757263	469877569	0	0
OtpWdataKnown_A	470757263	469877569	0	0
ReadLockPropagation_A	470757263	211913453	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	470757263	469877569	0	0
TlulRdataKnown_A	470757263	469877569	0	0
TlulReadOnReadLock_A	470757263	7891	0	0
TlulRerrorKnown_A	470757263	469877569	0	0
TlulRvalidKnown_A	470757263	469877569	0	0
WriteLockPropagation_A	470757263	1559570	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	470757263	18595212	0	0
u_state_regs_A	470757263	469877569	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	3230	0	0
T74	12091	3230	0	0
T132	30253	0	0	0
T133	13642	0	0	0
T134	14343	0	0	0
T135	9690	0	0	0
T136	30684	0	0	0
T137	8609	0	0	0
T138	15698	0	0	0
T139	206706	0	0	0
T140	4423	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	103805427	0	0
T1	26015	847	0	0
T2	77003	1221	0	0
T3	89819	1767	0	0
T7	72111	5601	0	0
T8	34081	554	0	0
T9	62025	1437	0	0
T10	13625	5202	0	0
T11	55720	2177	0	0
T12	47628	567	0	0
T13	14711	4930	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	103805427	0	0
T1	26015	847	0	0
T2	77003	1221	0	0
T3	89819	1767	0	0
T7	72111	5601	0	0
T8	34081	554	0	0
T9	62025	1437	0	0
T10	13625	5202	0	0
T11	55720	2177	0	0
T12	47628	567	0	0
T13	14711	4930	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	61	0	0
T16	36023	0	0	0
T70	97012	0	0	0
T85	0	1	0	0
T90	0	1	0	0
T98	518607	0	0	0
T125	10220	1	0	0
T127	11208	0	0	0
T128	0	1	0	0
T135	0	1	0	0
T138	0	1	0	0
T146	11012	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T162	4746	0	0	0
T163	22412	0	0	0
T164	11170	0	0	0
T165	32543	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	211913453	0	0
T2	77003	15698	0	0
T3	89819	7591	0	0
T4	0	49542	0	0
T7	72111	784	0	0
T8	34081	0	0	0
T9	62025	3767	0	0
T10	13625	0	0	0
T11	55720	0	0	0
T12	47628	0	0	0
T13	14711	0	0	0
T18	79829	1779	0	0
T19	0	2929	0	0
T91	0	21925	0	0
T95	0	19670	0	0
T99	0	14081	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	7891	0	0
T2	77003	11	0	0
T3	89819	2	0	0
T4	0	16	0	0
T5	0	26	0	0
T7	72111	0	0	0
T8	34081	0	0	0
T9	62025	3	0	0
T10	13625	0	0	0
T11	55720	0	0	0
T12	47628	0	0	0
T13	14711	0	0	0
T18	79829	3	0	0
T47	0	5	0	0
T91	0	5	0	0
T92	0	10	0	0
T99	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	1559570	0	0
T4	0	20298	0	0
T6	0	9871	0	0
T7	72111	418	0	0
T8	34081	0	0	0
T9	62025	1156	0	0
T10	13625	0	0	0
T11	55720	0	0	0
T12	47628	0	0	0
T13	14711	0	0	0
T17	50485	0	0	0
T18	79829	0	0	0
T19	60453	0	0	0
T41	0	3723	0	0
T92	0	39586	0	0
T93	0	12266	0	0
T94	0	7051	0	0
T96	0	2705	0	0
T98	0	16104	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	18595212	0	0
T4	0	152221	0	0
T6	0	218569	0	0
T7	72111	35451	0	0
T8	34081	0	0	0
T9	62025	53281	0	0
T10	13625	0	0	0
T11	55720	0	0	0
T12	47628	0	0	0
T13	14711	0	0	0
T17	50485	0	0	0
T18	79829	0	0	0
T19	60453	0	0	0
T92	0	130028	0	0
T93	0	93906	0	0
T94	0	65145	0	0
T96	0	36053	0	0
T99	0	12529	0	0
T166	0	4953	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470757263	469877569	0	0
T1	26015	25482	0	0
T2	77003	75762	0	0
T3	89819	88785	0	0
T7	72111	70888	0	0
T8	34081	33503	0	0
T9	62025	60711	0	0
T10	13625	13409	0	0
T11	55720	55218	0	0
T12	47628	47091	0	0
T13	14711	14428	0	0