Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

27912119

1

T1

7281

T2

3350

T3

7479

full_word

9035503

1

T1

5702

T2

2364

T3

6766

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	36947302	1			T1	12983		T2	5714		T3	14245
auto[TlIntgErrCmd]	123	1			T296	5		T297	9		T298	3
auto[TlIntgErrData]	98	1			T296	6		T297	4		T298	2
auto[TlIntgErrBoth]	99	1			T296	9		T297	7		T298	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10169901

1

T1

11596

T2

5067

T3

11959

auto[1]

26777721

1

T1

1387

T2

647

T3

2286

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6412949	1			T1	6429		T2	2972		T3	6277
auto[TlIntgErrNone]	partial	auto[1]	21498884	1			T1	852		T2	378		T3	1202
auto[TlIntgErrNone]	full_word	auto[0]	3756824	1			T1	5167		T2	2095		T3	5682
auto[TlIntgErrNone]	full_word	auto[1]	5278645	1			T1	535		T2	269		T3	1084
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T296	1		T297	3		T298	1
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T296	4		T297	6		T298	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T366	2		T372	1		T373	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T365	1		T366	1		T367	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T296	3		T297	1		T298	2
auto[TlIntgErrData]	partial	auto[1]	42	1			T296	2		T297	3		T366	5
auto[TlIntgErrData]	full_word	auto[0]	1	1			T374	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T296	1		T366	2		T369	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T296	1		T297	4		T298	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T296	7		T297	2		T298	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T375	1		T374	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T296	1		T297	1		T366	1