Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.92	98.05	96.15	96.77		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	502086640	9134766	0	0
check_regwen_rd_A	502086640	4394	0	0
check_timeout_rd_A	502086640	4118	0	0
check_trigger_regwen_rd_A	502086640	4282	0	0
consistency_check_period_rd_A	502086640	4607	0	0
creator_sw_cfg_read_lock_rd_A	502086640	3808	0	0
direct_access_address_rd_A	502086640	2300	0	0
direct_access_wdata_0_rd_A	502086640	1530	0	0
direct_access_wdata_1_rd_A	502086640	1808	0	0
integrity_check_period_rd_A	502086640	4636	0	0
intr_enable_rd_A	502086640	5394	0	0
owner_sw_cfg_read_lock_rd_A	502086640	3633	0	0
rot_creator_auth_codesign_read_lock_rd_A	502086640	3769	0	0
rot_creator_auth_state_read_lock_rd_A	502086640	3694	0	0
vendor_test_read_lock_rd_A	502086640	3900	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	9134766	0	0
T8	423052	104723	0	0
T13	0	302660	0	0
T14	0	75562	0	0
T16	0	109420	0	0
T17	0	98924	0	0
T18	0	48329	0	0
T19	0	94202	0	0
T27	0	18620	0	0
T68	25227	0	0	0
T70	13177	0	0	0
T106	28317	0	0	0
T107	101830	0	0	0
T108	59404	0	0	0
T109	105074	0	0	0
T145	0	100886	0	0
T169	0	65733	0	0
T172	126950	0	0	0
T173	91641	0	0	0
T283	8053	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	4394	0	0
T14	400725	107	0	0
T18	0	72	0	0
T20	0	345	0	0
T73	0	33	0	0
T180	18436	0	0	0
T204	10285	0	0	0
T205	10452	0	0	0
T206	9467	0	0	0
T270	0	81	0	0
T284	0	119	0	0
T320	0	35	0	0
T348	0	21	0	0
T349	0	165	0	0
T350	0	41	0	0
T351	15825	0	0	0
T352	16897	0	0	0
T353	23038	0	0	0
T354	21275	0	0	0
T355	25230	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	4118	0	0
T14	400725	110	0	0
T18	0	80	0	0
T20	0	303	0	0
T73	0	14	0	0
T180	18436	0	0	0
T204	10285	0	0	0
T205	10452	0	0	0
T206	9467	0	0	0
T270	0	43	0	0
T284	0	161	0	0
T320	0	36	0	0
T348	0	34	0	0
T349	0	215	0	0
T350	0	49	0	0
T351	15825	0	0	0
T352	16897	0	0	0
T353	23038	0	0	0
T354	21275	0	0	0
T355	25230	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	4282	0	0
T14	400725	96	0	0
T18	0	86	0	0
T20	0	230	0	0
T73	0	34	0	0
T180	18436	0	0	0
T204	10285	0	0	0
T205	10452	0	0	0
T206	9467	0	0	0
T270	0	43	0	0
T284	0	79	0	0
T320	0	9	0	0
T348	0	54	0	0
T349	0	213	0	0
T350	0	51	0	0
T351	15825	0	0	0
T352	16897	0	0	0
T353	23038	0	0	0
T354	21275	0	0	0
T355	25230	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	4607	0	0
T14	400725	86	0	0
T18	0	85	0	0
T20	0	310	0	0
T73	0	27	0	0
T180	18436	0	0	0
T204	10285	0	0	0
T205	10452	0	0	0
T206	9467	0	0	0
T270	0	52	0	0
T284	0	106	0	0
T320	0	21	0	0
T348	0	92	0	0
T349	0	191	0	0
T350	0	29	0	0
T351	15825	0	0	0
T352	16897	0	0	0
T353	23038	0	0	0
T354	21275	0	0	0
T355	25230	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	3808	0	0
T14	400725	103	0	0
T18	0	60	0	0
T20	0	279	0	0
T73	0	27	0	0
T180	18436	0	0	0
T204	10285	0	0	0
T205	10452	0	0	0
T206	9467	0	0	0
T270	0	75	0	0
T284	0	113	0	0
T320	0	43	0	0
T348	0	43	0	0
T349	0	198	0	0
T350	0	29	0	0
T351	15825	0	0	0
T352	16897	0	0	0
T353	23038	0	0	0
T354	21275	0	0	0
T355	25230	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	2300	0	0
T14	400725	119	0	0
T18	0	69	0	0
T20	0	218	0	0
T73	0	52	0	0
T180	18436	0	0	0
T204	10285	0	0	0
T205	10452	0	0	0
T206	9467	0	0	0
T270	0	59	0	0
T284	0	120	0	0
T320	0	49	0	0
T348	0	72	0	0
T349	0	212	0	0
T350	0	45	0	0
T351	15825	0	0	0
T352	16897	0	0	0
T353	23038	0	0	0
T354	21275	0	0	0
T355	25230	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	1530	0	0
T14	400725	84	0	0
T18	0	69	0	0
T20	0	240	0	0
T73	0	29	0	0
T180	18436	0	0	0
T204	10285	0	0	0
T205	10452	0	0	0
T206	9467	0	0	0
T270	0	11	0	0
T284	0	72	0	0
T320	0	4	0	0
T348	0	49	0	0
T349	0	147	0	0
T350	0	18	0	0
T351	15825	0	0	0
T352	16897	0	0	0
T353	23038	0	0	0
T354	21275	0	0	0
T355	25230	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	1808	0	0
T14	400725	83	0	0
T18	0	61	0	0
T20	0	217	0	0
T73	0	11	0	0
T180	18436	0	0	0
T204	10285	0	0	0
T205	10452	0	0	0
T206	9467	0	0	0
T270	0	16	0	0
T284	0	59	0	0
T320	0	21	0	0
T348	0	39	0	0
T349	0	152	0	0
T350	0	3	0	0
T351	15825	0	0	0
T352	16897	0	0	0
T353	23038	0	0	0
T354	21275	0	0	0
T355	25230	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	4636	0	0
T14	400725	129	0	0
T18	0	76	0	0
T20	0	337	0	0
T73	0	30	0	0
T180	18436	0	0	0
T204	10285	0	0	0
T205	10452	0	0	0
T206	9467	0	0	0
T270	0	44	0	0
T284	0	90	0	0
T320	0	13	0	0
T348	0	45	0	0
T349	0	173	0	0
T350	0	51	0	0
T351	15825	0	0	0
T352	16897	0	0	0
T353	23038	0	0	0
T354	21275	0	0	0
T355	25230	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	5394	0	0
T14	0	167	0	0
T15	493186	16	0	0
T18	0	94	0	0
T39	20114	0	0	0
T110	205467	0	0	0
T111	72274	0	0	0
T147	0	17	0	0
T155	22246	0	0	0
T174	15922	0	0	0
T175	106737	0	0	0
T177	84549	0	0	0
T218	18360	0	0	0
T219	4240	0	0	0
T270	0	33	0	0
T284	0	71	0	0
T320	0	74	0	0
T348	0	32	0	0
T349	0	226	0	0
T356	0	42	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	3633	0	0
T14	400725	85	0	0
T18	0	65	0	0
T20	0	284	0	0
T73	0	23	0	0
T180	18436	0	0	0
T204	10285	0	0	0
T205	10452	0	0	0
T206	9467	0	0	0
T270	0	17	0	0
T284	0	107	0	0
T320	0	25	0	0
T348	0	40	0	0
T349	0	185	0	0
T350	0	34	0	0
T351	15825	0	0	0
T352	16897	0	0	0
T353	23038	0	0	0
T354	21275	0	0	0
T355	25230	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	3769	0	0
T14	400725	109	0	0
T18	0	64	0	0
T20	0	270	0	0
T73	0	29	0	0
T180	18436	0	0	0
T204	10285	0	0	0
T205	10452	0	0	0
T206	9467	0	0	0
T270	0	72	0	0
T284	0	79	0	0
T320	0	12	0	0
T348	0	94	0	0
T349	0	176	0	0
T350	0	36	0	0
T351	15825	0	0	0
T352	16897	0	0	0
T353	23038	0	0	0
T354	21275	0	0	0
T355	25230	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	3694	0	0
T14	400725	123	0	0
T18	0	38	0	0
T20	0	244	0	0
T73	0	40	0	0
T180	18436	0	0	0
T204	10285	0	0	0
T205	10452	0	0	0
T206	9467	0	0	0
T270	0	81	0	0
T284	0	125	0	0
T320	0	19	0	0
T348	0	35	0	0
T349	0	198	0	0
T350	0	51	0	0
T351	15825	0	0	0
T352	16897	0	0	0
T353	23038	0	0	0
T354	21275	0	0	0
T355	25230	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	502086640	3900	0	0
T14	400725	107	0	0
T18	0	108	0	0
T20	0	314	0	0
T73	0	42	0	0
T180	18436	0	0	0
T204	10285	0	0	0
T205	10452	0	0	0
T206	9467	0	0	0
T270	0	70	0	0
T284	0	97	0	0
T320	0	31	0	0
T348	0	78	0	0
T349	0	174	0	0
T350	0	35	0	0
T351	15825	0	0	0
T352	16897	0	0	0
T353	23038	0	0	0
T354	21275	0	0	0
T355	25230	0	0	0