Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.92	98.05	96.15	96.77		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.92	98.05	96.15	96.77		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.92	98.05	96.15	96.77		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T4
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T178,T179
1	Covered	T178,T179

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T35

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T35

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T225,T226
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T222,T227,T228
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T9,T11,T35
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T78,T79,T80
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T9,T11,T35
CheckFailError	317	Covered	T178,T179
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T9,T7,T8
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T11,T35,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T178,T179
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T9,T11,T35
NoError->CheckFailError	317	Covered	T178,T179
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T36,T108,T111
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T9,T11,T35
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T178,T179
1	0	Covered	T178,T179
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	498920493	498060351	0	0
DigestKnown_A	498920493	498060351	0	0
DigestOffsetMustBeRepresentable_A	1151	1151	0	0
EccErrorState_A	498920493	5750	0	0
ErrorKnown_A	498920493	498060351	0	0
FsmStateKnown_A	498920493	498060351	0	0
InitDoneKnown_A	498920493	498060351	0	0
InitReadLocksPartition_A	498920493	110893880	0	0
InitWriteLocksPartition_A	498920493	110893880	0	0
OffsetMustBeBlockAligned_A	1151	1151	0	0
OtpAddrKnown_A	498920493	498060351	0	0
OtpCmdKnown_A	498920493	498060351	0	0
OtpErrorState_A	498920493	0	0	0
OtpReqKnown_A	498920493	498060351	0	0
OtpSizeKnown_A	498920493	498060351	0	0
OtpWdataKnown_A	498920493	498060351	0	0
ReadLockPropagation_A	498920493	223006348	0	0
SizeMustBeBlockAligned_A	1151	1151	0	0
TlulGntKnown_A	498920493	498060351	0	0
TlulRdataKnown_A	498920493	498060351	0	0
TlulReadOnReadLock_A	498920493	7964	0	0
TlulRerrorKnown_A	498920493	498060351	0	0
TlulRvalidKnown_A	498920493	498060351	0	0
WriteLockPropagation_A	498920493	2271658	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	498920493	26953924	0	0
u_state_regs_A	498920493	498060351	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	5750	0	0
T178	10547	2516	0	0
T179	0	3234	0	0
T195	15671	0	0	0
T196	10909	0	0	0
T197	10408	0	0	0
T198	14187	0	0	0
T199	255615	0	0	0
T200	12550	0	0	0
T201	12074	0	0	0
T202	55437	0	0	0
T203	18722	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	110893880	0	0
T1	209126	121152	0	0
T2	79202	20388	0	0
T3	34948	27422	0	0
T4	16057	4803	0	0
T5	80638	14054	0	0
T6	33328	26127	0	0
T9	29554	17979	0	0
T10	43932	354	0	0
T11	101956	7109	0	0
T12	26927	19858	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	110893880	0	0
T1	209126	121152	0	0
T2	79202	20388	0	0
T3	34948	27422	0	0
T4	16057	4803	0	0
T5	80638	14054	0	0
T6	33328	26127	0	0
T9	29554	17979	0	0
T10	43932	354	0	0
T11	101956	7109	0	0
T12	26927	19858	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	223006348	0	0
T1	209126	25055	0	0
T2	79202	2473	0	0
T3	34948	29017	0	0
T4	16057	0	0	0
T5	80638	2167	0	0
T6	33328	26092	0	0
T7	0	117215	0	0
T9	29554	22021	0	0
T10	43932	0	0	0
T11	101956	8051	0	0
T12	26927	0	0	0
T35	0	8116	0	0
T120	0	5953	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	7964	0	0
T1	209126	17	0	0
T2	79202	2	0	0
T3	34948	22	0	0
T4	16057	0	0	0
T5	80638	0	0	0
T6	33328	19	0	0
T9	29554	5	0	0
T10	43932	0	0	0
T11	101956	2	0	0
T12	26927	27	0	0
T35	0	4	0	0
T115	0	3	0	0
T120	0	9	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	2271658	0	0
T6	33328	0	0	0
T11	101956	16433	0	0
T12	26927	0	0	0
T15	0	9529	0	0
T30	14030	0	0	0
T35	46418	5631	0	0
T36	0	2771	0	0
T78	0	40569	0	0
T107	0	7928	0	0
T109	0	7536	0	0
T110	0	43364	0	0
T111	0	3182	0	0
T113	11814	0	0	0
T114	15842	0	0	0
T115	44559	0	0	0
T116	39347	0	0	0
T120	11607	0	0	0
T155	0	10494	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	26953924	0	0
T5	80638	0	0	0
T6	33328	0	0	0
T9	29554	3761	0	0
T10	43932	0	0	0
T11	101956	80105	0	0
T12	26927	0	0	0
T35	46418	32514	0	0
T36	0	44370	0	0
T70	0	2648	0	0
T71	0	3510	0	0
T107	0	87255	0	0
T109	0	95323	0	0
T113	11814	0	0	0
T114	15842	0	0	0
T115	44559	0	0	0
T120	0	2479	0	0
T157	0	3151	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T43,T180,T44

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T10
1	Covered	T11,T115,T181

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T79,T164,T178
1	Covered	T79,T164,T178

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T10

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T10

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T10
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T4,T10
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T11

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T11

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T4,T10
ReadWaitSt	252	Covered	T2,T4,T10
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T2,T4,T10
InitSt->ErrorSt	315	Covered	T222,T227,T225
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T70,T72,T204
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T11,T35
ReadSt->ReadWaitSt	252	Covered	T2,T4,T10
ReadWaitSt->ErrorSt	276	Covered	T216,T229,T230
ReadWaitSt->IdleSt	270	Covered	T2,T4,T10
ResetSt->ErrorSt	315	Covered	T78,T79,T80
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T11,T35
CheckFailError	317	Covered	T79,T164,T178
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T11,T115,T43
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T7,T8,T174
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T11,T35
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T79,T164,T178
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T115,T43,T180
MacroEccCorrError->NoError	235	Covered	T11,T216,T229
NoError->AccessError	256	Covered	T2,T11,T35
NoError->CheckFailError	317	Covered	T79,T164,T178
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T11,T115,T43

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T10

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T10

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T43,T180,T44
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T70,T72,T204
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T4,T10
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T4,T10
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T36,T8,T108
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T11,T35
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T11,T115,T181
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T4,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T216,T229,T230
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T4,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T79,T164,T178
1	0	Covered	T79,T164,T178
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	498920493	498060351	0	0
DigestKnown_A	498920493	498060351	0	0
DigestOffsetMustBeRepresentable_A	1151	1151	0	0
EccErrorState_A	498920493	11972	0	0
ErrorKnown_A	498920493	498060351	0	0
FsmStateKnown_A	498920493	498060351	0	0
InitDoneKnown_A	498920493	498060351	0	0
InitReadLocksPartition_A	498920493	111076707	0	0
InitWriteLocksPartition_A	498920493	111076707	0	0
OffsetMustBeBlockAligned_A	1151	1151	0	0
OtpAddrKnown_A	498920493	498060351	0	0
OtpCmdKnown_A	498920493	498060351	0	0
OtpErrorState_A	498920493	63	0	0
OtpReqKnown_A	498920493	498060351	0	0
OtpSizeKnown_A	498920493	498060351	0	0
OtpWdataKnown_A	498920493	498060351	0	0
ReadLockPropagation_A	498920493	226907846	0	0
SizeMustBeBlockAligned_A	1151	1151	0	0
TlulGntKnown_A	498920493	498060351	0	0
TlulRdataKnown_A	498920493	498060351	0	0
TlulReadOnReadLock_A	498920493	8062	0	0
TlulRerrorKnown_A	498920493	498060351	0	0
TlulRvalidKnown_A	498920493	498060351	0	0
WriteLockPropagation_A	498920493	2511746	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	498920493	26096014	0	0
u_state_regs_A	498920493	498060351	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	11972	0	0
T79	11612	2231	0	0
T80	9805	0	0	0
T164	0	3991	0	0
T178	0	2516	0	0
T179	0	3234	0	0
T187	7512	0	0	0
T188	28143	0	0	0
T189	20153	0	0	0
T190	27107	0	0	0
T191	20097	0	0	0
T192	9319	0	0	0
T193	144311	0	0	0
T194	10037	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	111076707	0	0
T1	209126	121441	0	0
T2	79202	20609	0	0
T3	34948	27456	0	0
T4	16057	4854	0	0
T5	80638	14241	0	0
T6	33328	26161	0	0
T9	29554	18047	0	0
T10	43932	422	0	0
T11	101956	7347	0	0
T12	26927	19926	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	111076707	0	0
T1	209126	121441	0	0
T2	79202	20609	0	0
T3	34948	27456	0	0
T4	16057	4854	0	0
T5	80638	14241	0	0
T6	33328	26161	0	0
T9	29554	18047	0	0
T10	43932	422	0	0
T11	101956	7347	0	0
T12	26927	19926	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	63	0	0
T15	493186	0	0	0
T70	13177	1	0	0
T71	13293	0	0	0
T72	0	1	0	0
T109	105074	0	0	0
T172	126950	0	0	0
T173	91641	0	0	0
T174	15922	0	0	0
T175	106737	0	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T211	0	1	0	0
T212	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0
T216	0	1	0	0
T218	18360	0	0	0
T219	4240	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	226907846	0	0
T1	209126	12379	0	0
T2	79202	7672	0	0
T3	34948	29402	0	0
T4	16057	0	0	0
T5	80638	6278	0	0
T6	33328	26090	0	0
T7	0	117200	0	0
T9	29554	19132	0	0
T10	43932	0	0	0
T11	101956	12918	0	0
T12	26927	0	0	0
T35	0	6120	0	0
T157	0	23666	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	8062	0	0
T1	209126	18	0	0
T2	79202	2	0	0
T3	34948	21	0	0
T4	16057	0	0	0
T5	80638	0	0	0
T6	33328	18	0	0
T9	29554	3	0	0
T10	43932	0	0	0
T11	101956	3	0	0
T12	26927	17	0	0
T35	0	4	0	0
T115	0	3	0	0
T120	0	15	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	2511746	0	0
T6	33328	0	0	0
T11	101956	5921	0	0
T12	26927	0	0	0
T15	0	43060	0	0
T30	14030	0	0	0
T35	46418	3018	0	0
T36	0	1165	0	0
T78	0	11921	0	0
T108	0	6459	0	0
T109	0	3108	0	0
T110	0	15752	0	0
T111	0	3572	0	0
T113	11814	0	0	0
T114	15842	0	0	0
T115	44559	0	0	0
T116	39347	0	0	0
T120	11607	0	0	0
T155	0	10494	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	26096014	0	0
T2	79202	62082	0	0
T3	34948	0	0	0
T4	16057	0	0	0
T5	80638	49384	0	0
T6	33328	0	0	0
T9	29554	0	0	0
T10	43932	0	0	0
T11	101956	79901	0	0
T12	26927	0	0	0
T15	0	152469	0	0
T35	0	32395	0	0
T36	0	36031	0	0
T70	0	2643	0	0
T107	0	87068	0	0
T108	0	48701	0	0
T109	0	95136	0	0
T113	11814	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T182,T24,T183

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T11,T115,T177

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T79,T165,T179
1	Covered	T79,T165,T179

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T35

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T35

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T2,T4,T5
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T222,T227,T225
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T70,T71,T72
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T11
ReadSt->ReadWaitSt	252	Covered	T2,T4,T5
ReadWaitSt->ErrorSt	276	Covered	T177,T186,T216
ReadWaitSt->IdleSt	270	Covered	T2,T4,T5
ResetSt->ErrorSt	315	Covered	T78,T79,T80
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T11
CheckFailError	317	Covered	T79,T165,T179
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T11,T115,T177
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T1,T8,T172
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T2,T11
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T79,T165,T179
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T115,T177,T182
MacroEccCorrError->NoError	235	Covered	T11,T69,T81
NoError->AccessError	256	Covered	T1,T2,T11
NoError->CheckFailError	317	Covered	T79,T165,T179
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T11,T115,T177

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T182,T24,T183
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T71,T180,T207
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T4,T5
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T36,T108,T111
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T11,T115,T177
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T177,T186,T216
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T79,T165,T179
1	0	Covered	T79,T165,T179
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	498920493	498060351	0	0
DigestKnown_A	498920493	498060351	0	0
DigestOffsetMustBeRepresentable_A	1151	1151	0	0
EccErrorState_A	498920493	9061	0	0
ErrorKnown_A	498920493	498060351	0	0
FsmStateKnown_A	498920493	498060351	0	0
InitDoneKnown_A	498920493	498060351	0	0
InitReadLocksPartition_A	498920493	111258416	0	0
InitWriteLocksPartition_A	498920493	111258416	0	0
OffsetMustBeBlockAligned_A	1151	1151	0	0
OtpAddrKnown_A	498920493	498060351	0	0
OtpCmdKnown_A	498920493	498060351	0	0
OtpErrorState_A	498920493	60	0	0
OtpReqKnown_A	498920493	498060351	0	0
OtpSizeKnown_A	498920493	498060351	0	0
OtpWdataKnown_A	498920493	498060351	0	0
ReadLockPropagation_A	498920493	224604721	0	0
SizeMustBeBlockAligned_A	1151	1151	0	0
TlulGntKnown_A	498920493	498060351	0	0
TlulRdataKnown_A	498920493	498060351	0	0
TlulReadOnReadLock_A	498920493	8198	0	0
TlulRerrorKnown_A	498920493	498060351	0	0
TlulRvalidKnown_A	498920493	498060351	0	0
WriteLockPropagation_A	498920493	1464865	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	498920493	16742412	0	0
u_state_regs_A	498920493	498060351	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	9061	0	0
T79	11612	2231	0	0
T80	9805	0	0	0
T165	0	3596	0	0
T179	0	3234	0	0
T187	7512	0	0	0
T188	28143	0	0	0
T189	20153	0	0	0
T190	27107	0	0	0
T191	20097	0	0	0
T192	9319	0	0	0
T193	144311	0	0	0
T194	10037	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	111258416	0	0
T1	209126	121730	0	0
T2	79202	20830	0	0
T3	34948	27490	0	0
T4	16057	4905	0	0
T5	80638	14423	0	0
T6	33328	26195	0	0
T9	29554	18115	0	0
T10	43932	490	0	0
T11	101956	7585	0	0
T12	26927	19994	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	111258416	0	0
T1	209126	121730	0	0
T2	79202	20830	0	0
T3	34948	27490	0	0
T4	16057	4905	0	0
T5	80638	14423	0	0
T6	33328	26195	0	0
T9	29554	18115	0	0
T10	43932	490	0	0
T11	101956	7585	0	0
T12	26927	19994	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	60	0	0
T15	493186	0	0	0
T71	13293	1	0	0
T110	205467	0	0	0
T111	72274	0	0	0
T155	22246	0	0	0
T174	15922	0	0	0
T175	106737	0	0	0
T177	84549	1	0	0
T180	0	1	0	0
T186	0	2	0	0
T207	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0
T213	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0
T218	18360	0	0	0
T219	4240	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	224604721	0	0
T1	209126	25033	0	0
T2	79202	6480	0	0
T3	34948	29400	0	0
T4	16057	0	0	0
T5	80638	5297	0	0
T6	33328	0	0	0
T8	0	336634	0	0
T9	29554	22014	0	0
T10	43932	0	0	0
T11	101956	8872	0	0
T12	26927	0	0	0
T35	0	7969	0	0
T36	0	6739	0	0
T157	0	24265	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	8198	0	0
T1	209126	20	0	0
T2	79202	6	0	0
T3	34948	33	0	0
T4	16057	0	0	0
T5	80638	0	0	0
T6	33328	24	0	0
T9	29554	4	0	0
T10	43932	0	0	0
T11	101956	2	0	0
T12	26927	18	0	0
T35	0	4	0	0
T115	0	5	0	0
T120	0	20	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	1464865	0	0
T6	33328	0	0	0
T11	101956	13473	0	0
T12	26927	0	0	0
T15	0	20395	0	0
T30	14030	0	0	0
T35	46418	3224	0	0
T36	0	1165	0	0
T78	0	32543	0	0
T107	0	17078	0	0
T108	0	5971	0	0
T109	0	7470	0	0
T112	0	9645	0	0
T113	11814	0	0	0
T114	15842	0	0	0
T115	44559	0	0	0
T116	39347	0	0	0
T118	0	4125	0	0
T120	11607	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	16742412	0	0
T5	80638	0	0	0
T6	33328	0	0	0
T9	29554	3693	0	0
T10	43932	0	0	0
T11	101956	79697	0	0
T12	26927	0	0	0
T35	46418	32276	0	0
T36	0	44064	0	0
T71	0	3488	0	0
T107	0	86881	0	0
T108	0	48514	0	0
T109	0	94949	0	0
T113	11814	0	0	0
T114	15842	0	0	0
T115	44559	0	0	0
T120	0	2445	0	0
T157	0	3083	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498920493	498060351	0	0
T1	209126	207626	0	0
T2	79202	78130	0	0
T3	34948	34680	0	0
T4	16057	15789	0	0
T5	80638	79798	0	0
T6	33328	33040	0	0
T9	29554	29317	0	0
T10	43932	43437	0	0
T11	101956	100892	0	0
T12	26927	26661	0	0