Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

26219899

1

T1

6717

T2

818

T3

1280

full_word

8558751

1

T1

4954

T2

681

T3

246

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34778370	1			T1	11671		T2	1499		T3	1526
auto[TlIntgErrCmd]	85	1			T268	4		T269	3		T270	2
auto[TlIntgErrData]	103	1			T268	9		T269	2		T270	4
auto[TlIntgErrBoth]	92	1			T268	7		T269	5		T270	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9785991

1

T1

10506

T2

1258

T3

1247

auto[1]

24992659

1

T1

1165

T2

241

T3

279

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6145212	1			T1	5980		T2	691		T3	1110
auto[TlIntgErrNone]	partial	auto[1]	20074434	1			T1	737		T2	127		T3	170
auto[TlIntgErrNone]	full_word	auto[0]	3640660	1			T1	4526		T2	567		T3	137
auto[TlIntgErrNone]	full_word	auto[1]	4918064	1			T1	428		T2	114		T3	109
auto[TlIntgErrCmd]	partial	auto[0]	24	1			T365	1		T277	1		T370	4
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T268	3		T269	3		T270	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T268	1		T370	1		T369	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T270	1		T277	1		T368	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T268	5		T269	2		T270	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T268	3		T270	1		T365	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T268	1		T370	3		T371	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T277	1		T372	1		T373	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T268	1		T269	2		T270	2
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T268	4		T269	3		T270	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T277	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T268	2		T270	1		T368	2