Unified Coverage Report :: Module :: prim_lfsr

Module : prim_lfsr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.49			73.49

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr	73.49			73.49
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr	73.49			73.49

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.49			73.49

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.49			73.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_double_lfsr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.49			73.49

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.49			73.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_double_lfsr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	122	73.49
Total Bits 0->1	83	61	73.49
Total Bits 1->0	83	61	73.49

Ports	5	4	80.00
Port Bits	166	122	73.49
Port Bits 0->1	83	61	73.49
Port Bits 1->0	83	61	73.49

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[0]	No	No		No		INPUT
entropy_i[1]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[2]	No	No		No		INPUT
entropy_i[3]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[5:4]	No	No		No		INPUT
entropy_i[6]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[7]	No	No		No		INPUT
entropy_i[8]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[9]	No	No		No		INPUT
entropy_i[10]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[11]	No	No		No		INPUT
entropy_i[12]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[13]	No	No		No		INPUT
entropy_i[15:14]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[19:16]	No	No		No		INPUT
entropy_i[20]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[23:21]	No	No		No		INPUT
entropy_i[27:24]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[29:28]	No	No		No		INPUT
entropy_i[31:30]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[33:32]	No	No		No		INPUT
entropy_i[35:34]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[38:36]	No	No		No		INPUT
entropy_i[39]	Yes	Yes	T5	Yes	T5	INPUT
state_o[39:0]	Yes	Yes	T1,T6,T4	Yes	T1,T6,T4	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	122	73.49
Total Bits 0->1	83	61	73.49
Total Bits 1->0	83	61	73.49

Ports	5	4	80.00
Port Bits	166	122	73.49
Port Bits 0->1	83	61	73.49
Port Bits 1->0	83	61	73.49

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[0]	No	No		No		INPUT
entropy_i[1]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[2]	No	No		No		INPUT
entropy_i[3]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[5:4]	No	No		No		INPUT
entropy_i[6]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[7]	No	No		No		INPUT
entropy_i[8]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[9]	No	No		No		INPUT
entropy_i[10]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[11]	No	No		No		INPUT
entropy_i[12]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[13]	No	No		No		INPUT
entropy_i[15:14]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[19:16]	No	No		No		INPUT
entropy_i[20]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[23:21]	No	No		No		INPUT
entropy_i[27:24]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[29:28]	No	No		No		INPUT
entropy_i[31:30]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[33:32]	No	No		No		INPUT
entropy_i[35:34]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[38:36]	No	No		No		INPUT
entropy_i[39]	Yes	Yes	T5	Yes	T5	INPUT
state_o[39:0]	Yes	Yes	T1,T6,T4	Yes	T1,T6,T4	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	166	122	73.49
Total Bits 0->1	83	61	73.49
Total Bits 1->0	83	61	73.49

Ports	5	4	80.00
Port Bits	166	122	73.49
Port Bits 0->1	83	61	73.49
Port Bits 1->0	83	61	73.49

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Unreachable	Unreachable		Unreachable		INPUT
seed_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[0]	No	No		No		INPUT
entropy_i[1]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[2]	No	No		No		INPUT
entropy_i[3]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[5:4]	No	No		No		INPUT
entropy_i[6]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[7]	No	No		No		INPUT
entropy_i[8]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[9]	No	No		No		INPUT
entropy_i[10]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[11]	No	No		No		INPUT
entropy_i[12]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[13]	No	No		No		INPUT
entropy_i[15:14]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[19:16]	No	No		No		INPUT
entropy_i[20]	Yes	Yes	*T5	Yes	T5	INPUT
entropy_i[23:21]	No	No		No		INPUT
entropy_i[27:24]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[29:28]	No	No		No		INPUT
entropy_i[31:30]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[33:32]	No	No		No		INPUT
entropy_i[35:34]	Yes	Yes	T5	Yes	T5	INPUT
entropy_i[38:36]	No	No		No		INPUT
entropy_i[39]	Yes	Yes	T5	Yes	T5	INPUT
state_o[39:0]	Yes	Yes	T1,T6,T4	Yes	T1,T6,T4	OUTPUT

*Tests covering at least one bit in the range