Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.58	96.10	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	495321076	8489906	0	0
check_regwen_rd_A	495321076	3117	0	0
check_timeout_rd_A	495321076	2767	0	0
check_trigger_regwen_rd_A	495321076	3255	0	0
consistency_check_period_rd_A	495321076	3509	0	0
creator_sw_cfg_read_lock_rd_A	495321076	2919	0	0
direct_access_address_rd_A	495321076	1938	0	0
direct_access_wdata_0_rd_A	495321076	1363	0	0
direct_access_wdata_1_rd_A	495321076	1516	0	0
integrity_check_period_rd_A	495321076	3115	0	0
intr_enable_rd_A	495321076	3934	0	0
owner_sw_cfg_read_lock_rd_A	495321076	2674	0	0
rot_creator_auth_codesign_read_lock_rd_A	495321076	2673	0	0
rot_creator_auth_state_read_lock_rd_A	495321076	2768	0	0
vendor_test_read_lock_rd_A	495321076	2589	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	8489906	0	0
T4	160632	48690	0	0
T7	18536	0	0	0
T8	0	194209	0	0
T10	24066	0	0	0
T11	70022	0	0	0
T12	80499	0	0	0
T13	9808	0	0	0
T14	0	98280	0	0
T15	0	143532	0	0
T17	0	81299	0	0
T34	35950	0	0	0
T36	0	82496	0	0
T47	13074	0	0	0
T70	11251	0	0	0
T78	16885	0	0	0
T117	0	43397	0	0
T141	0	184427	0	0
T274	0	244410	0	0
T278	0	195658	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	3117	0	0
T19	0	61	0	0
T122	11542	0	0	0
T207	9969	0	0	0
T220	15027	0	0	0
T251	106813	60	0	0
T252	0	51	0	0
T253	0	135	0	0
T266	27858	0	0	0
T282	0	163	0	0
T304	0	133	0	0
T334	0	105	0	0
T335	0	211	0	0
T336	0	39	0	0
T337	0	87	0	0
T338	100576	0	0	0
T339	12929	0	0	0
T340	13647	0	0	0
T341	27527	0	0	0
T342	131988	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	2767	0	0
T19	0	40	0	0
T122	11542	0	0	0
T207	9969	0	0	0
T220	15027	0	0	0
T251	106813	57	0	0
T252	0	76	0	0
T253	0	168	0	0
T266	27858	0	0	0
T282	0	129	0	0
T304	0	105	0	0
T334	0	92	0	0
T335	0	235	0	0
T336	0	50	0	0
T337	0	86	0	0
T338	100576	0	0	0
T339	12929	0	0	0
T340	13647	0	0	0
T341	27527	0	0	0
T342	131988	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	3255	0	0
T19	0	55	0	0
T122	11542	0	0	0
T207	9969	0	0	0
T220	15027	0	0	0
T251	106813	53	0	0
T252	0	40	0	0
T253	0	105	0	0
T266	27858	0	0	0
T282	0	134	0	0
T304	0	130	0	0
T334	0	158	0	0
T335	0	166	0	0
T336	0	58	0	0
T337	0	70	0	0
T338	100576	0	0	0
T339	12929	0	0	0
T340	13647	0	0	0
T341	27527	0	0	0
T342	131988	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	3509	0	0
T19	0	60	0	0
T122	11542	0	0	0
T207	9969	0	0	0
T220	15027	0	0	0
T251	106813	76	0	0
T252	0	118	0	0
T253	0	243	0	0
T266	27858	0	0	0
T282	0	131	0	0
T304	0	141	0	0
T334	0	198	0	0
T335	0	179	0	0
T336	0	41	0	0
T337	0	67	0	0
T338	100576	0	0	0
T339	12929	0	0	0
T340	13647	0	0	0
T341	27527	0	0	0
T342	131988	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	2919	0	0
T19	0	42	0	0
T122	11542	0	0	0
T207	9969	0	0	0
T220	15027	0	0	0
T251	106813	44	0	0
T252	0	92	0	0
T253	0	176	0	0
T266	27858	0	0	0
T282	0	144	0	0
T304	0	145	0	0
T334	0	155	0	0
T335	0	217	0	0
T336	0	34	0	0
T337	0	49	0	0
T338	100576	0	0	0
T339	12929	0	0	0
T340	13647	0	0	0
T341	27527	0	0	0
T342	131988	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	1938	0	0
T19	0	75	0	0
T122	11542	0	0	0
T207	9969	0	0	0
T220	15027	0	0	0
T251	106813	82	0	0
T252	0	57	0	0
T253	0	193	0	0
T266	27858	0	0	0
T282	0	115	0	0
T304	0	156	0	0
T334	0	135	0	0
T335	0	194	0	0
T336	0	41	0	0
T337	0	66	0	0
T338	100576	0	0	0
T339	12929	0	0	0
T340	13647	0	0	0
T341	27527	0	0	0
T342	131988	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	1363	0	0
T19	0	23	0	0
T122	11542	0	0	0
T207	9969	0	0	0
T220	15027	0	0	0
T251	106813	77	0	0
T252	0	64	0	0
T253	0	125	0	0
T266	27858	0	0	0
T282	0	100	0	0
T304	0	70	0	0
T334	0	55	0	0
T335	0	145	0	0
T336	0	43	0	0
T337	0	37	0	0
T338	100576	0	0	0
T339	12929	0	0	0
T340	13647	0	0	0
T341	27527	0	0	0
T342	131988	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	1516	0	0
T19	0	32	0	0
T122	11542	0	0	0
T207	9969	0	0	0
T220	15027	0	0	0
T251	106813	31	0	0
T252	0	62	0	0
T253	0	166	0	0
T266	27858	0	0	0
T282	0	107	0	0
T304	0	118	0	0
T334	0	94	0	0
T335	0	144	0	0
T336	0	29	0	0
T337	0	72	0	0
T338	100576	0	0	0
T339	12929	0	0	0
T340	13647	0	0	0
T341	27527	0	0	0
T342	131988	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	3115	0	0
T19	0	64	0	0
T122	11542	0	0	0
T207	9969	0	0	0
T220	15027	0	0	0
T251	106813	32	0	0
T252	0	59	0	0
T253	0	179	0	0
T266	27858	0	0	0
T282	0	105	0	0
T304	0	146	0	0
T334	0	110	0	0
T335	0	172	0	0
T336	0	33	0	0
T337	0	54	0	0
T338	100576	0	0	0
T339	12929	0	0	0
T340	13647	0	0	0
T341	27527	0	0	0
T342	131988	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	3934	0	0
T17	451200	0	0	0
T76	80955	0	0	0
T79	31975	0	0	0
T168	12367	0	0	0
T225	106754	0	0	0
T232	440016	46	0	0
T251	0	84	0	0
T252	0	38	0	0
T253	0	157	0	0
T282	0	147	0	0
T304	0	172	0	0
T343	0	17	0	0
T344	0	17	0	0
T345	0	44	0	0
T346	0	14	0	0
T347	101129	0	0	0
T348	15432	0	0	0
T349	87382	0	0	0
T350	42118	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	2674	0	0
T19	0	53	0	0
T122	11542	0	0	0
T207	9969	0	0	0
T220	15027	0	0	0
T251	106813	58	0	0
T252	0	91	0	0
T253	0	151	0	0
T266	27858	0	0	0
T282	0	107	0	0
T304	0	120	0	0
T334	0	99	0	0
T335	0	133	0	0
T336	0	45	0	0
T337	0	66	0	0
T338	100576	0	0	0
T339	12929	0	0	0
T340	13647	0	0	0
T341	27527	0	0	0
T342	131988	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	2673	0	0
T19	0	36	0	0
T122	11542	0	0	0
T207	9969	0	0	0
T220	15027	0	0	0
T251	106813	60	0	0
T252	0	59	0	0
T253	0	116	0	0
T266	27858	0	0	0
T282	0	139	0	0
T304	0	124	0	0
T334	0	143	0	0
T335	0	193	0	0
T336	0	76	0	0
T337	0	64	0	0
T338	100576	0	0	0
T339	12929	0	0	0
T340	13647	0	0	0
T341	27527	0	0	0
T342	131988	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	2768	0	0
T19	0	42	0	0
T122	11542	0	0	0
T207	9969	0	0	0
T220	15027	0	0	0
T251	106813	60	0	0
T252	0	91	0	0
T253	0	148	0	0
T266	27858	0	0	0
T282	0	129	0	0
T304	0	155	0	0
T334	0	91	0	0
T335	0	195	0	0
T336	0	29	0	0
T337	0	87	0	0
T338	100576	0	0	0
T339	12929	0	0	0
T340	13647	0	0	0
T341	27527	0	0	0
T342	131988	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495321076	2589	0	0
T19	0	49	0	0
T122	11542	0	0	0
T207	9969	0	0	0
T220	15027	0	0	0
T251	106813	22	0	0
T252	0	97	0	0
T253	0	96	0	0
T266	27858	0	0	0
T282	0	140	0	0
T304	0	150	0	0
T334	0	129	0	0
T335	0	141	0	0
T336	0	44	0	0
T337	0	61	0	0
T338	100576	0	0	0
T339	12929	0	0	0
T340	13647	0	0	0
T341	27527	0	0	0
T342	131988	0	0	0