Module Definition
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Module : tlul_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_core.u_socket.fifo_h 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_core.u_socket.fifo_h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 98.21 100.00 100.00 100.00 u_socket


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
reqfifo 100.00 100.00 100.00
rspfifo 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 98.21 100.00 100.00 100.00 u_socket


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
reqfifo 100.00 100.00 100.00
rspfifo 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 98.21 100.00 100.00 100.00 u_socket


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
reqfifo 100.00 100.00 100.00
rspfifo 100.00 100.00 100.00

Cond Coverage for Module : tlul_fifo_sync
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Module : tlul_fifo_sync
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Cond Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Cond Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT4,T8,T14
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T8,T14

Cond Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

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