Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.58	96.10	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.58	96.10	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.58	96.10	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T3,T6
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T174,T173,T175
1	Covered	T174,T173,T175

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T34,T71

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T34,T71

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T6
ReadWaitSt	252	Covered	T1,T3,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T9
IdleSt->ReadSt	236	Covered	T1,T3,T6
InitSt->ErrorSt	315	Covered	T216,T217,T218
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T115,T219,T220
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T4,T34
ReadSt->ReadWaitSt	252	Covered	T1,T3,T6
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T3,T6
ResetSt->ErrorSt	315	Covered	T79,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T1,T4,T34
CheckFailError	317	Covered	T174,T173,T175
FsmStateError	289	Covered	T2,T3,T9
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T7,T146,T15
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T1,T4,T34
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T174,T173,T175
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T2,T3,T9
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T1,T4,T34
NoError->CheckFailError	317	Covered	T174,T173,T175
NoError->FsmStateError	289	Covered	T2,T3,T9
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T34,T71
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T34,T8,T37
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T34
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T9,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T9,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T174,T173,T175
1	0	Covered	T174,T173,T175
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	492507365	491677277	0	0
DigestKnown_A	492507365	491677277	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	492507365	10470	0	0
ErrorKnown_A	492507365	491677277	0	0
FsmStateKnown_A	492507365	491677277	0	0
InitDoneKnown_A	492507365	491677277	0	0
InitReadLocksPartition_A	492507365	82752738	0	0
InitWriteLocksPartition_A	492507365	82752738	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	492507365	491677277	0	0
OtpCmdKnown_A	492507365	491677277	0	0
OtpErrorState_A	492507365	0	0	0
OtpReqKnown_A	492507365	491677277	0	0
OtpSizeKnown_A	492507365	491677277	0	0
OtpWdataKnown_A	492507365	491677277	0	0
ReadLockPropagation_A	492507365	204452974	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	492507365	491677277	0	0
TlulRdataKnown_A	492507365	491677277	0	0
TlulReadOnReadLock_A	492507365	7757	0	0
TlulRerrorKnown_A	492507365	491677277	0	0
TlulRvalidKnown_A	492507365	491677277	0	0
WriteLockPropagation_A	492507365	2755340	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	492507365	28566685	0	0
u_state_regs_A	492507365	491677277	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	10470	0	0
T74	11443	0	0	0
T139	538658	0	0	0
T173	0	2391	0	0
T174	11241	3203	0	0
T175	0	2330	0	0
T176	0	2546	0	0
T188	31252	0	0	0
T189	44968	0	0	0
T190	17508	0	0	0
T191	14269	0	0	0
T192	988115	0	0	0
T193	136480	0	0	0
T194	21790	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	82752738	0	0
T1	166454	7000	0	0
T2	41374	13238	0	0
T3	12241	4430	0	0
T4	160632	589144	0	0
T6	8621	2941	0	0
T9	50189	41695	0	0
T10	24066	11981	0	0
T11	70022	32109	0	0
T12	80499	73683	0	0
T13	9808	4458	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	82752738	0	0
T1	166454	7000	0	0
T2	41374	13238	0	0
T3	12241	4430	0	0
T4	160632	589144	0	0
T6	8621	2941	0	0
T9	50189	41695	0	0
T10	24066	11981	0	0
T11	70022	32109	0	0
T12	80499	73683	0	0
T13	9808	4458	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	204452974	0	0
T1	166454	57524	0	0
T2	41374	0	0	0
T3	12241	0	0	0
T4	160632	873667	0	0
T6	8621	0	0	0
T7	0	9234	0	0
T8	0	569767	0	0
T9	50189	0	0	0
T10	24066	12541	0	0
T11	70022	0	0	0
T12	80499	0	0	0
T13	9808	0	0	0
T14	0	462749	0	0
T27	0	24006	0	0
T28	0	38841	0	0
T34	0	2959	0	0
T146	0	8960	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	7757	0	0
T1	166454	8	0	0
T2	41374	2	0	0
T3	12241	0	0	0
T4	160632	19	0	0
T6	8621	0	0	0
T7	0	5	0	0
T8	0	25	0	0
T9	50189	13	0	0
T10	24066	7	0	0
T11	70022	4	0	0
T12	80499	10	0	0
T13	9808	0	0	0
T34	0	5	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	2755340	0	0
T1	166454	28477	0	0
T2	41374	0	0	0
T3	12241	0	0	0
T4	160632	0	0	0
T6	8621	0	0	0
T9	50189	0	0	0
T10	24066	0	0	0
T11	70022	0	0	0
T12	80499	0	0	0
T13	9808	0	0	0
T27	0	10346	0	0
T37	0	5628	0	0
T38	0	4659	0	0
T45	0	8560	0	0
T69	0	12484	0	0
T105	0	6292	0	0
T107	0	2594	0	0
T124	0	5464	0	0
T136	0	16181	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	28566685	0	0
T1	166454	136802	0	0
T2	41374	0	0	0
T3	12241	0	0	0
T4	160632	0	0	0
T6	8621	0	0	0
T9	50189	0	0	0
T10	24066	0	0	0
T11	70022	0	0	0
T12	80499	0	0	0
T13	9808	0	0	0
T27	0	54631	0	0
T28	0	95175	0	0
T34	0	27830	0	0
T45	0	39636	0	0
T71	0	2862	0	0
T110	0	17256	0	0
T112	0	10125	0	0
T118	0	6019	0	0
T215	0	2583	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T70,T82

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T119,T68,T124

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T174,T173,T176
1	Covered	T174,T173,T176

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T34

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T34

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T9
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T115,T216,T219
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T125,T179,T199
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T4,T10
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T2,T165,T166
ReadWaitSt->IdleSt	270	Covered	T1,T3,T6
ResetSt->ErrorSt	315	Covered	T79,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T4,T10
CheckFailError	317	Covered	T174,T173,T176
FsmStateError	289	Covered	T2,T3,T9
MacroEccCorrError	221	Covered	T13,T70,T119
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T10,T7,T15
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T4,T10
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T174,T173,T176
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T9
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T13,T70,T119
MacroEccCorrError->NoError	235	Covered	T119,T68,T124
NoError->AccessError	256	Covered	T1,T4,T10
NoError->CheckFailError	317	Covered	T174,T173,T176
NoError->FsmStateError	289	Covered	T2,T3,T9
NoError->MacroEccCorrError	221	Covered	T13,T70,T119

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T34
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T13,T70,T82
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T125,T179,T199
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T4,T34,T37
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T119,T68,T124
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T2,T165,T166
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T9,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T9,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T174,T173,T176
1	0	Covered	T174,T173,T176
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	492507365	491677277	0	0
DigestKnown_A	492507365	491677277	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	492507365	8140	0	0
ErrorKnown_A	492507365	491677277	0	0
FsmStateKnown_A	492507365	491677277	0	0
InitDoneKnown_A	492507365	491677277	0	0
InitReadLocksPartition_A	492507365	82928399	0	0
InitWriteLocksPartition_A	492507365	82928399	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	492507365	491677277	0	0
OtpCmdKnown_A	492507365	491677277	0	0
OtpErrorState_A	492507365	78	0	0
OtpReqKnown_A	492507365	491677277	0	0
OtpSizeKnown_A	492507365	491677277	0	0
OtpWdataKnown_A	492507365	491677277	0	0
ReadLockPropagation_A	492507365	199919224	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	492507365	491677277	0	0
TlulRdataKnown_A	492507365	491677277	0	0
TlulReadOnReadLock_A	492507365	8408	0	0
TlulRerrorKnown_A	492507365	491677277	0	0
TlulRvalidKnown_A	492507365	491677277	0	0
WriteLockPropagation_A	492507365	2766346	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	492507365	29366352	0	0
u_state_regs_A	492507365	491677277	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	8140	0	0
T74	11443	0	0	0
T139	538658	0	0	0
T173	0	2391	0	0
T174	11241	3203	0	0
T176	0	2546	0	0
T188	31252	0	0	0
T189	44968	0	0	0
T190	17508	0	0	0
T191	14269	0	0	0
T192	988115	0	0	0
T193	136480	0	0	0
T194	21790	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	82928399	0	0
T1	166454	7238	0	0
T2	41374	13308	0	0
T3	12241	4464	0	0
T4	160632	589246	0	0
T6	8621	2992	0	0
T9	50189	41746	0	0
T10	24066	12049	0	0
T11	70022	32245	0	0
T12	80499	73734	0	0
T13	9808	4492	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	82928399	0	0
T1	166454	7238	0	0
T2	41374	13308	0	0
T3	12241	4464	0	0
T4	160632	589246	0	0
T6	8621	2992	0	0
T9	50189	41746	0	0
T10	24066	12049	0	0
T11	70022	32245	0	0
T12	80499	73734	0	0
T13	9808	4492	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	78	0	0
T2	41374	1	0	0
T3	12241	0	0	0
T4	160632	0	0	0
T6	8621	0	0	0
T9	50189	0	0	0
T10	24066	0	0	0
T11	70022	0	0	0
T12	80499	0	0	0
T13	9808	0	0	0
T70	11251	0	0	0
T103	0	1	0	0
T125	0	1	0	0
T165	0	2	0	0
T166	0	1	0	0
T179	0	1	0	0
T199	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	199919224	0	0
T1	166454	65671	0	0
T2	41374	0	0	0
T3	12241	0	0	0
T4	160632	70490	0	0
T6	8621	0	0	0
T7	0	9232	0	0
T8	0	569877	0	0
T9	50189	0	0	0
T10	24066	12539	0	0
T11	70022	0	0	0
T12	80499	0	0	0
T13	9808	0	0	0
T14	0	404149	0	0
T27	0	28919	0	0
T28	0	36196	0	0
T34	0	2846	0	0
T112	0	9188	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	8408	0	0
T1	166454	10	0	0
T2	41374	2	0	0
T3	12241	0	0	0
T4	160632	15	0	0
T6	8621	0	0	0
T7	0	6	0	0
T9	50189	16	0	0
T10	24066	20	0	0
T11	70022	7	0	0
T12	80499	25	0	0
T13	9808	0	0	0
T34	0	3	0	0
T78	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	2766346	0	0
T1	166454	14760	0	0
T2	41374	0	0	0
T3	12241	0	0	0
T4	160632	0	0	0
T6	8621	0	0	0
T9	50189	0	0	0
T10	24066	0	0	0
T11	70022	0	0	0
T12	80499	0	0	0
T13	9808	0	0	0
T27	0	10568	0	0
T28	0	18445	0	0
T34	0	848	0	0
T37	0	1326	0	0
T45	0	2019	0	0
T69	0	15920	0	0
T105	0	923	0	0
T106	0	8848	0	0
T107	0	14658	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	29366352	0	0
T1	166454	136581	0	0
T2	41374	0	0	0
T3	12241	0	0	0
T4	160632	0	0	0
T6	8621	0	0	0
T9	50189	0	0	0
T10	24066	3537	0	0
T11	70022	0	0	0
T12	80499	0	0	0
T13	9808	0	0	0
T27	0	54512	0	0
T28	0	94988	0	0
T34	0	27694	0	0
T45	0	44465	0	0
T110	0	17205	0	0
T112	0	10091	0	0
T115	0	2480	0	0
T118	0	5985	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T71,T177,T43

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T119,T178,T165

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T81,T172,T174
1	Covered	T81,T172,T174

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T2,T3,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T34,T28

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T34,T28

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T6
ReadWaitSt	252	Covered	T1,T3,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T9
IdleSt->ReadSt	236	Covered	T1,T3,T6
InitSt->ErrorSt	315	Covered	T115,T216,T219
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T125,T179,T195
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T4,T11
ReadSt->ReadWaitSt	252	Covered	T1,T3,T6
ReadWaitSt->ErrorSt	276	Covered	T221,T222,T223
ReadWaitSt->IdleSt	270	Covered	T1,T3,T6
ResetSt->ErrorSt	315	Covered	T79,T80,T81
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T4,T11
CheckFailError	317	Covered	T81,T172,T174
FsmStateError	289	Covered	T2,T3,T9
MacroEccCorrError	221	Covered	T71,T119,T178
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T11,T7,T146
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T4,T34
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T81,T172,T174
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T9
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T71,T119,T178
MacroEccCorrError->NoError	235	Covered	T119,T51,T224
NoError->AccessError	256	Covered	T1,T4,T11
NoError->CheckFailError	317	Covered	T81,T172,T174
NoError->FsmStateError	289	Covered	T2,T3,T9
NoError->MacroEccCorrError	221	Covered	T71,T119,T178

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T34,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T71,T177,T43
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T195,T196,T197
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T37,T105,T107
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T119,T178,T165
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T221,T222,T223
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T9,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T9,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T81,T172,T174
1	0	Covered	T81,T172,T174
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T9
1	0	Covered	T2,T3,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	492507365	491677277	0	0
DigestKnown_A	492507365	491677277	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	492507365	13968	0	0
ErrorKnown_A	492507365	491677277	0	0
FsmStateKnown_A	492507365	491677277	0	0
InitDoneKnown_A	492507365	491677277	0	0
InitReadLocksPartition_A	492507365	83102684	0	0
InitWriteLocksPartition_A	492507365	83102684	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	492507365	491677277	0	0
OtpCmdKnown_A	492507365	491677277	0	0
OtpErrorState_A	492507365	55	0	0
OtpReqKnown_A	492507365	491677277	0	0
OtpSizeKnown_A	492507365	491677277	0	0
OtpWdataKnown_A	492507365	491677277	0	0
ReadLockPropagation_A	492507365	205475519	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	492507365	491677277	0	0
TlulRdataKnown_A	492507365	491677277	0	0
TlulReadOnReadLock_A	492507365	8278	0	0
TlulRerrorKnown_A	492507365	491677277	0	0
TlulRvalidKnown_A	492507365	491677277	0	0
WriteLockPropagation_A	492507365	2004834	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	492507365	20426408	0	0
u_state_regs_A	492507365	491677277	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	13968	0	0
T18	691893	0	0	0
T81	13959	3403	0	0
T172	0	2641	0	0
T173	0	2391	0	0
T174	0	3203	0	0
T175	0	2330	0	0
T180	14112	0	0	0
T181	12623	0	0	0
T182	13805	0	0	0
T183	70740	0	0	0
T184	69279	0	0	0
T185	304331	0	0	0
T186	5600	0	0	0
T187	35535	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	83102684	0	0
T1	166454	7476	0	0
T2	41374	13374	0	0
T3	12241	4498	0	0
T4	160632	589348	0	0
T6	8621	3043	0	0
T9	50189	41797	0	0
T10	24066	12117	0	0
T11	70022	32381	0	0
T12	80499	73785	0	0
T13	9808	4526	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	83102684	0	0
T1	166454	7476	0	0
T2	41374	13374	0	0
T3	12241	4498	0	0
T4	160632	589348	0	0
T6	8621	3043	0	0
T9	50189	41797	0	0
T10	24066	12117	0	0
T11	70022	32381	0	0
T12	80499	73785	0	0
T13	9808	4526	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	55	0	0
T54	9481	0	0	0
T55	16129	0	0	0
T102	0	1	0	0
T134	10221	0	0	0
T195	12759	1	0	0
T196	13685	1	0	0
T197	0	1	0	0
T198	0	1	0	0
T200	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	4383	0	0	0
T209	31227	0	0	0
T210	5563	0	0	0
T211	28973	0	0	0
T212	16422	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	205475519	0	0
T1	166454	93107	0	0
T2	41374	0	0	0
T3	12241	0	0	0
T4	160632	873661	0	0
T6	8621	0	0	0
T7	0	8445	0	0
T8	0	569506	0	0
T9	50189	0	0	0
T10	24066	0	0	0
T11	70022	11326	0	0
T12	80499	0	0	0
T13	9808	0	0	0
T14	0	465184	0	0
T27	0	30493	0	0
T34	0	4207	0	0
T118	0	2706	0	0
T146	0	8958	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	8278	0	0
T1	166454	9	0	0
T2	41374	1	0	0
T3	12241	0	0	0
T4	160632	17	0	0
T6	8621	0	0	0
T7	0	4	0	0
T9	50189	9	0	0
T10	24066	13	0	0
T11	70022	5	0	0
T12	80499	14	0	0
T13	9808	0	0	0
T34	0	5	0	0
T78	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	2004834	0	0
T15	581429	0	0	0
T28	115797	18445	0	0
T37	0	3249	0	0
T45	88935	0	0	0
T69	0	5150	0	0
T101	0	1757	0	0
T105	0	7082	0	0
T107	0	2854	0	0
T109	0	5994	0	0
T110	29586	0	0	0
T112	27937	0	0	0
T113	19624	0	0	0
T114	32139	0	0	0
T115	19993	0	0	0
T116	35117	0	0	0
T117	213072	0	0	0
T129	0	6522	0	0
T130	0	2037	0	0
T136	0	4214	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	20426408	0	0
T7	18536	0	0	0
T8	773417	0	0	0
T10	24066	3503	0	0
T11	70022	0	0	0
T12	80499	0	0	0
T13	9808	0	0	0
T28	0	94801	0	0
T34	35950	27558	0	0
T37	0	92682	0	0
T45	0	39506	0	0
T47	13074	0	0	0
T70	11251	0	0	0
T78	16885	0	0	0
T110	0	17154	0	0
T112	0	10057	0	0
T115	0	2463	0	0
T119	0	2526	0	0
T215	0	2549	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492507365	491677277	0	0
T1	166454	165228	0	0
T2	41374	40823	0	0
T3	12241	12028	0	0
T4	160632	160594	0	0
T6	8621	8344	0	0
T9	50189	49990	0	0
T10	24066	23761	0	0
T11	70022	69364	0	0
T12	80499	80310	0	0
T13	9808	9562	0	0