Module Definition
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Module Instance : tb.dut.u_prim_lc_sync_escalate_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.58 96.10 96.15 97.04 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[10].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[10].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[10].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[10].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[11].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[11].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[11].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[11].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[12].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[12].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[12].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[12].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[13].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[13].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[13].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[13].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[14].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[14].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[14].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[14].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[15].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[15].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[15].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[15].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[8].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[8].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[8].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[8].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[9].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[9].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[9].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[9].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.58 96.10 96.15 97.04 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.58 96.10 96.15 97.04 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_seed_hw_rd_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.58 96.10 96.15 97.04 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_dft_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.58 96.10 96.15 97.04 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_check_byp_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.58 96.10 96.15 97.04 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.66 98.04 88.89 85.71 95.65 50.00 u_tlul_lc_gate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=16,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_escalate_en

Line No.TotalCoveredPercent
TOTAL1717100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 16 16


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en

SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en

SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_seed_hw_rd_en

SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_check_byp_en

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_dft_en

Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 3 3


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 8050 8050 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.OutputDelay_A 2147483647 2147483647 0 20700
gen_no_flops.OutputDelay_A 492507365 491677277 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8050 8050 0 0
T1 7 7 0 0
T2 7 7 0 0
T3 7 7 0 0
T4 7 7 0 0
T6 7 7 0 0
T9 7 7 0 0
T10 7 7 0 0
T11 7 7 0 0
T12 7 7 0 0
T13 7 7 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1165178 1156596 0 0
T2 289618 285761 0 0
T3 85687 84196 0 0
T4 1124424 1124158 0 0
T6 60347 58408 0 0
T9 351323 349930 0 0
T10 168462 166327 0 0
T11 490154 485548 0 0
T12 563493 562170 0 0
T13 68656 66934 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 20700
T1 998724 991044 0 18
T2 248244 244794 0 18
T3 73446 72114 0 18
T4 963792 963552 0 18
T6 51726 49992 0 18
T9 301134 299886 0 18
T10 144396 142494 0 18
T11 420132 415986 0 18
T12 482994 481806 0 18
T13 58848 57300 0 18

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491677277 0 0
T1 166454 165228 0 0
T2 41374 40823 0 0
T3 12241 12028 0 0
T4 160632 160594 0 0
T6 8621 8344 0 0
T9 50189 49990 0 0
T10 24066 23761 0 0
T11 70022 69364 0 0
T12 80499 80310 0 0
T13 9808 9562 0 0

Line Coverage for Instance : tb.dut.u_prim_lc_sync_escalate_en
Line No.TotalCoveredPercent
TOTAL1717100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 16 16


Assert Coverage for Instance : tb.dut.u_prim_lc_sync_escalate_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1150 1150 0 0
OutputsKnown_A 492507365 491677277 0 0
gen_flops.OutputDelay_A 492507365 491638295 0 3450


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491677277 0 0
T1 166454 165228 0 0
T2 41374 40823 0 0
T3 12241 12028 0 0
T4 160632 160594 0 0
T6 8621 8344 0 0
T9 50189 49990 0 0
T10 24066 23761 0 0
T11 70022 69364 0 0
T12 80499 80310 0 0
T13 9808 9562 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491638295 0 3450
T1 166454 165174 0 3
T2 41374 40799 0 3
T3 12241 12019 0 3
T4 160632 160592 0 3
T6 8621 8332 0 3
T9 50189 49981 0 3
T10 24066 23749 0 3
T11 70022 69331 0 3
T12 80499 80301 0 3
T13 9808 9550 0 3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1150 1150 0 0
OutputsKnown_A 492507365 491677277 0 0
gen_flops.OutputDelay_A 492507365 491638295 0 3450


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491677277 0 0
T1 166454 165228 0 0
T2 41374 40823 0 0
T3 12241 12028 0 0
T4 160632 160594 0 0
T6 8621 8344 0 0
T9 50189 49990 0 0
T10 24066 23761 0 0
T11 70022 69364 0 0
T12 80499 80310 0 0
T13 9808 9562 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491638295 0 3450
T1 166454 165174 0 3
T2 41374 40799 0 3
T3 12241 12019 0 3
T4 160632 160592 0 3
T6 8621 8332 0 3
T9 50189 49981 0 3
T10 24066 23749 0 3
T11 70022 69331 0 3
T12 80499 80301 0 3
T13 9808 9550 0 3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1150 1150 0 0
OutputsKnown_A 492507365 491677277 0 0
gen_flops.OutputDelay_A 492507365 491638295 0 3450


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491677277 0 0
T1 166454 165228 0 0
T2 41374 40823 0 0
T3 12241 12028 0 0
T4 160632 160594 0 0
T6 8621 8344 0 0
T9 50189 49990 0 0
T10 24066 23761 0 0
T11 70022 69364 0 0
T12 80499 80310 0 0
T13 9808 9562 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491638295 0 3450
T1 166454 165174 0 3
T2 41374 40799 0 3
T3 12241 12019 0 3
T4 160632 160592 0 3
T6 8621 8332 0 3
T9 50189 49981 0 3
T10 24066 23749 0 3
T11 70022 69331 0 3
T12 80499 80301 0 3
T13 9808 9550 0 3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_seed_hw_rd_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_prim_lc_sync_seed_hw_rd_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1150 1150 0 0
OutputsKnown_A 492507365 491677277 0 0
gen_flops.OutputDelay_A 492507365 491638295 0 3450


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491677277 0 0
T1 166454 165228 0 0
T2 41374 40823 0 0
T3 12241 12028 0 0
T4 160632 160594 0 0
T6 8621 8344 0 0
T9 50189 49990 0 0
T10 24066 23761 0 0
T11 70022 69364 0 0
T12 80499 80310 0 0
T13 9808 9562 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491638295 0 3450
T1 166454 165174 0 3
T2 41374 40799 0 3
T3 12241 12019 0 3
T4 160632 160592 0 3
T6 8621 8332 0 3
T9 50189 49981 0 3
T10 24066 23749 0 3
T11 70022 69331 0 3
T12 80499 80301 0 3
T13 9808 9550 0 3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 3 3


Assert Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1150 1150 0 0
OutputsKnown_A 492507365 491677277 0 0
gen_flops.OutputDelay_A 492507365 491638295 0 3450


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491677277 0 0
T1 166454 165228 0 0
T2 41374 40823 0 0
T3 12241 12028 0 0
T4 160632 160594 0 0
T6 8621 8344 0 0
T9 50189 49990 0 0
T10 24066 23761 0 0
T11 70022 69364 0 0
T12 80499 80310 0 0
T13 9808 9562 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491638295 0 3450
T1 166454 165174 0 3
T2 41374 40799 0 3
T3 12241 12019 0 3
T4 160632 160592 0 3
T6 8621 8332 0 3
T9 50189 49981 0 3
T10 24066 23749 0 3
T11 70022 69331 0 3
T12 80499 80301 0 3
T13 9808 9550 0 3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_check_byp_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_prim_lc_sync_check_byp_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1150 1150 0 0
OutputsKnown_A 492507365 491677277 0 0
gen_flops.OutputDelay_A 492507365 491638295 0 3450


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491677277 0 0
T1 166454 165228 0 0
T2 41374 40823 0 0
T3 12241 12028 0 0
T4 160632 160594 0 0
T6 8621 8344 0 0
T9 50189 49990 0 0
T10 24066 23761 0 0
T11 70022 69364 0 0
T12 80499 80310 0 0
T13 9808 9562 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491638295 0 3450
T1 166454 165174 0 3
T2 41374 40799 0 3
T3 12241 12019 0 3
T4 160632 160592 0 3
T6 8621 8332 0 3
T9 50189 49981 0 3
T10 24066 23749 0 3
T11 70022 69331 0 3
T12 80499 80301 0 3
T13 9808 9550 0 3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1150 1150 0 0
OutputsKnown_A 492507365 491677277 0 0
gen_no_flops.OutputDelay_A 492507365 491677277 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491677277 0 0
T1 166454 165228 0 0
T2 41374 40823 0 0
T3 12241 12028 0 0
T4 160632 160594 0 0
T6 8621 8344 0 0
T9 50189 49990 0 0
T10 24066 23761 0 0
T11 70022 69364 0 0
T12 80499 80310 0 0
T13 9808 9562 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492507365 491677277 0 0
T1 166454 165228 0 0
T2 41374 40823 0 0
T3 12241 12028 0 0
T4 160632 160594 0 0
T6 8621 8344 0 0
T9 50189 49990 0 0
T10 24066 23761 0 0
T11 70022 69364 0 0
T12 80499 80310 0 0
T13 9808 9562 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%