Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

23969600

1

T1

343

T2

512

T3

250180

full_word

7913964

1

T1

162

T2

251

T3

73402

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31883284	1			T1	505		T2	763		T3	323582
auto[TlIntgErrCmd]	90	1			T264	7		T265	5		T266	8
auto[TlIntgErrData]	105	1			T264	7		T265	2		T266	6
auto[TlIntgErrBoth]	85	1			T264	6		T265	3		T266	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9739057

1

T1

307

T2

461

T3

54113

auto[1]

22144507

1

T1

198

T2

302

T3

269469

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6205447	1			T1	231		T2	345		T3	32228
auto[TlIntgErrNone]	partial	auto[1]	17763893	1			T1	112		T2	167		T3	217952
auto[TlIntgErrNone]	full_word	auto[0]	3533480	1			T1	76		T2	116		T3	21885
auto[TlIntgErrNone]	full_word	auto[1]	4380464	1			T1	86		T2	135		T3	51517
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T264	2		T265	1		T266	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T264	5		T265	4		T266	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T266	1		T334	1		T338	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T266	1		T333	2		-	-
auto[TlIntgErrData]	partial	auto[0]	46	1			T264	2		T266	4		T271	4
auto[TlIntgErrData]	partial	auto[1]	51	1			T264	5		T265	2		T266	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T271	1		T334	1		T340	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T271	1		T270	1		T341	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T264	1		T265	2		T266	1
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T264	4		T265	1		T266	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T266	1		T342	1		T336	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T264	1		T271	1		T334	1