Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.96	98.05	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	476117732	7481420	0	0
check_regwen_rd_A	476117732	3005	0	0
check_timeout_rd_A	476117732	2112	0	0
check_trigger_regwen_rd_A	476117732	2896	0	0
consistency_check_period_rd_A	476117732	3096	0	0
creator_sw_cfg_read_lock_rd_A	476117732	2340	0	0
direct_access_address_rd_A	476117732	1879	0	0
direct_access_wdata_0_rd_A	476117732	1293	0	0
direct_access_wdata_1_rd_A	476117732	1421	0	0
integrity_check_period_rd_A	476117732	2941	0	0
intr_enable_rd_A	476117732	4028	0	0
owner_sw_cfg_read_lock_rd_A	476117732	2104	0	0
rot_creator_auth_codesign_read_lock_rd_A	476117732	2326	0	0
rot_creator_auth_state_read_lock_rd_A	476117732	1944	0	0
vendor_test_read_lock_rd_A	476117732	1974	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	7481420	0	0
T3	547471	92343	0	0
T4	50763	0	0	0
T5	11371	0	0	0
T6	655000	140611	0	0
T7	0	111726	0	0
T8	15736	0	0	0
T9	12774	0	0	0
T10	83394	0	0	0
T11	9262	0	0	0
T13	20024	0	0	0
T14	0	228177	0	0
T15	0	127902	0	0
T66	0	79611	0	0
T67	0	23389	0	0
T68	0	132210	0	0
T112	80231	0	0	0
T191	0	49513	0	0
T257	0	24639	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	3005	0	0
T15	0	58	0	0
T48	15056	0	0	0
T66	428259	93	0	0
T109	22529	0	0	0
T117	71615	0	0	0
T118	15837	0	0	0
T119	28459	0	0	0
T146	124674	0	0	0
T165	27082	0	0	0
T191	240180	0	0	0
T212	0	83	0	0
T257	0	40	0	0
T273	0	40	0	0
T318	0	154	0	0
T319	0	231	0	0
T320	0	76	0	0
T321	0	58	0	0
T322	0	36	0	0
T323	9550	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	2112	0	0
T15	0	118	0	0
T48	15056	0	0	0
T66	428259	162	0	0
T109	22529	0	0	0
T117	71615	0	0	0
T118	15837	0	0	0
T119	28459	0	0	0
T146	124674	0	0	0
T165	27082	0	0	0
T191	240180	0	0	0
T212	0	58	0	0
T257	0	32	0	0
T273	0	40	0	0
T318	0	144	0	0
T319	0	280	0	0
T320	0	54	0	0
T321	0	61	0	0
T322	0	34	0	0
T323	9550	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	2896	0	0
T15	0	94	0	0
T48	15056	0	0	0
T66	428259	113	0	0
T109	22529	0	0	0
T117	71615	0	0	0
T118	15837	0	0	0
T119	28459	0	0	0
T146	124674	0	0	0
T165	27082	0	0	0
T191	240180	0	0	0
T212	0	74	0	0
T257	0	31	0	0
T273	0	49	0	0
T318	0	139	0	0
T319	0	283	0	0
T320	0	28	0	0
T321	0	52	0	0
T322	0	46	0	0
T323	9550	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	3096	0	0
T15	0	58	0	0
T48	15056	0	0	0
T66	428259	86	0	0
T109	22529	0	0	0
T117	71615	0	0	0
T118	15837	0	0	0
T119	28459	0	0	0
T146	124674	0	0	0
T165	27082	0	0	0
T191	240180	0	0	0
T212	0	152	0	0
T257	0	39	0	0
T273	0	94	0	0
T318	0	181	0	0
T319	0	265	0	0
T320	0	46	0	0
T321	0	30	0	0
T322	0	38	0	0
T323	9550	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	2340	0	0
T15	0	112	0	0
T48	15056	0	0	0
T66	428259	112	0	0
T109	22529	0	0	0
T117	71615	0	0	0
T118	15837	0	0	0
T119	28459	0	0	0
T146	124674	0	0	0
T165	27082	0	0	0
T191	240180	0	0	0
T212	0	122	0	0
T257	0	51	0	0
T273	0	79	0	0
T318	0	155	0	0
T319	0	322	0	0
T320	0	84	0	0
T321	0	59	0	0
T322	0	25	0	0
T323	9550	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	1879	0	0
T15	0	112	0	0
T48	15056	0	0	0
T66	428259	118	0	0
T109	22529	0	0	0
T117	71615	0	0	0
T118	15837	0	0	0
T119	28459	0	0	0
T146	124674	0	0	0
T165	27082	0	0	0
T191	240180	0	0	0
T212	0	60	0	0
T257	0	54	0	0
T273	0	44	0	0
T318	0	154	0	0
T319	0	329	0	0
T320	0	80	0	0
T321	0	44	0	0
T322	0	20	0	0
T323	9550	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	1293	0	0
T15	0	77	0	0
T48	15056	0	0	0
T66	428259	79	0	0
T109	22529	0	0	0
T117	71615	0	0	0
T118	15837	0	0	0
T119	28459	0	0	0
T146	124674	0	0	0
T165	27082	0	0	0
T191	240180	0	0	0
T212	0	68	0	0
T257	0	28	0	0
T273	0	72	0	0
T318	0	122	0	0
T319	0	179	0	0
T320	0	59	0	0
T321	0	23	0	0
T322	0	26	0	0
T323	9550	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	1421	0	0
T15	0	86	0	0
T48	15056	0	0	0
T66	428259	79	0	0
T109	22529	0	0	0
T117	71615	0	0	0
T118	15837	0	0	0
T119	28459	0	0	0
T146	124674	0	0	0
T165	27082	0	0	0
T191	240180	0	0	0
T212	0	87	0	0
T257	0	41	0	0
T273	0	28	0	0
T318	0	122	0	0
T319	0	184	0	0
T320	0	50	0	0
T321	0	31	0	0
T322	0	28	0	0
T323	9550	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	2941	0	0
T15	0	77	0	0
T48	15056	0	0	0
T66	428259	126	0	0
T109	22529	0	0	0
T117	71615	0	0	0
T118	15837	0	0	0
T119	28459	0	0	0
T146	124674	0	0	0
T165	27082	0	0	0
T191	240180	0	0	0
T212	0	47	0	0
T257	0	45	0	0
T273	0	53	0	0
T318	0	105	0	0
T319	0	245	0	0
T320	0	45	0	0
T321	0	53	0	0
T322	0	25	0	0
T323	9550	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	4028	0	0
T15	0	115	0	0
T48	15056	0	0	0
T66	428259	112	0	0
T97	0	5	0	0
T109	22529	0	0	0
T117	71615	0	0	0
T118	15837	0	0	0
T119	28459	0	0	0
T146	124674	0	0	0
T165	27082	0	0	0
T191	240180	0	0	0
T210	0	7	0	0
T212	0	109	0	0
T237	0	32	0	0
T257	0	99	0	0
T273	0	60	0	0
T318	0	165	0	0
T319	0	321	0	0
T323	9550	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	2104	0	0
T15	0	55	0	0
T48	15056	0	0	0
T66	428259	88	0	0
T109	22529	0	0	0
T117	71615	0	0	0
T118	15837	0	0	0
T119	28459	0	0	0
T146	124674	0	0	0
T165	27082	0	0	0
T191	240180	0	0	0
T212	0	105	0	0
T257	0	24	0	0
T273	0	60	0	0
T318	0	137	0	0
T319	0	239	0	0
T320	0	57	0	0
T321	0	25	0	0
T322	0	25	0	0
T323	9550	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	2326	0	0
T15	0	96	0	0
T48	15056	0	0	0
T66	428259	162	0	0
T109	22529	0	0	0
T117	71615	0	0	0
T118	15837	0	0	0
T119	28459	0	0	0
T146	124674	0	0	0
T165	27082	0	0	0
T191	240180	0	0	0
T212	0	132	0	0
T257	0	27	0	0
T273	0	79	0	0
T318	0	125	0	0
T319	0	282	0	0
T320	0	73	0	0
T321	0	56	0	0
T322	0	49	0	0
T323	9550	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	1944	0	0
T15	0	67	0	0
T48	15056	0	0	0
T66	428259	115	0	0
T109	22529	0	0	0
T117	71615	0	0	0
T118	15837	0	0	0
T119	28459	0	0	0
T146	124674	0	0	0
T165	27082	0	0	0
T191	240180	0	0	0
T212	0	64	0	0
T257	0	53	0	0
T273	0	66	0	0
T318	0	111	0	0
T319	0	229	0	0
T320	0	66	0	0
T321	0	31	0	0
T322	0	28	0	0
T323	9550	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476117732	1974	0	0
T15	0	146	0	0
T48	15056	0	0	0
T66	428259	143	0	0
T109	22529	0	0	0
T117	71615	0	0	0
T118	15837	0	0	0
T119	28459	0	0	0
T146	124674	0	0	0
T165	27082	0	0	0
T191	240180	0	0	0
T212	0	69	0	0
T257	0	25	0	0
T273	0	80	0	0
T318	0	120	0	0
T319	0	228	0	0
T320	0	62	0	0
T321	0	56	0	0
T322	0	46	0	0
T323	9550	0	0	0