Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T64,T29,T82

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T14,T165,T160

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T19,T20,T21

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T74,T166,T167
1	Covered	T74,T166,T167

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T14

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T14

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T4,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T4,T5
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Covered	T10,T119,T177
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T65,T168,T220
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T5,T6
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T221,T222,T223
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T74,T75,T76
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T5,T6
CheckFailError	317	Covered	T74,T166,T167
FsmStateError	289	Covered	T3,T4,T5
MacroEccCorrError	221	Covered	T14,T64,T29
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T90,T23,T16
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T5,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T74,T166,T167
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T4,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T64,T29,T82
MacroEccCorrError->NoError	235	Covered	T14,T160,T218
NoError->AccessError	256	Covered	T4,T5,T6
NoError->CheckFailError	317	Covered	T74,T166,T167
NoError->FsmStateError	289	Covered	T3,T4,T5
NoError->MacroEccCorrError	221	Covered	T14,T64,T29

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T64,T29,T82
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T65,T220,T224
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T92,T97,T99
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T14,T165,T160
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T221,T222,T223
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T19,T20,T21
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T74,T166,T167
1	0	Covered	T74,T166,T167
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	449173931	448303791	0	0
DigestKnown_A	449173931	448303791	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	449173931	22621	0	0
ErrorKnown_A	449173931	448303791	0	0
FsmStateKnown_A	449173931	448303791	0	0
InitDoneKnown_A	449173931	448303791	0	0
InitReadLocksPartition_A	449173931	82316397	0	0
InitWriteLocksPartition_A	449173931	82316397	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	449173931	448303791	0	0
OtpCmdKnown_A	449173931	448303791	0	0
OtpErrorState_A	449173931	41	0	0
OtpReqKnown_A	449173931	448303791	0	0
OtpSizeKnown_A	449173931	448303791	0	0
OtpWdataKnown_A	449173931	448303791	0	0
ReadLockPropagation_A	449173931	188031252	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	449173931	448303791	0	0
TlulRdataKnown_A	449173931	448303791	0	0
TlulReadOnReadLock_A	449173931	8090	0	0
TlulRerrorKnown_A	449173931	448303791	0	0
TlulRvalidKnown_A	449173931	448303791	0	0
WriteLockPropagation_A	449173931	2700108	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	449173931	28135345	0	0
u_state_regs_A	449173931	448303791	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	22621	0	0
T12	192285	0	0	0
T16	233521	0	0	0
T70	16235	0	0	0
T74	9688	2469	0	0
T94	23532	0	0	0
T109	12414	0	0	0
T119	15260	0	0	0
T162	22189	0	0	0
T166	0	3094	0	0
T167	0	2983	0	0
T170	0	3250	0	0
T173	65312	0	0	0
T176	0	2199	0	0
T180	0	2826	0	0
T182	0	2367	0	0
T183	0	3433	0	0
T185	26833	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	82316397	0	0
T1	106902	1551	0	0
T2	12987	1382	0	0
T3	10479	4004	0	0
T4	756283	207354	0	0
T5	56328	6784	0	0
T6	603424	23907	0	0
T8	13701	3968	0	0
T9	12421	4790	0	0
T10	10569	3007	0	0
T11	17381	4271	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	82316397	0	0
T1	106902	1551	0	0
T2	12987	1382	0	0
T3	10479	4004	0	0
T4	756283	207354	0	0
T5	56328	6784	0	0
T6	603424	23907	0	0
T8	13701	3968	0	0
T9	12421	4790	0	0
T10	10569	3007	0	0
T11	17381	4271	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	41	0	0
T23	284205	0	0	0
T44	10788	0	0	0
T64	13442	0	0	0
T65	10032	1	0	0
T89	4835	0	0	0
T90	30007	0	0	0
T91	60308	0	0	0
T92	42627	0	0	0
T93	39898	0	0	0
T104	64912	0	0	0
T220	0	1	0	0
T224	0	1	0	0
T225	0	1	0	0
T226	0	1	0	0
T227	0	1	0	0
T228	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0
T231	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	188031252	0	0
T1	106902	10377	0	0
T2	12987	0	0	0
T3	10479	0	0	0
T4	756283	283960	0	0
T5	56328	7805	0	0
T6	603424	519745	0	0
T7	0	135613	0	0
T8	13701	0	0	0
T9	12421	0	0	0
T10	10569	0	0	0
T11	17381	0	0	0
T14	0	38636	0	0
T15	0	56288	0	0
T62	0	14056	0	0
T90	0	17852	0	0
T104	0	3759	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	8090	0	0
T4	756283	46	0	0
T5	56328	9	0	0
T6	603424	17	0	0
T7	0	21	0	0
T8	13701	0	0	0
T9	12421	0	0	0
T10	10569	0	0	0
T11	17381	0	0	0
T13	64282	21	0	0
T14	134137	13	0	0
T15	0	37	0	0
T62	0	10	0	0
T102	12342	3	0	0
T103	0	10	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	2700108	0	0
T1	106902	7264	0	0
T2	12987	0	0	0
T3	10479	0	0	0
T4	756283	0	0	0
T5	56328	0	0	0
T6	603424	0	0	0
T8	13701	0	0	0
T9	12421	0	0	0
T10	10569	0	0	0
T11	17381	0	0	0
T14	0	17022	0	0
T15	0	26930	0	0
T91	0	3075	0	0
T95	0	30764	0	0
T97	0	7686	0	0
T98	0	27344	0	0
T99	0	5531	0	0
T104	0	3296	0	0
T108	0	17134	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	28135345	0	0
T1	106902	63073	0	0
T2	12987	0	0	0
T3	10479	0	0	0
T4	756283	0	0	0
T5	56328	38983	0	0
T6	603424	0	0	0
T8	13701	0	0	0
T9	12421	0	0	0
T10	10569	0	0	0
T11	17381	0	0	0
T14	0	111027	0	0
T15	0	246381	0	0
T62	0	77672	0	0
T90	0	2904	0	0
T91	0	42300	0	0
T92	0	24424	0	0
T104	0	47997	0	0
T173	0	3959	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T174,T39,T175

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T14,T165,T159

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T19,T20,T21

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T167,T176,T171
1	Covered	T167,T176,T171

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T14

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T14

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T4,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T4,T5
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T10,T119,T177
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T65,T232,T220
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T5,T6
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T165,T159,T178
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T74,T75,T76
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T5,T6
CheckFailError	317	Covered	T167,T176,T171
FsmStateError	289	Covered	T3,T4,T5
MacroEccCorrError	221	Covered	T14,T165,T174
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T23,T16
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T5,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T167,T176,T171
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T4,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T174,T159,T178
MacroEccCorrError->NoError	235	Covered	T14,T165,T233
NoError->AccessError	256	Covered	T4,T5,T6
NoError->CheckFailError	317	Covered	T167,T176,T171
NoError->FsmStateError	289	Covered	T3,T4,T5
NoError->MacroEccCorrError	221	Covered	T14,T165,T174

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T174,T39,T175
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T232,T234,T235
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T92,T158,T97
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T14,T165,T159
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T165,T159,T178
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T19,T20,T21
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T167,T176,T171
1	0	Covered	T167,T176,T171
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	449173931	448303791	0	0
DigestKnown_A	449173931	448303791	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	449173931	11379	0	0
ErrorKnown_A	449173931	448303791	0	0
FsmStateKnown_A	449173931	448303791	0	0
InitDoneKnown_A	449173931	448303791	0	0
InitReadLocksPartition_A	449173931	82496753	0	0
InitWriteLocksPartition_A	449173931	82496753	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	449173931	448303791	0	0
OtpCmdKnown_A	449173931	448303791	0	0
OtpErrorState_A	449173931	40	0	0
OtpReqKnown_A	449173931	448303791	0	0
OtpSizeKnown_A	449173931	448303791	0	0
OtpWdataKnown_A	449173931	448303791	0	0
ReadLockPropagation_A	449173931	197738148	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	449173931	448303791	0	0
TlulRdataKnown_A	449173931	448303791	0	0
TlulReadOnReadLock_A	449173931	7772	0	0
TlulRerrorKnown_A	449173931	448303791	0	0
TlulRvalidKnown_A	449173931	448303791	0	0
WriteLockPropagation_A	449173931	1021740	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	449173931	12673101	0	0
u_state_regs_A	449173931	448303791	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	11379	0	0
T167	10923	2983	0	0
T171	0	3590	0	0
T176	0	2199	0	0
T181	0	2607	0	0
T186	25952	0	0	0
T187	63289	0	0	0
T188	9756	0	0	0
T189	44494	0	0	0
T190	10078	0	0	0
T191	170958	0	0	0
T192	9686	0	0	0
T193	11147	0	0	0
T194	89239	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	82496753	0	0
T1	106902	1806	0	0
T2	12987	1433	0	0
T3	10479	4038	0	0
T4	756283	207558	0	0
T5	56328	7005	0	0
T6	603424	24043	0	0
T8	13701	4002	0	0
T9	12421	4824	0	0
T10	10569	3024	0	0
T11	17381	4305	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	82496753	0	0
T1	106902	1806	0	0
T2	12987	1433	0	0
T3	10479	4038	0	0
T4	756283	207558	0	0
T5	56328	7005	0	0
T6	603424	24043	0	0
T8	13701	4002	0	0
T9	12421	4824	0	0
T10	10569	3024	0	0
T11	17381	4305	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	40	0	0
T30	15279	0	0	0
T76	8875	0	0	0
T146	54282	0	0	0
T159	0	1	0	0
T161	0	1	0	0
T165	53556	1	0	0
T169	29073	0	0	0
T178	0	1	0	0
T211	26656	0	0	0
T212	119296	0	0	0
T232	11410	1	0	0
T234	0	1	0	0
T235	0	1	0	0
T236	0	1	0	0
T237	0	1	0	0
T238	0	1	0	0
T239	62519	0	0	0
T240	17651	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	197738148	0	0
T1	106902	8451	0	0
T2	12987	0	0	0
T3	10479	0	0	0
T4	756283	281213	0	0
T5	56328	8625	0	0
T6	603424	520170	0	0
T7	0	204051	0	0
T8	13701	0	0	0
T9	12421	0	0	0
T10	10569	0	0	0
T11	17381	0	0	0
T14	0	52574	0	0
T15	0	61828	0	0
T62	0	11505	0	0
T90	0	18883	0	0
T104	0	4329	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	7772	0	0
T4	756283	44	0	0
T5	56328	11	0	0
T6	603424	20	0	0
T7	0	31	0	0
T8	13701	0	0	0
T9	12421	0	0	0
T10	10569	0	0	0
T11	17381	0	0	0
T13	64282	15	0	0
T14	134137	23	0	0
T15	0	59	0	0
T62	0	10	0	0
T102	12342	3	0	0
T103	0	11	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	1021740	0	0
T1	106902	1879	0	0
T2	12987	0	0	0
T3	10479	0	0	0
T4	756283	0	0	0
T5	56328	3477	0	0
T6	603424	0	0	0
T8	13701	0	0	0
T9	12421	0	0	0
T10	10569	0	0	0
T11	17381	0	0	0
T14	0	13028	0	0
T15	0	17519	0	0
T92	0	943	0	0
T96	0	12639	0	0
T104	0	1004	0	0
T131	0	3989	0	0
T213	0	17465	0	0
T241	0	9834	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	12673101	0	0
T1	106902	62920	0	0
T2	12987	0	0	0
T3	10479	0	0	0
T4	756283	0	0	0
T5	56328	45737	0	0
T6	603424	0	0	0
T8	13701	0	0	0
T9	12421	0	0	0
T10	10569	0	0	0
T11	17381	0	0	0
T14	0	110891	0	0
T15	0	172177	0	0
T62	0	77485	0	0
T92	0	32426	0	0
T96	0	57168	0	0
T104	0	47742	0	0
T232	0	2925	0	0
T242	0	313003	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449173931	448303791	0	0
T1	106902	105679	0	0
T2	12987	12793	0	0
T3	10479	10214	0	0
T4	756283	756261	0	0
T5	56328	55462	0	0
T6	603424	603397	0	0
T8	13701	13512	0	0
T9	12421	12226	0	0
T10	10569	10342	0	0
T11	17381	17109	0	0