SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_escalate_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_seed_hw_rd_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_check_byp_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.82 | 97.40 | 96.15 | 96.92 | 96.43 | 97.18 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.82 | 97.40 | 96.15 | 96.92 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.82 | 97.40 | 96.15 | 96.92 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.82 | 97.40 | 96.15 | 96.92 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.82 | 97.40 | 96.15 | 96.92 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.82 | 97.40 | 96.15 | 96.92 | 96.43 | 97.18 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
83.66 | 98.04 | 88.89 | 85.71 | 95.65 | 50.00 | u_tlul_lc_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 17 | 17 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 16 | 16 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 8050 | 8050 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 20700 |
gen_no_flops.OutputDelay_A | 449173931 | 448303791 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 8050 | 8050 | 0 | 0 |
T1 | 7 | 7 | 0 | 0 |
T2 | 7 | 7 | 0 | 0 |
T3 | 7 | 7 | 0 | 0 |
T4 | 7 | 7 | 0 | 0 |
T5 | 7 | 7 | 0 | 0 |
T6 | 7 | 7 | 0 | 0 |
T8 | 7 | 7 | 0 | 0 |
T9 | 7 | 7 | 0 | 0 |
T10 | 7 | 7 | 0 | 0 |
T11 | 7 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 748314 | 739753 | 0 | 0 |
T2 | 90909 | 89551 | 0 | 0 |
T3 | 73353 | 71498 | 0 | 0 |
T4 | 5293981 | 5293827 | 0 | 0 |
T5 | 394296 | 388234 | 0 | 0 |
T6 | 4223968 | 4223779 | 0 | 0 |
T8 | 95907 | 94584 | 0 | 0 |
T9 | 86947 | 85582 | 0 | 0 |
T10 | 73983 | 72394 | 0 | 0 |
T11 | 121667 | 119763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 20700 |
T1 | 641412 | 633750 | 0 | 18 |
T2 | 77922 | 76704 | 0 | 18 |
T3 | 62874 | 61212 | 0 | 18 |
T4 | 4537698 | 4537536 | 0 | 18 |
T5 | 337968 | 332520 | 0 | 18 |
T6 | 3620544 | 3620364 | 0 | 18 |
T8 | 82206 | 81018 | 0 | 18 |
T9 | 74526 | 73302 | 0 | 18 |
T10 | 63414 | 61998 | 0 | 18 |
T11 | 104286 | 102582 | 0 | 18 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448303791 | 0 | 0 |
T1 | 106902 | 105679 | 0 | 0 |
T2 | 12987 | 12793 | 0 | 0 |
T3 | 10479 | 10214 | 0 | 0 |
T4 | 756283 | 756261 | 0 | 0 |
T5 | 56328 | 55462 | 0 | 0 |
T6 | 603424 | 603397 | 0 | 0 |
T8 | 13701 | 13512 | 0 | 0 |
T9 | 12421 | 12226 | 0 | 0 |
T10 | 10569 | 10342 | 0 | 0 |
T11 | 17381 | 17109 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 17 | 17 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 16 | 16 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1150 | 1150 | 0 | 0 |
OutputsKnown_A | 449173931 | 448303791 | 0 | 0 |
gen_flops.OutputDelay_A | 449173931 | 448263155 | 0 | 3450 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1150 | 1150 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448303791 | 0 | 0 |
T1 | 106902 | 105679 | 0 | 0 |
T2 | 12987 | 12793 | 0 | 0 |
T3 | 10479 | 10214 | 0 | 0 |
T4 | 756283 | 756261 | 0 | 0 |
T5 | 56328 | 55462 | 0 | 0 |
T6 | 603424 | 603397 | 0 | 0 |
T8 | 13701 | 13512 | 0 | 0 |
T9 | 12421 | 12226 | 0 | 0 |
T10 | 10569 | 10342 | 0 | 0 |
T11 | 17381 | 17109 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448263155 | 0 | 3450 |
T1 | 106902 | 105625 | 0 | 3 |
T2 | 12987 | 12784 | 0 | 3 |
T3 | 10479 | 10202 | 0 | 3 |
T4 | 756283 | 756256 | 0 | 3 |
T5 | 56328 | 55420 | 0 | 3 |
T6 | 603424 | 603394 | 0 | 3 |
T8 | 13701 | 13503 | 0 | 3 |
T9 | 12421 | 12217 | 0 | 3 |
T10 | 10569 | 10333 | 0 | 3 |
T11 | 17381 | 17097 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1150 | 1150 | 0 | 0 |
OutputsKnown_A | 449173931 | 448303791 | 0 | 0 |
gen_flops.OutputDelay_A | 449173931 | 448263155 | 0 | 3450 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1150 | 1150 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448303791 | 0 | 0 |
T1 | 106902 | 105679 | 0 | 0 |
T2 | 12987 | 12793 | 0 | 0 |
T3 | 10479 | 10214 | 0 | 0 |
T4 | 756283 | 756261 | 0 | 0 |
T5 | 56328 | 55462 | 0 | 0 |
T6 | 603424 | 603397 | 0 | 0 |
T8 | 13701 | 13512 | 0 | 0 |
T9 | 12421 | 12226 | 0 | 0 |
T10 | 10569 | 10342 | 0 | 0 |
T11 | 17381 | 17109 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448263155 | 0 | 3450 |
T1 | 106902 | 105625 | 0 | 3 |
T2 | 12987 | 12784 | 0 | 3 |
T3 | 10479 | 10202 | 0 | 3 |
T4 | 756283 | 756256 | 0 | 3 |
T5 | 56328 | 55420 | 0 | 3 |
T6 | 603424 | 603394 | 0 | 3 |
T8 | 13701 | 13503 | 0 | 3 |
T9 | 12421 | 12217 | 0 | 3 |
T10 | 10569 | 10333 | 0 | 3 |
T11 | 17381 | 17097 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1150 | 1150 | 0 | 0 |
OutputsKnown_A | 449173931 | 448303791 | 0 | 0 |
gen_flops.OutputDelay_A | 449173931 | 448263155 | 0 | 3450 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1150 | 1150 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448303791 | 0 | 0 |
T1 | 106902 | 105679 | 0 | 0 |
T2 | 12987 | 12793 | 0 | 0 |
T3 | 10479 | 10214 | 0 | 0 |
T4 | 756283 | 756261 | 0 | 0 |
T5 | 56328 | 55462 | 0 | 0 |
T6 | 603424 | 603397 | 0 | 0 |
T8 | 13701 | 13512 | 0 | 0 |
T9 | 12421 | 12226 | 0 | 0 |
T10 | 10569 | 10342 | 0 | 0 |
T11 | 17381 | 17109 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448263155 | 0 | 3450 |
T1 | 106902 | 105625 | 0 | 3 |
T2 | 12987 | 12784 | 0 | 3 |
T3 | 10479 | 10202 | 0 | 3 |
T4 | 756283 | 756256 | 0 | 3 |
T5 | 56328 | 55420 | 0 | 3 |
T6 | 603424 | 603394 | 0 | 3 |
T8 | 13701 | 13503 | 0 | 3 |
T9 | 12421 | 12217 | 0 | 3 |
T10 | 10569 | 10333 | 0 | 3 |
T11 | 17381 | 17097 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1150 | 1150 | 0 | 0 |
OutputsKnown_A | 449173931 | 448303791 | 0 | 0 |
gen_flops.OutputDelay_A | 449173931 | 448263155 | 0 | 3450 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1150 | 1150 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448303791 | 0 | 0 |
T1 | 106902 | 105679 | 0 | 0 |
T2 | 12987 | 12793 | 0 | 0 |
T3 | 10479 | 10214 | 0 | 0 |
T4 | 756283 | 756261 | 0 | 0 |
T5 | 56328 | 55462 | 0 | 0 |
T6 | 603424 | 603397 | 0 | 0 |
T8 | 13701 | 13512 | 0 | 0 |
T9 | 12421 | 12226 | 0 | 0 |
T10 | 10569 | 10342 | 0 | 0 |
T11 | 17381 | 17109 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448263155 | 0 | 3450 |
T1 | 106902 | 105625 | 0 | 3 |
T2 | 12987 | 12784 | 0 | 3 |
T3 | 10479 | 10202 | 0 | 3 |
T4 | 756283 | 756256 | 0 | 3 |
T5 | 56328 | 55420 | 0 | 3 |
T6 | 603424 | 603394 | 0 | 3 |
T8 | 13701 | 13503 | 0 | 3 |
T9 | 12421 | 12217 | 0 | 3 |
T10 | 10569 | 10333 | 0 | 3 |
T11 | 17381 | 17097 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1150 | 1150 | 0 | 0 |
OutputsKnown_A | 449173931 | 448303791 | 0 | 0 |
gen_flops.OutputDelay_A | 449173931 | 448263155 | 0 | 3450 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1150 | 1150 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448303791 | 0 | 0 |
T1 | 106902 | 105679 | 0 | 0 |
T2 | 12987 | 12793 | 0 | 0 |
T3 | 10479 | 10214 | 0 | 0 |
T4 | 756283 | 756261 | 0 | 0 |
T5 | 56328 | 55462 | 0 | 0 |
T6 | 603424 | 603397 | 0 | 0 |
T8 | 13701 | 13512 | 0 | 0 |
T9 | 12421 | 12226 | 0 | 0 |
T10 | 10569 | 10342 | 0 | 0 |
T11 | 17381 | 17109 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448263155 | 0 | 3450 |
T1 | 106902 | 105625 | 0 | 3 |
T2 | 12987 | 12784 | 0 | 3 |
T3 | 10479 | 10202 | 0 | 3 |
T4 | 756283 | 756256 | 0 | 3 |
T5 | 56328 | 55420 | 0 | 3 |
T6 | 603424 | 603394 | 0 | 3 |
T8 | 13701 | 13503 | 0 | 3 |
T9 | 12421 | 12217 | 0 | 3 |
T10 | 10569 | 10333 | 0 | 3 |
T11 | 17381 | 17097 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1150 | 1150 | 0 | 0 |
OutputsKnown_A | 449173931 | 448303791 | 0 | 0 |
gen_flops.OutputDelay_A | 449173931 | 448263155 | 0 | 3450 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1150 | 1150 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448303791 | 0 | 0 |
T1 | 106902 | 105679 | 0 | 0 |
T2 | 12987 | 12793 | 0 | 0 |
T3 | 10479 | 10214 | 0 | 0 |
T4 | 756283 | 756261 | 0 | 0 |
T5 | 56328 | 55462 | 0 | 0 |
T6 | 603424 | 603397 | 0 | 0 |
T8 | 13701 | 13512 | 0 | 0 |
T9 | 12421 | 12226 | 0 | 0 |
T10 | 10569 | 10342 | 0 | 0 |
T11 | 17381 | 17109 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448263155 | 0 | 3450 |
T1 | 106902 | 105625 | 0 | 3 |
T2 | 12987 | 12784 | 0 | 3 |
T3 | 10479 | 10202 | 0 | 3 |
T4 | 756283 | 756256 | 0 | 3 |
T5 | 56328 | 55420 | 0 | 3 |
T6 | 603424 | 603394 | 0 | 3 |
T8 | 13701 | 13503 | 0 | 3 |
T9 | 12421 | 12217 | 0 | 3 |
T10 | 10569 | 10333 | 0 | 3 |
T11 | 17381 | 17097 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1150 | 1150 | 0 | 0 |
OutputsKnown_A | 449173931 | 448303791 | 0 | 0 |
gen_no_flops.OutputDelay_A | 449173931 | 448303791 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1150 | 1150 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448303791 | 0 | 0 |
T1 | 106902 | 105679 | 0 | 0 |
T2 | 12987 | 12793 | 0 | 0 |
T3 | 10479 | 10214 | 0 | 0 |
T4 | 756283 | 756261 | 0 | 0 |
T5 | 56328 | 55462 | 0 | 0 |
T6 | 603424 | 603397 | 0 | 0 |
T8 | 13701 | 13512 | 0 | 0 |
T9 | 12421 | 12226 | 0 | 0 |
T10 | 10569 | 10342 | 0 | 0 |
T11 | 17381 | 17109 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 449173931 | 448303791 | 0 | 0 |
T1 | 106902 | 105679 | 0 | 0 |
T2 | 12987 | 12793 | 0 | 0 |
T3 | 10479 | 10214 | 0 | 0 |
T4 | 756283 | 756261 | 0 | 0 |
T5 | 56328 | 55462 | 0 | 0 |
T6 | 603424 | 603397 | 0 | 0 |
T8 | 13701 | 13512 | 0 | 0 |
T9 | 12421 | 12226 | 0 | 0 |
T10 | 10569 | 10342 | 0 | 0 |
T11 | 17381 | 17109 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |