Module Definition
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Module Instance : tb.dut.u_otp_rsp_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.68 100.00 94.74 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.83 100.00 92.31 95.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.82 97.40 96.15 96.92 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 93.64 100.00 90.00 90.91



Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.36 95.00 87.10 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.84 100.00 95.37 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73



Module Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.36 95.00 87.10 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.84 100.00 95.37 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73



Module Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.37 95.00 89.47 85.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.84 100.00 95.37 100.00 100.00 u_tlul_adapter_sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
98.68 100.00
tb.dut.u_otp_rsp_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T8,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T8,T9
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T8,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
98.68 94.74
tb.dut.u_otp_rsp_fifo

TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo

SCOREBRANCH
98.68 100.00
tb.dut.u_otp_rsp_fifo

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo

SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 272411805 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1796695724 41204033 0 0
gen_passthru_fifo.paramCheckPass 7950 7950 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 272411805 0 0
T1 1069020 45233 0 0
T2 129870 10179 0 0
T3 104790 8019 0 0
T4 7562830 2489874 0 0
T5 563280 47273 0 0
T6 6034240 818638 0 0
T8 137010 9475 0 0
T9 124210 5651 0 0
T10 105690 5238 0 0
T11 173810 7499 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1069020 1056790 0 0
T2 129870 127930 0 0
T3 104790 102140 0 0
T4 7562830 7562610 0 0
T5 563280 554620 0 0
T6 6034240 6033970 0 0
T8 137010 135120 0 0
T9 124210 122260 0 0
T10 105690 103420 0 0
T11 173810 171090 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1069020 1056790 0 0
T2 129870 127930 0 0
T3 104790 102140 0 0
T4 7562830 7562610 0 0
T5 563280 554620 0 0
T6 6034240 6033970 0 0
T8 137010 135120 0 0
T9 124210 122260 0 0
T10 105690 103420 0 0
T11 173810 171090 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1069020 1056790 0 0
T2 129870 127930 0 0
T3 104790 102140 0 0
T4 7562830 7562610 0 0
T5 563280 554620 0 0
T6 6034240 6033970 0 0
T8 137010 135120 0 0
T9 124210 122260 0 0
T10 105690 103420 0 0
T11 173810 171090 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1796695724 41204033 0 0
T1 427608 18297 0 0
T2 51948 3791 0 0
T3 41916 3395 0 0
T4 3025132 292636 0 0
T5 225312 13349 0 0
T6 2413696 68804 0 0
T8 54804 3535 0 0
T9 49684 2979 0 0
T10 42276 2602 0 0
T11 69524 4193 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 7950 7950 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T6 6 6 0 0
T8 6 6 0 0
T9 6 6 0 0
T10 6 6 0 0
T11 6 6 0 0

Line Coverage for Instance : tb.dut.u_otp_rsp_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_otp_rsp_fifo
TotalCoveredPercent
Conditions191894.74
Logical191894.74
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T3
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_otp_rsp_fifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp_rsp_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 449173931 17259228 0 0
DepthKnown_A 449173931 448303791 0 0
RvalidKnown_A 449173931 448303791 0 0
WreadyKnown_A 449173931 448303791 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 449173931 17259228 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 17259228 0 0
T1 106902 18091 0 0
T2 12987 3728 0 0
T3 10479 3101 0 0
T4 756283 40347 0 0
T5 56328 13166 0 0
T6 603424 15888 0 0
T8 13701 3178 0 0
T9 12421 2414 0 0
T10 10569 2065 0 0
T11 17381 3593 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 448303791 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 448303791 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 448303791 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 17259228 0 0
T1 106902 18091 0 0
T2 12987 3728 0 0
T3 10479 3101 0 0
T4 756283 40347 0 0
T5 56328 13166 0 0
T6 603424 15888 0 0
T8 13701 3178 0 0
T9 12421 2414 0 0
T10 10569 2065 0 0
T11 17381 3593 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 452398705 59859030 0 0
DepthKnown_A 452398705 451472557 0 0
RvalidKnown_A 452398705 451472557 0 0
WreadyKnown_A 452398705 451472557 0 0
gen_passthru_fifo.paramCheckPass 1325 1325 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 59859030 0 0
T1 106902 2411 0 0
T2 12987 1597 0 0
T3 10479 1156 0 0
T4 756283 121668 0 0
T5 56328 8481 0 0
T6 603424 271515 0 0
T8 13701 542 0 0
T9 12421 637 0 0
T10 10569 635 0 0
T11 17381 792 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1325 1325 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 452398705 60560297 0 0
DepthKnown_A 452398705 451472557 0 0
RvalidKnown_A 452398705 451472557 0 0
WreadyKnown_A 452398705 451472557 0 0
gen_passthru_fifo.paramCheckPass 1325 1325 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 60560297 0 0
T1 106902 11057 0 0
T2 12987 1597 0 0
T3 10479 1156 0 0
T4 756283 554684 0 0
T5 56328 8481 0 0
T6 603424 130069 0 0
T8 13701 2428 0 0
T9 12421 699 0 0
T10 10569 683 0 0
T11 17381 861 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1325 1325 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 452398705 25090941 0 0
DepthKnown_A 452398705 451472557 0 0
RvalidKnown_A 452398705 451472557 0 0
WreadyKnown_A 452398705 451472557 0 0
gen_passthru_fifo.paramCheckPass 1325 1325 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 25090941 0 0
T1 106902 8 0 0
T2 12987 3 0 0
T3 10479 14 0 0
T4 756283 530973 0 0
T5 56328 49 0 0
T6 603424 111222 0 0
T8 13701 13 0 0
T9 12421 21 0 0
T10 10569 21 0 0
T11 17381 22 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1325 1325 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 452398705 22404217 0 0
DepthKnown_A 452398705 451472557 0 0
RvalidKnown_A 452398705 451472557 0 0
WreadyKnown_A 452398705 451472557 0 0
gen_passthru_fifo.paramCheckPass 1325 1325 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 22404217 0 0
T1 106902 36 0 0
T2 12987 3 0 0
T3 10479 14 0 0
T4 756283 250969 0 0
T5 56328 49 0 0
T6 603424 52560 0 0
T8 13701 55 0 0
T9 12421 83 0 0
T10 10569 69 0 0
T11 17381 91 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1325 1325 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 452398705 25137207 0 0
DepthKnown_A 452398705 451472557 0 0
RvalidKnown_A 452398705 451472557 0 0
WreadyKnown_A 452398705 451472557 0 0
gen_passthru_fifo.paramCheckPass 1325 1325 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 25137207 0 0
T1 106902 2403 0 0
T2 12987 1594 0 0
T3 10479 1142 0 0
T4 756283 435229 0 0
T5 56328 8432 0 0
T6 603424 106959 0 0
T8 13701 529 0 0
T9 12421 616 0 0
T10 10569 614 0 0
T11 17381 770 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1325 1325 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 452398705 38156080 0 0
DepthKnown_A 452398705 451472557 0 0
RvalidKnown_A 452398705 451472557 0 0
WreadyKnown_A 452398705 451472557 0 0
gen_passthru_fifo.paramCheckPass 1325 1325 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 38156080 0 0
T1 106902 11021 0 0
T2 12987 1594 0 0
T3 10479 1142 0 0
T4 756283 303715 0 0
T5 56328 8432 0 0
T6 603424 77509 0 0
T8 13701 2373 0 0
T9 12421 616 0 0
T10 10569 614 0 0
T11 17381 770 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 452398705 451472557 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1325 1325 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T3
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 449173931 22967796 0 0
DepthKnown_A 449173931 448303791 0 0
RvalidKnown_A 449173931 448303791 0 0
WreadyKnown_A 449173931 448303791 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 449173931 22967796 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 22967796 0 0
T1 106902 99 0 0
T2 12987 30 0 0
T3 10479 140 0 0
T4 756283 251358 0 0
T5 56328 67 0 0
T6 603424 52632 0 0
T8 13701 172 0 0
T9 12421 272 0 0
T10 10569 258 0 0
T11 17381 289 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 448303791 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 448303791 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 448303791 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 22967796 0 0
T1 106902 99 0 0
T2 12987 30 0 0
T3 10479 140 0 0
T4 756283 251358 0 0
T5 56328 67 0 0
T6 603424 52632 0 0
T8 13701 172 0 0
T9 12421 272 0 0
T10 10569 258 0 0
T11 17381 289 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T3
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 449173931 692063 0 0
DepthKnown_A 449173931 448303791 0 0
RvalidKnown_A 449173931 448303791 0 0
WreadyKnown_A 449173931 448303791 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 449173931 692063 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 692063 0 0
T1 106902 71 0 0
T2 12987 30 0 0
T3 10479 140 0 0
T4 756283 660 0 0
T5 56328 67 0 0
T6 603424 178 0 0
T8 13701 130 0 0
T9 12421 210 0 0
T10 10569 210 0 0
T11 17381 220 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 448303791 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 448303791 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 448303791 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 692063 0 0
T1 106902 71 0 0
T2 12987 30 0 0
T3 10479 140 0 0
T4 756283 660 0 0
T5 56328 67 0 0
T6 603424 178 0 0
T8 13701 130 0 0
T9 12421 210 0 0
T10 10569 210 0 0
T11 17381 220 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
TotalCoveredPercent
Conditions1818100.00
Logical1818100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T8,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T8,T9
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T8,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 449173931 284946 0 0
DepthKnown_A 449173931 448303791 0 0
RvalidKnown_A 449173931 448303791 0 0
WreadyKnown_A 449173931 448303791 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 449173931 284946 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 284946 0 0
T1 106902 36 0 0
T2 12987 3 0 0
T3 10479 14 0 0
T4 756283 271 0 0
T5 56328 49 0 0
T6 603424 106 0 0
T8 13701 55 0 0
T9 12421 83 0 0
T10 10569 69 0 0
T11 17381 91 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 448303791 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 448303791 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 448303791 0 0
T1 106902 105679 0 0
T2 12987 12793 0 0
T3 10479 10214 0 0
T4 756283 756261 0 0
T5 56328 55462 0 0
T6 603424 603397 0 0
T8 13701 13512 0 0
T9 12421 12226 0 0
T10 10569 10342 0 0
T11 17381 17109 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 449173931 284946 0 0
T1 106902 36 0 0
T2 12987 3 0 0
T3 10479 14 0 0
T4 756283 271 0 0
T5 56328 49 0 0
T6 603424 106 0 0
T8 13701 55 0 0
T9 12421 83 0 0
T10 10569 69 0 0
T11 17381 91 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%