Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25113832

1

T1

471

T2

47779

T3

2223

full_word

8199362

1

T1

401

T2

32775

T3

1203

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33312894	1			T1	872		T2	80554		T3	3426
auto[TlIntgErrCmd]	108	1			T271	3		T272	1		T273	4
auto[TlIntgErrData]	81	1			T271	1		T272	3		T273	4
auto[TlIntgErrBoth]	111	1			T271	6		T272	6		T273	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9752554

1

T1

719

T2

70943

T3

3083

auto[1]

23560640

1

T1

153

T2

9611

T3

343

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6195546	1			T1	382		T2	42101		T3	2016
auto[TlIntgErrNone]	partial	auto[1]	18918005	1			T1	89		T2	5678		T3	207
auto[TlIntgErrNone]	full_word	auto[0]	3556877	1			T1	337		T2	28842		T3	1067
auto[TlIntgErrNone]	full_word	auto[1]	4642466	1			T1	64		T2	3933		T3	136
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T346	3		T347	2		T277	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T271	2		T272	1		T273	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T278	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T271	1		T278	1		T350	2
auto[TlIntgErrData]	partial	auto[0]	43	1			T271	1		T272	1		T273	2
auto[TlIntgErrData]	partial	auto[1]	32	1			T272	2		T273	2		T347	1
auto[TlIntgErrData]	full_word	auto[0]	1	1			T351	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T277	1		T278	1		T352	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T271	2		T272	2		T273	1
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T271	4		T272	4		T273	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T353	1		T351	2		T354	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T348	1		-	-		-	-