Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.81	97.40	96.15	96.88		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	483193334	8022540	0	0
check_regwen_rd_A	483193334	2520	0	0
check_timeout_rd_A	483193334	2459	0	0
check_trigger_regwen_rd_A	483193334	2421	0	0
consistency_check_period_rd_A	483193334	2705	0	0
creator_sw_cfg_read_lock_rd_A	483193334	2350	0	0
direct_access_address_rd_A	483193334	1871	0	0
direct_access_wdata_0_rd_A	483193334	1204	0	0
direct_access_wdata_1_rd_A	483193334	1304	0	0
integrity_check_period_rd_A	483193334	2600	0	0
intr_enable_rd_A	483193334	3240	0	0
owner_sw_cfg_read_lock_rd_A	483193334	1911	0	0
rot_creator_auth_codesign_read_lock_rd_A	483193334	2510	0	0
rot_creator_auth_state_read_lock_rd_A	483193334	2284	0	0
vendor_test_read_lock_rd_A	483193334	2384	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	8022540	0	0
T12	115924	78657	0	0
T13	251061	38935	0	0
T14	0	46834	0	0
T15	0	72170	0	0
T18	0	82098	0	0
T26	0	157581	0	0
T35	0	209356	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T132	0	54614	0	0
T250	12118	0	0	0
T256	0	21294	0	0
T280	0	14814	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	2520	0	0
T12	115924	102	0	0
T13	251061	0	0	0
T18	0	47	0	0
T35	0	219	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T169	0	147	0	0
T216	0	86	0	0
T250	12118	0	0	0
T256	0	34	0	0
T257	0	16	0	0
T280	0	13	0	0
T284	0	82	0	0
T285	0	42	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	2459	0	0
T12	115924	96	0	0
T13	251061	0	0	0
T18	0	81	0	0
T35	0	190	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T169	0	215	0	0
T216	0	114	0	0
T250	12118	0	0	0
T256	0	49	0	0
T257	0	40	0	0
T280	0	21	0	0
T284	0	116	0	0
T285	0	55	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	2421	0	0
T12	115924	51	0	0
T13	251061	0	0	0
T18	0	59	0	0
T35	0	277	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T169	0	138	0	0
T216	0	74	0	0
T250	12118	0	0	0
T256	0	31	0	0
T257	0	44	0	0
T280	0	28	0	0
T284	0	86	0	0
T285	0	62	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	2705	0	0
T12	115924	89	0	0
T13	251061	0	0	0
T18	0	70	0	0
T35	0	190	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T169	0	189	0	0
T216	0	116	0	0
T250	12118	0	0	0
T256	0	36	0	0
T257	0	29	0	0
T280	0	41	0	0
T284	0	103	0	0
T285	0	40	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	2350	0	0
T12	115924	122	0	0
T13	251061	0	0	0
T18	0	66	0	0
T35	0	224	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T169	0	194	0	0
T216	0	90	0	0
T250	12118	0	0	0
T256	0	40	0	0
T257	0	44	0	0
T280	0	20	0	0
T284	0	90	0	0
T285	0	69	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	1871	0	0
T12	115924	77	0	0
T13	251061	0	0	0
T18	0	62	0	0
T35	0	262	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T169	0	182	0	0
T216	0	107	0	0
T250	12118	0	0	0
T256	0	27	0	0
T257	0	33	0	0
T280	0	40	0	0
T284	0	189	0	0
T285	0	89	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	1204	0	0
T12	115924	85	0	0
T13	251061	0	0	0
T18	0	29	0	0
T35	0	206	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T169	0	123	0	0
T216	0	66	0	0
T250	12118	0	0	0
T256	0	14	0	0
T257	0	19	0	0
T280	0	27	0	0
T284	0	71	0	0
T285	0	38	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	1304	0	0
T12	115924	80	0	0
T13	251061	0	0	0
T18	0	31	0	0
T35	0	214	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T169	0	141	0	0
T216	0	92	0	0
T250	12118	0	0	0
T256	0	24	0	0
T257	0	20	0	0
T280	0	12	0	0
T284	0	88	0	0
T285	0	44	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	2600	0	0
T12	115924	83	0	0
T13	251061	0	0	0
T18	0	41	0	0
T35	0	195	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T169	0	203	0	0
T216	0	122	0	0
T250	12118	0	0	0
T256	0	35	0	0
T257	0	26	0	0
T280	0	30	0	0
T284	0	85	0	0
T285	0	69	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	3240	0	0
T12	115924	96	0	0
T13	251061	0	0	0
T18	0	60	0	0
T35	0	249	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T98	0	23	0	0
T169	0	172	0	0
T216	0	90	0	0
T250	12118	0	0	0
T256	0	57	0	0
T257	0	32	0	0
T280	0	49	0	0
T331	0	26	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	1911	0	0
T12	115924	85	0	0
T13	251061	0	0	0
T18	0	44	0	0
T35	0	176	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T169	0	122	0	0
T216	0	110	0	0
T250	12118	0	0	0
T256	0	28	0	0
T257	0	23	0	0
T280	0	36	0	0
T284	0	84	0	0
T285	0	47	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	2510	0	0
T12	115924	111	0	0
T13	251061	0	0	0
T18	0	27	0	0
T35	0	216	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T169	0	246	0	0
T216	0	140	0	0
T250	12118	0	0	0
T256	0	45	0	0
T257	0	13	0	0
T280	0	37	0	0
T284	0	153	0	0
T285	0	60	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	2284	0	0
T12	115924	82	0	0
T13	251061	0	0	0
T18	0	70	0	0
T35	0	208	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T169	0	141	0	0
T216	0	119	0	0
T250	12118	0	0	0
T256	0	42	0	0
T257	0	12	0	0
T280	0	36	0	0
T284	0	152	0	0
T285	0	53	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	2384	0	0
T12	115924	104	0	0
T13	251061	0	0	0
T18	0	44	0	0
T35	0	191	0	0
T43	17001	0	0	0
T76	14775	0	0	0
T79	14438	0	0	0
T89	56553	0	0	0
T90	30748	0	0	0
T91	4101	0	0	0
T92	30778	0	0	0
T169	0	191	0	0
T216	0	134	0	0
T250	12118	0	0	0
T256	0	47	0	0
T257	0	25	0	0
T280	0	70	0	0
T284	0	101	0	0
T285	0	73	0	0