SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_rsp_intg_gen |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_data_gen | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.84 | 100.00 | 95.37 | 100.00 | 100.00 | u_tlul_adapter_sram |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_data_gen | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.84 | 100.00 | 95.37 | 100.00 | 100.00 | u_tlul_adapter_sram |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_data_gen | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_intg_gen |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_data_gen | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_rsp_intg_gen |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_data_gen | 100.00 | 100.00 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |