Unified Coverage Report :: Module

Line Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Module : prim_subreg ( parameter DW=11,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_direct_access_address

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field4

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 + DW=1,SwAccess=5,RESVAL=1,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_state_otp_operation_done

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_state_otp_error

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_enable_otp_operation_done

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_enable_otp_error

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field0

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field1

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field2

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field1

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field3

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr2

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_check_trigger_regwen

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_check_regwen

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_vendor_test_read_lock

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_creator_sw_cfg_read_lock

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_owner_sw_cfg_read_lock

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_rot_creator_auth_codesign_read_lock

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_rot_creator_auth_state_read_lock

SCORE	COND
94.44	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3

SCORE	COND
94.44	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4

SCORE	COND
94.44	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5

SCORE	COND
94.44	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6

SCORE	COND
94.44	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7

SCORE	COND
94.44	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8

SCORE	COND
94.44	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2

SCORE	COND
94.44	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4

SCORE	COND
94.44	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5

SCORE	COND
94.44	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2

SCORE	COND
94.44	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_direct_access_wdata_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_direct_access_wdata_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_check_timeout

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_integrity_check_period

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_consistency_check_period

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=16,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field4

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T14

Cond Coverage for Module : prim_subreg ( parameter DW=10,SwAccess=0,RESVAL=0,Mubi=0 + DW=10,SwAccess=3,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field3

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T14

Cond Coverage for Module : prim_subreg ( parameter DW=7,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field0

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field2

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T14

Cond Coverage for Module : prim_subreg ( parameter DW=3,SwAccess=3,RESVAL=0,Mubi=0 + DW=3,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0

SCORE	COND
94.44	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3

SCORE	COND
94.44	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T14

Cond Coverage for Module : prim_subreg ( parameter DW=2,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T14

Cond Coverage for Module : prim_subreg ( parameter DW=6,SwAccess=0,RESVAL=0,Mubi=0 + DW=6,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0

SCORE	COND
94.44	100.00

tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T14

Branch Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3	94.44	83.33	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4	94.44	83.33	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5	94.44	83.33	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6	94.44	83.33	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7	94.44	83.33	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8	94.44	83.33	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2	94.44	83.33	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3	94.44	83.33	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4	94.44	83.33	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5	94.44	83.33	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0	94.44	83.33	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1	94.44	83.33	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field2	94.44	83.33	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr7_field3	94.44	83.33	100.00			100.00
tb.dut.u_reg_core.u_intr_state_otp_operation_done	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_intr_state_otp_error	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_intr_enable_otp_operation_done	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_intr_enable_otp_error	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_direct_access_address	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_direct_access_wdata_0	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_direct_access_wdata_1	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_check_trigger_regwen	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_check_regwen	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_check_timeout	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_integrity_check_period	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_consistency_check_period	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_vendor_test_read_lock	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_creator_sw_cfg_read_lock	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_owner_sw_cfg_read_lock	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_rot_creator_auth_codesign_read_lock	100.00	100.00	100.00			100.00
tb.dut.u_reg_core.u_rot_creator_auth_state_read_lock	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field0	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field1	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field2	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field3	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr0_field4	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field0	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field1	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field2	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field3	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr1_field4	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr2	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2	100.00	100.00	100.00			100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3	100.00	100.00	100.00			100.00