Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.97	100.00	71.88			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_rsp_fifo	98.68	100.00	94.74			100.00	100.00
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_otp_rsp_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.68	100.00	94.74			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.83	100.00	92.31			95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.81	97.40	96.15	96.88		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

---

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.36	95.00	87.10			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.84	100.00	95.37			100.00	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.36	95.00	87.10			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.84	100.00	95.37			100.00	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.37	95.00	89.47			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.84	100.00	95.37			100.00	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
98.68	100.00

tb.dut.u_otp_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
98.68	94.74

tb.dut.u_otp_rsp_fifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_rspfifo

SCORE	BRANCH
98.68	100.00

tb.dut.u_otp_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_reqfifo

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	264117670	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1921184516	38128800	0	0
gen_passthru_fifo.paramCheckPass	7950	7950	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	264117670	0	0
T1	128320	6715	0	0
T2	9846970	523621	0	0
T3	708120	26643	0	0
T4	135200	5970	0	0
T5	1454000	148915	0	0
T7	118040	10657	0	0
T8	144050	8309	0	0
T9	1706330	141643	0	0
T10	508340	44607	0	0
T11	163590	11421	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	128320	125620	0	0
T2	9846970	9741800	0	0
T3	708120	700110	0	0
T4	135200	132140	0	0
T5	1454000	1436230	0	0
T7	118040	115070	0	0
T8	144050	141410	0	0
T9	1706330	1692250	0	0
T10	508340	503890	0	0
T11	163590	160860	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	128320	125620	0	0
T2	9846970	9741800	0	0
T3	708120	700110	0	0
T4	135200	132140	0	0
T5	1454000	1436230	0	0
T7	118040	115070	0	0
T8	144050	141410	0	0
T9	1706330	1692250	0	0
T10	508340	503890	0	0
T11	163590	160860	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	128320	125620	0	0
T2	9846970	9741800	0	0
T3	708120	700110	0	0
T4	135200	132140	0	0
T5	1454000	1436230	0	0
T7	118040	115070	0	0
T8	144050	141410	0	0
T9	1706330	1692250	0	0
T10	508340	503890	0	0
T11	163590	160860	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1921184516	38128800	0	0
T1	51328	3227	0	0
T2	3938788	200173	0	0
T3	283248	12883	0	0
T4	54080	3040	0	0
T5	581600	50535	0	0
T7	47216	4569	0	0
T8	57620	4625	0	0
T9	682532	18677	0	0
T10	203336	7653	0	0
T11	65436	3245	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	7950	7950	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T7	6	6	0	0
T8	6	6	0	0
T9	6	6	0	0
T10	6	6	0	0
T11	6	6	0	0

Line Coverage for Instance : tb.dut.u_otp_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_otp_rsp_fifo

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_otp_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_otp_rsp_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	480296129	16817828	0	0
DepthKnown_A	480296129	479436668	0	0
RvalidKnown_A	480296129	479436668	0	0
WreadyKnown_A	480296129	479436668	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	480296129	16817828	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	16817828	0	0
T1	12832	3218	0	0
T2	984697	193211	0	0
T3	70812	12539	0	0
T4	13520	2648	0	0
T5	145400	40992	0	0
T7	11804	4086	0	0
T8	14405	3969	0	0
T9	170633	17215	0	0
T10	50834	7400	0	0
T11	16359	2527	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	479436668	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	479436668	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	479436668	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	16817828	0	0
T1	12832	3218	0	0
T2	984697	193211	0	0
T3	70812	12539	0	0
T4	13520	2648	0	0
T5	145400	40992	0	0
T7	11804	4086	0	0
T8	14405	3969	0	0
T9	170633	17215	0	0
T10	50834	7400	0	0
T11	16359	2527	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483193334	63595455	0	0
DepthKnown_A	483193334	482281299	0	0
RvalidKnown_A	483193334	482281299	0	0
WreadyKnown_A	483193334	482281299	0	0
gen_passthru_fifo.paramCheckPass	1325	1325	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	63595455	0	0
T1	12832	872	0	0
T2	984697	80554	0	0
T3	70812	3426	0	0
T4	13520	708	0	0
T5	145400	24595	0	0
T7	11804	1522	0	0
T8	14405	883	0	0
T9	170633	11304	0	0
T10	50834	3327	0	0
T11	16359	753	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1325	1325	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483193334	54515667	0	0
DepthKnown_A	483193334	482281299	0	0
RvalidKnown_A	483193334	482281299	0	0
WreadyKnown_A	483193334	482281299	0	0
gen_passthru_fifo.paramCheckPass	1325	1325	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	54515667	0	0
T1	12832	872	0	0
T2	984697	81170	0	0
T3	70812	3454	0	0
T4	13520	757	0	0
T5	145400	24595	0	0
T7	11804	1522	0	0
T8	14405	959	0	0
T9	170633	50179	0	0
T10	50834	15150	0	0
T11	16359	3335	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1325	1325	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483193334	26780119	0	0
DepthKnown_A	483193334	482281299	0	0
RvalidKnown_A	483193334	482281299	0	0
WreadyKnown_A	483193334	482281299	0	0
gen_passthru_fifo.paramCheckPass	1325	1325	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	26780119	0	0
T1	12832	3	0	0
T2	984697	644	0	0
T3	70812	18	0	0
T4	13520	14	0	0
T5	145400	523	0	0
T7	11804	23	0	0
T8	14405	24	0	0
T9	170633	90	0	0
T10	50834	21	0	0
T11	16359	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1325	1325	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483193334	20050473	0	0
DepthKnown_A	483193334	482281299	0	0
RvalidKnown_A	483193334	482281299	0	0
WreadyKnown_A	483193334	482281299	0	0
gen_passthru_fifo.paramCheckPass	1325	1325	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	20050473	0	0
T1	12832	3	0	0
T2	984697	1260	0	0
T3	70812	46	0	0
T4	13520	63	0	0
T5	145400	523	0	0
T7	11804	23	0	0
T8	14405	100	0	0
T9	170633	398	0	0
T10	50834	89	0	0
T11	16359	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1325	1325	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483193334	26581962	0	0
DepthKnown_A	483193334	482281299	0	0
RvalidKnown_A	483193334	482281299	0	0
WreadyKnown_A	483193334	482281299	0	0
gen_passthru_fifo.paramCheckPass	1325	1325	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	26581962	0	0
T1	12832	869	0	0
T2	984697	79910	0	0
T3	70812	3408	0	0
T4	13520	694	0	0
T5	145400	24072	0	0
T7	11804	1499	0	0
T8	14405	859	0	0
T9	170633	11214	0	0
T10	50834	3306	0	0
T11	16359	727	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1325	1325	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483193334	34465194	0	0
DepthKnown_A	483193334	482281299	0	0
RvalidKnown_A	483193334	482281299	0	0
WreadyKnown_A	483193334	482281299	0	0
gen_passthru_fifo.paramCheckPass	1325	1325	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	34465194	0	0
T1	12832	869	0	0
T2	984697	79910	0	0
T3	70812	3408	0	0
T4	13520	694	0	0
T5	145400	24072	0	0
T7	11804	1499	0	0
T8	14405	859	0	0
T9	170633	49781	0	0
T10	50834	15061	0	0
T11	16359	3223	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483193334	482281299	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1325	1325	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	480296129	20521168	0	0
DepthKnown_A	480296129	479436668	0	0
RvalidKnown_A	480296129	479436668	0	0
WreadyKnown_A	480296129	479436668	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	480296129	20521168	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	20521168	0	0
T1	12832	3	0	0
T2	984697	3159	0	0
T3	70812	163	0	0
T4	13520	189	0	0
T5	145400	4510	0	0
T7	11804	230	0	0
T8	14405	316	0	0
T9	170633	686	0	0
T10	50834	116	0	0
T11	16359	346	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	479436668	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	479436668	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	479436668	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	20521168	0	0
T1	12832	3	0	0
T2	984697	3159	0	0
T3	70812	163	0	0
T4	13520	189	0	0
T5	145400	4510	0	0
T7	11804	230	0	0
T8	14405	316	0	0
T9	170633	686	0	0
T10	50834	116	0	0
T11	16359	346	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T2,T3,T4
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	480296129	587139	0	0
DepthKnown_A	480296129	479436668	0	0
RvalidKnown_A	480296129	479436668	0	0
WreadyKnown_A	480296129	479436668	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	480296129	587139	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	587139	0	0
T1	12832	3	0	0
T2	984697	2543	0	0
T3	70812	135	0	0
T4	13520	140	0	0
T5	145400	4510	0	0
T7	11804	230	0	0
T8	14405	240	0	0
T9	170633	378	0	0
T10	50834	48	0	0
T11	16359	260	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	479436668	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	479436668	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	479436668	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	587139	0	0
T1	12832	3	0	0
T2	984697	2543	0	0
T3	70812	135	0	0
T4	13520	140	0	0
T5	145400	4510	0	0
T7	11804	230	0	0
T8	14405	240	0	0
T9	170633	378	0	0
T10	50834	48	0	0
T11	16359	260	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Total	Covered	Percent
Conditions	18	18	100.00
Logical	18	18	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	480296129	202665	0	0
DepthKnown_A	480296129	479436668	0	0
RvalidKnown_A	480296129	479436668	0	0
WreadyKnown_A	480296129	479436668	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	480296129	202665	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	202665	0	0
T1	12832	3	0	0
T2	984697	1260	0	0
T3	70812	46	0	0
T4	13520	63	0	0
T5	145400	523	0	0
T7	11804	23	0	0
T8	14405	100	0	0
T9	170633	398	0	0
T10	50834	89	0	0
T11	16359	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	479436668	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	479436668	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	479436668	0	0
T1	12832	12562	0	0
T2	984697	974180	0	0
T3	70812	70011	0	0
T4	13520	13214	0	0
T5	145400	143623	0	0
T7	11804	11507	0	0
T8	14405	14141	0	0
T9	170633	169225	0	0
T10	50834	50389	0	0
T11	16359	16086	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	480296129	202665	0	0
T1	12832	3	0	0
T2	984697	1260	0	0
T3	70812	46	0	0
T4	13520	63	0	0
T5	145400	523	0	0
T7	11804	23	0	0
T8	14405	100	0	0
T9	170633	398	0	0
T10	50834	89	0	0
T11	16359	112	0	0