Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7444191	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7362065

1

T1

880

T2

293

T3

676

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8639996	1			T1	1695		T2	940		T3	1496
values[0x0]	2357059	1			T1	111		T2	48		T3	173
values[0x1]	3809201	1			T1	109		T2	32		T3	166

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4840430	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9965826

1

T1

1094

T2

500

T3

952

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	63770	1			T2	6		T3	5		T8	6
valid_sources[0x01]	68920	1			T2	2		T3	7		T8	6
valid_sources[0x02]	51553	1			T3	8		T8	6		T9	1
valid_sources[0x03]	53117	1			T2	11		T3	5		T8	4
valid_sources[0x04]	54979	1			T3	9		T8	7		T4	790
valid_sources[0x05]	55337	1			T2	2		T3	2		T8	2
valid_sources[0x06]	55476	1			T2	5		T3	13		T8	7
valid_sources[0x07]	50647	1			T3	4		T8	9		T4	276
valid_sources[0x08]	54193	1			T2	5		T3	5		T8	9
valid_sources[0x09]	56628	1			T2	2		T3	8		T8	9
valid_sources[0x0a]	65827	1			T3	3		T8	12		T4	262
valid_sources[0x0b]	52522	1			T3	8		T8	8		T4	105
valid_sources[0x0c]	53192	1			T2	1		T3	8		T8	13
valid_sources[0x0d]	57322	1			T3	12		T8	9		T4	345
valid_sources[0x0e]	55565	1			T2	12		T3	8		T8	6
valid_sources[0x0f]	51492	1			T3	5		T8	9		T4	437
valid_sources[0x10]	53011	1			T3	6		T8	7		T4	300
valid_sources[0x11]	52490	1			T3	10		T8	5		T4	1110
valid_sources[0x12]	52985	1			T3	7		T8	3		T4	354
valid_sources[0x13]	53622	1			T2	1		T3	4		T8	11
valid_sources[0x14]	53919	1			T3	6		T8	3		T4	176
valid_sources[0x15]	51391	1			T2	11		T3	4		T8	6
valid_sources[0x16]	62059	1			T2	2		T3	2		T8	10
valid_sources[0x17]	51573	1			T2	4		T3	3		T8	8
valid_sources[0x18]	56046	1			T2	1		T3	13		T8	17
valid_sources[0x19]	52961	1			T2	15		T3	9		T8	9
valid_sources[0x1a]	64632	1			T3	15		T8	10		T4	210
valid_sources[0x1b]	52002	1			T3	5		T8	7		T4	332
valid_sources[0x1c]	51857	1			T2	21		T3	4		T8	14
valid_sources[0x1d]	59187	1			T2	8		T3	5		T8	4
valid_sources[0x1e]	68287	1			T2	9		T3	2		T8	12
valid_sources[0x1f]	65217	1			T3	7		T8	6		T4	150
valid_sources[0x20]	52389	1			T2	3		T3	8		T8	6
valid_sources[0x21]	50486	1			T2	1		T3	7		T8	5
valid_sources[0x22]	52216	1			T2	2		T3	5		T8	3
valid_sources[0x23]	50812	1			T2	1		T3	10		T8	12
valid_sources[0x24]	52124	1			T2	6		T3	12		T8	14
valid_sources[0x25]	51327	1			T3	3		T8	11		T4	1028
valid_sources[0x26]	54707	1			T2	2		T3	6		T8	9
valid_sources[0x27]	56047	1			T3	10		T8	2		T4	394
valid_sources[0x28]	51083	1			T2	16		T3	9		T8	8
valid_sources[0x29]	59381	1			T2	7		T3	2		T8	4
valid_sources[0x2a]	52710	1			T2	6		T3	5		T8	12
valid_sources[0x2b]	64011	1			T2	15		T3	13		T8	9
valid_sources[0x2c]	52997	1			T3	7		T8	7		T4	1449
valid_sources[0x2d]	61774	1			T2	5		T3	4		T8	7
valid_sources[0x2e]	51613	1			T2	3		T3	2		T8	7
valid_sources[0x2f]	53708	1			T2	10		T3	10		T8	3
valid_sources[0x30]	55033	1			T3	14		T8	2		T4	275
valid_sources[0x31]	55848	1			T2	2		T3	15		T8	13
valid_sources[0x32]	57498	1			T2	4		T3	2		T8	5
valid_sources[0x33]	55734	1			T3	6		T8	7		T4	212
valid_sources[0x34]	66506	1			T3	10		T8	5		T9	2
valid_sources[0x35]	55640	1			T2	15		T3	8		T8	7
valid_sources[0x36]	50717	1			T2	1		T3	6		T8	5
valid_sources[0x37]	57505	1			T2	5		T3	4		T8	8
valid_sources[0x38]	53699	1			T3	18		T8	8		T9	2
valid_sources[0x39]	55577	1			T2	4		T3	11		T8	13
valid_sources[0x3a]	60408	1			T3	4		T8	15		T4	527
valid_sources[0x3b]	54833	1			T2	7		T3	7		T8	8
valid_sources[0x3c]	56047	1			T2	11		T3	11		T8	8
valid_sources[0x3d]	52572	1			T2	6		T3	12		T8	8
valid_sources[0x3e]	64615	1			T3	4		T8	15		T4	283
valid_sources[0x3f]	57274	1			T3	11		T8	5		T4	248
valid_sources[0x40]	63382	1			T3	7		T8	8		T4	261
valid_sources[0x41]	55459	1			T2	13		T3	9		T8	11
valid_sources[0x42]	76311	1			T2	5		T3	5		T8	7
valid_sources[0x43]	62947	1			T3	7		T8	16		T4	861
valid_sources[0x44]	56899	1			T2	5		T3	7		T8	7
valid_sources[0x45]	54142	1			T2	6		T3	5		T8	12
valid_sources[0x46]	58273	1			T3	17		T8	8		T4	668
valid_sources[0x47]	62320	1			T3	6		T8	5		T9	1
valid_sources[0x48]	66296	1			T2	3		T3	7		T8	11
valid_sources[0x49]	62906	1			T2	6		T3	8		T8	7
valid_sources[0x4a]	56877	1			T2	3		T3	5		T8	8
valid_sources[0x4b]	51388	1			T3	7		T8	3		T4	307
valid_sources[0x4c]	52611	1			T3	7		T8	8		T4	165
valid_sources[0x4d]	56065	1			T3	3		T8	6		T4	277
valid_sources[0x4e]	66269	1			T2	1		T3	8		T8	6
valid_sources[0x4f]	62251	1			T2	1		T3	6		T8	6
valid_sources[0x50]	51847	1			T2	9		T3	6		T8	8
valid_sources[0x51]	71443	1			T3	4		T8	2		T4	143
valid_sources[0x52]	53654	1			T2	5		T3	3		T8	4
valid_sources[0x53]	64517	1			T2	1		T3	10		T8	13
valid_sources[0x54]	63786	1			T2	9		T3	20		T8	5
valid_sources[0x55]	55092	1			T2	10		T3	4		T8	2
valid_sources[0x56]	57145	1			T3	9		T8	6		T4	552
valid_sources[0x57]	50912	1			T2	19		T3	5		T8	5
valid_sources[0x58]	53304	1			T2	3		T3	9		T8	16
valid_sources[0x59]	53076	1			T2	3		T3	4		T8	10
valid_sources[0x5a]	57804	1			T2	16		T3	11		T8	3
valid_sources[0x5b]	63812	1			T2	4		T3	10		T8	4
valid_sources[0x5c]	60657	1			T2	50		T3	5		T8	2
valid_sources[0x5d]	53803	1			T3	2		T8	1		T4	252
valid_sources[0x5e]	52464	1			T2	12		T3	4		T8	12
valid_sources[0x5f]	51444	1			T3	1		T8	10		T4	296
valid_sources[0x60]	65767	1			T2	6		T3	2		T8	6
valid_sources[0x61]	52941	1			T3	7		T8	4		T4	578
valid_sources[0x62]	53319	1			T2	8		T3	16		T8	10
valid_sources[0x63]	54642	1			T2	10		T3	5		T8	12
valid_sources[0x64]	53562	1			T2	5		T3	6		T8	7
valid_sources[0x65]	53697	1			T3	11		T8	8		T4	816
valid_sources[0x66]	56781	1			T2	1		T3	11		T8	6
valid_sources[0x67]	51006	1			T3	3		T8	4		T4	221
valid_sources[0x68]	51837	1			T2	13		T3	9		T8	3
valid_sources[0x69]	51172	1			T2	1		T3	3		T8	5
valid_sources[0x6a]	65875	1			T2	2		T3	8		T8	8
valid_sources[0x6b]	58116	1			T2	8		T3	4		T8	7
valid_sources[0x6c]	58443	1			T2	13		T3	14		T8	12
valid_sources[0x6d]	74009	1			T2	1		T3	7		T8	4
valid_sources[0x6e]	63569	1			T3	4		T8	6		T4	413
valid_sources[0x6f]	54077	1			T3	12		T8	11		T4	217
valid_sources[0x70]	52853	1			T3	10		T8	6		T4	324
valid_sources[0x71]	67205	1			T3	5		T8	20		T9	1
valid_sources[0x72]	56978	1			T2	2		T3	8		T8	3
valid_sources[0x73]	51097	1			T2	12		T3	8		T8	7
valid_sources[0x74]	60526	1			T2	1		T3	7		T8	17
valid_sources[0x75]	77711	1			T2	5		T3	2		T8	12
valid_sources[0x76]	50118	1			T2	14		T3	4		T8	7
valid_sources[0x77]	51207	1			T3	3		T8	10		T4	103
valid_sources[0x78]	57750	1			T2	13		T3	19		T8	5
valid_sources[0x79]	129837	1			T2	4		T3	5		T8	9
valid_sources[0x7a]	53690	1			T2	14		T3	8		T8	9
valid_sources[0x7b]	53673	1			T3	12		T8	8		T4	1076
valid_sources[0x7c]	52991	1			T2	5		T3	10		T8	13
valid_sources[0x7d]	52359	1			T2	16		T8	13		T4	266
valid_sources[0x7e]	52874	1			T3	4		T8	6		T4	362
valid_sources[0x7f]	98966	1			T3	1		T8	2		T4	237
valid_sources[0x80]	52169	1			T2	1		T3	6		T8	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3542856

1

T1

784

T2

260

T3

523

values[0x0]

all_enables

biggest_size

1950244

1

T1

57

T2

21

T3

98

values[0x1]

all_enables

biggest_size

1868965

1

T1

39

T2

12

T3

55

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	249275	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9051038

1

T1

100

T2

20

T3

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2313822	1			T1	50		T2	10		T3	20
values[0x0]	3392900	1			T1	33		T2	3		T3	9
values[0x1]	3593591	1			T1	17		T2	7		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	90209	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9210104

1

T1

100

T2

20

T3

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	36550	1			T4	470		T72	1		T160	1
valid_sources[0x01]	36834	1			T4	410		T13	840		T14	737
valid_sources[0x02]	36515	1			T4	311		T100	3		T72	1
valid_sources[0x03]	37377	1			T4	502		T27	2		T101	1
valid_sources[0x04]	36616	1			T4	440		T100	1		T27	8
valid_sources[0x05]	35191	1			T3	1		T4	324		T100	1
valid_sources[0x06]	34634	1			T3	1		T4	406		T5	1
valid_sources[0x07]	36347	1			T4	389		T27	3		T101	1
valid_sources[0x08]	36400	1			T4	420		T100	1		T13	740
valid_sources[0x09]	36743	1			T4	464		T101	2		T109	1
valid_sources[0x0a]	36955	1			T4	417		T5	1		T27	4
valid_sources[0x0b]	34937	1			T4	463		T100	3		T27	2
valid_sources[0x0c]	34450	1			T4	344		T27	2		T101	1
valid_sources[0x0d]	37982	1			T3	1		T4	491		T5	1
valid_sources[0x0e]	36331	1			T3	1		T4	661		T5	1
valid_sources[0x0f]	38312	1			T4	337		T5	1		T101	1
valid_sources[0x10]	36204	1			T4	248		T15	5		T72	1
valid_sources[0x11]	35582	1			T4	548		T100	1		T160	8
valid_sources[0x12]	36738	1			T4	321		T100	1		T101	2
valid_sources[0x13]	36256	1			T4	418		T27	9		T108	1
valid_sources[0x14]	36570	1			T4	449		T100	1		T268	1
valid_sources[0x15]	36938	1			T3	1		T4	516		T5	2
valid_sources[0x16]	38527	1			T8	1		T4	479		T100	1
valid_sources[0x17]	36560	1			T4	420		T100	1		T13	706
valid_sources[0x18]	35793	1			T4	527		T5	1		T13	632
valid_sources[0x19]	35712	1			T3	1		T4	453		T5	1
valid_sources[0x1a]	37203	1			T4	483		T101	1		T96	22
valid_sources[0x1b]	37161	1			T4	365		T5	1		T100	1
valid_sources[0x1c]	35522	1			T4	498		T52	1		T109	1
valid_sources[0x1d]	36280	1			T4	449		T5	1		T100	1
valid_sources[0x1e]	35758	1			T4	348		T100	1		T101	2
valid_sources[0x1f]	35115	1			T3	1		T4	251		T27	2
valid_sources[0x20]	36822	1			T4	253		T100	1		T27	8
valid_sources[0x21]	35712	1			T4	352		T101	2		T52	19
valid_sources[0x22]	34747	1			T4	444		T27	2		T6	48
valid_sources[0x23]	36411	1			T4	431		T5	1		T109	1
valid_sources[0x24]	36060	1			T4	328		T72	1		T257	1
valid_sources[0x25]	36583	1			T3	1		T4	442		T101	1
valid_sources[0x26]	37979	1			T4	380		T100	3		T15	9
valid_sources[0x27]	36752	1			T4	471		T100	1		T27	14
valid_sources[0x28]	36224	1			T3	1		T4	489		T101	1
valid_sources[0x29]	37106	1			T3	2		T4	454		T108	1
valid_sources[0x2a]	35946	1			T1	7		T4	546		T101	3
valid_sources[0x2b]	36302	1			T3	1		T4	391		T100	1
valid_sources[0x2c]	37066	1			T4	475		T5	1		T101	1
valid_sources[0x2d]	36796	1			T8	2		T4	400		T101	2
valid_sources[0x2e]	37030	1			T4	421		T5	2		T52	14
valid_sources[0x2f]	35818	1			T4	345		T100	1		T72	1
valid_sources[0x30]	35975	1			T1	1		T3	1		T4	429
valid_sources[0x31]	36277	1			T8	1		T4	584		T15	4
valid_sources[0x32]	36919	1			T4	403		T100	1		T27	1
valid_sources[0x33]	37653	1			T4	393		T101	1		T13	731
valid_sources[0x34]	36485	1			T4	391		T101	1		T108	1
valid_sources[0x35]	36769	1			T3	2		T4	420		T100	1
valid_sources[0x36]	33854	1			T4	335		T5	1		T15	3
valid_sources[0x37]	35499	1			T4	363		T5	2		T72	1
valid_sources[0x38]	36039	1			T4	415		T108	3		T156	2
valid_sources[0x39]	35946	1			T4	294		T100	1		T101	1
valid_sources[0x3a]	36034	1			T4	362		T108	1		T72	1
valid_sources[0x3b]	36739	1			T4	261		T100	1		T6	18
valid_sources[0x3c]	36740	1			T4	417		T6	3		T160	1
valid_sources[0x3d]	36310	1			T3	1		T4	436		T27	5
valid_sources[0x3e]	36276	1			T4	436		T52	2		T109	1
valid_sources[0x3f]	38161	1			T1	9		T4	536		T100	3
valid_sources[0x40]	37457	1			T4	468		T100	1		T101	1
valid_sources[0x41]	35676	1			T4	365		T12	25		T101	2
valid_sources[0x42]	36677	1			T1	2		T4	389		T27	8
valid_sources[0x43]	36855	1			T4	287		T101	1		T6	3
valid_sources[0x44]	35851	1			T4	409		T100	1		T6	8
valid_sources[0x45]	36823	1			T1	2		T4	386		T100	1
valid_sources[0x46]	36116	1			T1	3		T4	442		T27	2
valid_sources[0x47]	36810	1			T3	1		T4	621		T108	2
valid_sources[0x48]	35446	1			T2	20		T4	336		T101	1
valid_sources[0x49]	36413	1			T4	288		T101	1		T108	1
valid_sources[0x4a]	35395	1			T4	374		T101	1		T6	70
valid_sources[0x4b]	35746	1			T4	410		T100	3		T27	12
valid_sources[0x4c]	35852	1			T4	440		T100	1		T15	9
valid_sources[0x4d]	38505	1			T4	423		T5	2		T100	2
valid_sources[0x4e]	35331	1			T4	457		T100	3		T101	2
valid_sources[0x4f]	36916	1			T4	391		T100	2		T268	1
valid_sources[0x50]	38124	1			T4	484		T15	6		T109	2
valid_sources[0x51]	36114	1			T4	577		T160	1		T13	585
valid_sources[0x52]	35580	1			T4	501		T101	2		T36	14
valid_sources[0x53]	35468	1			T1	1		T4	406		T100	1
valid_sources[0x54]	35374	1			T4	510		T101	1		T156	1
valid_sources[0x55]	35527	1			T4	439		T101	1		T15	1
valid_sources[0x56]	35583	1			T4	256		T72	1		T13	727
valid_sources[0x57]	36452	1			T4	484		T27	4		T101	1
valid_sources[0x58]	35726	1			T1	4		T4	387		T5	1
valid_sources[0x59]	36924	1			T4	588		T100	2		T101	1
valid_sources[0x5a]	35769	1			T4	463		T101	1		T72	1
valid_sources[0x5b]	35121	1			T4	473		T100	1		T101	1
valid_sources[0x5c]	35384	1			T4	368		T101	1		T156	3
valid_sources[0x5d]	36821	1			T4	439		T100	1		T27	4
valid_sources[0x5e]	36641	1			T3	2		T4	458		T101	1
valid_sources[0x5f]	35980	1			T4	470		T27	3		T6	40
valid_sources[0x60]	37798	1			T4	367		T100	1		T27	2
valid_sources[0x61]	38714	1			T3	1		T4	356		T95	3
valid_sources[0x62]	36562	1			T4	406		T101	1		T268	1
valid_sources[0x63]	36402	1			T4	424		T5	2		T100	1
valid_sources[0x64]	36941	1			T1	1		T4	469		T100	1
valid_sources[0x65]	36839	1			T4	434		T12	17		T100	1
valid_sources[0x66]	36429	1			T3	1		T4	410		T5	3
valid_sources[0x67]	36531	1			T3	2		T4	523		T101	1
valid_sources[0x68]	36112	1			T4	382		T101	2		T72	1
valid_sources[0x69]	36114	1			T4	469		T100	3		T101	1
valid_sources[0x6a]	35601	1			T4	453		T100	2		T101	1
valid_sources[0x6b]	35748	1			T4	323		T391	20		T94	4
valid_sources[0x6c]	38923	1			T4	380		T101	1		T109	2
valid_sources[0x6d]	35280	1			T8	1		T4	403		T27	2
valid_sources[0x6e]	36459	1			T4	489		T100	1		T15	3
valid_sources[0x6f]	35643	1			T4	351		T100	1		T101	1
valid_sources[0x70]	35227	1			T3	1		T8	1		T4	644
valid_sources[0x71]	36563	1			T4	362		T100	1		T101	1
valid_sources[0x72]	34851	1			T4	442		T101	2		T72	1
valid_sources[0x73]	38006	1			T4	434		T108	1		T15	3
valid_sources[0x74]	36202	1			T1	7		T4	439		T100	1
valid_sources[0x75]	37763	1			T4	455		T265	40		T160	1
valid_sources[0x76]	35748	1			T1	3		T4	484		T108	1
valid_sources[0x77]	36143	1			T4	391		T5	2		T100	2
valid_sources[0x78]	35740	1			T4	486		T100	2		T101	1
valid_sources[0x79]	35604	1			T4	428		T100	2		T72	1
valid_sources[0x7a]	36361	1			T4	318		T100	1		T27	2
valid_sources[0x7b]	36416	1			T3	2		T4	557		T5	1
valid_sources[0x7c]	36514	1			T4	663		T101	1		T6	23
valid_sources[0x7d]	34802	1			T4	408		T100	1		T101	2
valid_sources[0x7e]	34937	1			T4	260		T5	2		T100	3
valid_sources[0x7f]	35048	1			T8	1		T4	403		T100	1
valid_sources[0x80]	34700	1			T8	2		T4	368		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2300182

1

T1

50

T2

10

T3

20

values[0x0]

all_enables

biggest_size

3375918

1

T1

33

T2

3

T3

9

values[0x1]

all_enables

biggest_size

3374938

1

T1

17

T2

7

T3

11