Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 25593029 1 T1 1035 T2 727 T3 1159
full_word 8461368 1 T1 880 T2 293 T3 676



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 34054087 1 T1 1915 T2 1020 T3 1835
auto[TlIntgErrCmd] 96 1 T274 4 T275 2 T276 6
auto[TlIntgErrData] 103 1 T274 2 T275 6 T276 5
auto[TlIntgErrBoth] 111 1 T274 4 T275 12 T276 9



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9969739 1 T1 1695 T2 940 T3 1496
auto[1] 24084658 1 T1 220 T2 80 T3 339



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 6292389 1 T1 911 T2 680 T3 973
auto[TlIntgErrNone] partial auto[1] 19300362 1 T1 124 T2 47 T3 186
auto[TlIntgErrNone] full_word auto[0] 3677206 1 T1 784 T2 260 T3 523
auto[TlIntgErrNone] full_word auto[1] 4784130 1 T1 96 T2 33 T3 153
auto[TlIntgErrCmd] partial auto[0] 43 1 T275 1 T276 3 T357 6
auto[TlIntgErrCmd] partial auto[1] 43 1 T274 3 T275 1 T276 2
auto[TlIntgErrCmd] full_word auto[0] 4 1 T274 1 T361 1 T363 1
auto[TlIntgErrCmd] full_word auto[1] 6 1 T276 1 T362 1 T361 1
auto[TlIntgErrData] partial auto[0] 45 1 T274 1 T276 1 T357 4
auto[TlIntgErrData] partial auto[1] 47 1 T274 1 T275 5 T276 3
auto[TlIntgErrData] full_word auto[0] 6 1 T275 1 T276 1 T361 2
auto[TlIntgErrData] full_word auto[1] 5 1 T357 3 T364 2 - -
auto[TlIntgErrBoth] partial auto[0] 44 1 T274 3 T275 6 T276 4
auto[TlIntgErrBoth] partial auto[1] 56 1 T274 1 T275 5 T276 3
auto[TlIntgErrBoth] full_word auto[0] 2 1 T276 1 T359 1 - -
auto[TlIntgErrBoth] full_word auto[1] 9 1 T275 1 T276 1 T361 1

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